CN117350206A - Method and equipment for generating simulation excitation file - Google Patents

Method and equipment for generating simulation excitation file Download PDF

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Publication number
CN117350206A
CN117350206A CN202210705169.1A CN202210705169A CN117350206A CN 117350206 A CN117350206 A CN 117350206A CN 202210705169 A CN202210705169 A CN 202210705169A CN 117350206 A CN117350206 A CN 117350206A
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excitation
simulation
file
time
time sequence
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陈愿
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The embodiment of the disclosure provides a method and equipment for generating a simulation excitation file, which relate to the technical field of semiconductors and comprise the following steps: determining a time sequence characteristic text corresponding to the circuit to be tested, wherein the time sequence characteristic text comprises an excitation start identifier and an excitation end identifier; simulating the circuit to be tested based on the time sequence characteristic text, and obtaining excitation start time and excitation end time according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result; generating an excitation sampling file according to the excitation start time, the excitation end time and a preset excitation signal list; and sampling a preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file. The method and the device for generating the simulation excitation file can efficiently and accurately generate the simulation excitation file, and improve the verification efficiency of the integrated circuit.

Description

Method and equipment for generating simulation excitation file
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a method and equipment for generating a simulation excitation file.
Background
At present, when integrated circuit verification is performed, a simulation excitation file is generally adopted as an input of an integrated circuit, and then whether the integrated circuit functions normally is judged by comparing output data of the integrated circuit with expected simulation data.
Along with the increasing size and complexity of integrated circuit design and verification systems, the existing simulation excitation file generation method exposes more and more defects, such as long generation time, high labor cost, and easy error. Therefore, how to efficiently and accurately generate the simulation excitation file is a technical problem to be solved at present.
Disclosure of Invention
The embodiment of the disclosure provides a method and equipment for generating a simulation excitation file, which can efficiently and accurately generate the simulation excitation file and improve the verification efficiency of an integrated circuit.
In a first aspect, an embodiment of the present disclosure provides a method for generating a simulation excitation file, where the method includes:
simulating the circuit to be tested based on the time sequence characteristic text, and obtaining excitation start time and excitation end time according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result;
generating an excitation sampling file according to the excitation starting time, the excitation ending time and a preset excitation signal list;
and sampling a preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file.
In a possible implementation manner, the determining the timing characteristic text corresponding to the circuit to be tested includes:
the original time sequence characteristic text corresponding to the circuit to be tested is obtained, and the excitation start identifier and the excitation end identifier are respectively added to the time sequence starting position and the time sequence ending position of the original time sequence characteristic text to obtain the time sequence characteristic text.
In a possible implementation manner, the sampling the preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file includes:
sampling the preset excitation signal based on the excitation sampling file to generate a first file;
and adjusting the first file according to a simulation excitation file format which can be identified by the target simulation tool to obtain the simulation excitation file.
In a possible implementation manner, before the simulating the circuit under test based on the timing characteristic text, the method further includes:
determining a simulation clock signal of the circuit to be tested in a simulation process, wherein the frequency of the simulation clock signal is N times of the frequency of a clock signal adopted when the circuit to be tested is in a preset working mode; wherein N is a positive integer.
In a possible implementation, the adjusting the first file according to the simulation stimulus file format recognizable by the target simulation tool includes:
deleting a sampling value corresponding to the simulation clock signal in the first file;
according to the duration of the initialization flow corresponding to the target simulation tool, adjusting each excitation time in the first file;
vector timing feature definition data and waveform parameter setting data are added to the first file.
In a possible embodiment, the method further includes:
determining the operation time of each command in the time sequence characteristic text;
and adding the commands into the simulation excitation file according to the operation time of the commands and the excitation time of the simulation excitation file.
In a possible implementation manner, before the simulating the circuit under test based on the timing characteristic text, the method further includes:
determining expected simulation data corresponding to the time sequence feature text, and adding the expected simulation data into the time sequence feature text;
after the circuit to be tested is simulated based on the time sequence characteristic text, the method further comprises the following steps:
and acquiring the expected simulation data from the simulation result according to the keywords corresponding to the expected simulation data.
In a possible embodiment, the method further includes:
and verifying the simulation excitation file based on a command truth table corresponding to the preset excitation signal and/or the expected simulation data.
In a second aspect, an embodiment of the present disclosure provides a generating device for a simulation excitation file, including:
the determining module is used for determining a time sequence characteristic text corresponding to the circuit to be tested, wherein the time sequence characteristic text comprises an excitation start identifier and an excitation end identifier;
the simulation module is used for simulating the circuit to be tested based on the time sequence characteristic text, and obtaining excitation start time and excitation end time according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result;
the first processing module is used for generating an excitation sampling file according to the excitation starting time, the excitation ending time and a preset excitation signal list;
and the second processing module is used for sampling a preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file.
In a possible embodiment, the determining module is configured to:
the original time sequence characteristic text corresponding to the circuit to be tested is obtained, and the excitation start identifier and the excitation end identifier are respectively added to the time sequence starting position and the time sequence ending position of the original time sequence characteristic text to obtain the time sequence characteristic text.
In a possible embodiment, the second processing module is configured to:
sampling the preset excitation signal based on the excitation sampling file to generate a first file;
and adjusting the first file according to a simulation excitation file format which can be identified by the target simulation tool to obtain the simulation excitation file.
In a possible embodiment, the device further comprises a clock module for:
determining a simulation clock signal of the circuit to be tested in a simulation process, wherein the frequency of the simulation clock signal is N times of the frequency of a clock signal adopted when the circuit to be tested is in a preset working mode; wherein N is a positive integer.
In a possible embodiment, the second processing module is configured to:
deleting a sampling value corresponding to the simulation clock signal in the first file;
according to the duration of the initialization flow corresponding to the target simulation tool, adjusting each excitation time in the first file;
vector timing feature definition data and waveform parameter setting data are added to the first file.
In a possible embodiment, the second processing module is further configured to:
determining the operation time of each command in the time sequence characteristic text;
and adding the commands into the simulation excitation file according to the operation time of the commands and the excitation time of the simulation excitation file.
In a possible embodiment, the determining module is further configured to:
determining expected simulation data corresponding to the time sequence feature text, and adding the expected simulation data into the time sequence feature text;
the simulation module is also used for:
and acquiring the expected simulation data from the simulation result according to the keywords corresponding to the expected simulation data.
In a possible implementation manner, the device further comprises a verification module, configured to:
and verifying the simulation excitation file based on a command truth table corresponding to the preset excitation signal and/or the expected simulation data.
In a third aspect, an embodiment of the present disclosure provides an electronic device, including: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executes computer-executable instructions stored by the memory, causing the at least one processor to perform the method of generating a simulated stimulus file as provided in the first aspect.
In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, implement a method for generating a simulated stimulus file as provided in the first aspect.
According to the method and the device for generating the simulation excitation file, the excitation start identifier and the excitation end identifier are added to the time sequence characteristic text corresponding to the circuit to be tested, so that after the circuit to be tested is simulated based on the time sequence characteristic text, the excitation start time and the excitation end time can be obtained according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result; according to the excitation start time, the excitation end time and the preset excitation signal list, an excitation sampling file is generated, and the preset excitation signal is sampled according to the excitation sampling file, so that a corresponding simulation excitation file can be automatically generated, a large amount of time and labor can be effectively saved, the possibility of errors is reduced, and the verification efficiency of the integrated circuit is improved.
Drawings
Fig. 1 is a schematic step flow diagram of a method for generating a simulation excitation file according to an embodiment of the present disclosure;
fig. 2 is a second step flow diagram of a method for generating a simulation excitation file according to an embodiment of the present disclosure;
fig. 3 is a step flow diagram of a method for generating a simulation excitation file according to an embodiment of the present disclosure;
FIG. 4 is a schematic program module diagram of a simulation excitation file generation apparatus according to an embodiment of the present disclosure;
fig. 5 is a schematic hardware structure of an electronic device according to an embodiment of the disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. Furthermore, while the disclosure has been presented by way of example only, it should be appreciated that various aspects of the disclosure may be separately implemented in a complete embodiment.
It should be noted that the brief description of the terms in the present disclosure is only for convenience in understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between similar or similar objects or entities and not necessarily for describing a particular sequential or chronological order, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to those elements expressly listed, but may include other elements not expressly listed or inherent to such product or apparatus.
The term "module" as used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware or/and software code that is capable of performing the function associated with that element.
The embodiment of the disclosure can be applied to the field of semiconductor technology, for example, the design verification process of an integrated circuit.
The design verification of the integrated circuit is an important link in the production of the integrated circuit, and all the integrated circuits can be put on the market after the functions and the performances of the integrated circuits are confirmed to meet the requirements.
At present, when integrated circuit verification is performed, a simulation excitation file is generally adopted as an input of an integrated circuit, output data of the integrated circuit is compared with expected simulation data, if the output data of the integrated circuit is consistent with the expected simulation data, a test result is judged to be qualified, and if the output result of a certain signal in a certain period is different from the expected simulation data, the test result is judged to be unqualified.
The simulation excitation (or testbench) file is very important for the design verification of the integrated circuit, and is the basis and input file of the whole verification process. The most basic structure of the simulation excitation file includes vector timing characteristics definition (Vector Pattern Definition), waveform parameter settings (Waveform Parameter Settings) and table Data (Tabular Data).
Along with the increasing size and complexity of integrated circuit design and verification systems, the existing simulation excitation file generation method exposes more and more defects, such as long generation time, high labor cost, and easy error.
In view of the above technical problems, the embodiments of the present disclosure provide a method for generating a simulation excitation file, which can quickly generate a simulation excitation file, thereby effectively saving a lot of time and labor, reducing the possibility of error, and improving the verification efficiency of an integrated circuit. For details, reference is made to the following examples.
Referring to fig. 1, fig. 1 is a schematic step flow diagram of a method for generating a simulation excitation file according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the method for generating the simulation excitation file includes:
s101, determining a time sequence characteristic text corresponding to a circuit to be tested, wherein the time sequence characteristic text comprises an excitation start identifier and an excitation end identifier.
The time sequence characteristic text, namely the Pattern text, comprises a command time sequence corresponding to the circuit to be tested. In the simulation process of the circuit to be tested, automatic test equipment (Automated Test Equipment, ATE) sends a series of commands to the circuit to be tested, and then judges whether the circuit to be tested meets the functions of the circuit to be tested by comparing the output time sequence of the circuit to be tested with expected simulation data.
In a possible implementation manner, the excitation start identifier and the excitation end identifier are added in advance in the time sequence characteristic text corresponding to the circuit to be tested. Wherein, the excitation start mark is added at the position of the simulation start in the time sequence feature text, and the excitation end mark is added at the position of the simulation end in the time sequence feature text.
In some embodiments of the present disclosure, the timing sequence feature text includes a simulation start command and a simulation end command, and when a simulation tool runs to the simulation start command in a simulation process of the circuit to be tested, a waveform starts to be input to the circuit to be tested; and stopping inputting the waveform to the circuit to be tested when the simulation tool runs to the simulation ending command, so that the simulation is ended. Alternatively, the excitation start identifier may be located in a line where the simulation start command is located in the time sequence feature text, and the excitation end identifier may be located in a line where the simulation end command is located in the time sequence feature text.
In some embodiments of the present disclosure, the above-described timing feature text may be written based on verilog language.
S102, simulating the circuit to be tested based on the time sequence characteristic text, and obtaining excitation start time and excitation end time according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result.
In some embodiments of the present disclosure, a preset simulation tool may be used to simulate the circuit to be tested based on the above-mentioned time sequence feature text, so as to obtain a simulation result.
Alternatively, the simulation tool may be a sign-off (sign-off) tool capable of logic and timing verification, such as a finesim simulator, etc., which is not limited herein.
In some embodiments of the present disclosure, after obtaining the simulation result, the excitation start identifier and the excitation end identifier are found in a simulation result log (log) file, and according to a time point corresponding to the excitation start identifier and the excitation end identifier in the simulation result log file, the excitation start time and the excitation end time are determined.
S103, generating an excitation sampling file according to the excitation start time, the excitation end time and a preset excitation signal list.
In some embodiments of the present disclosure, the incentive sample file may be a script file written based on verilog language.
In some embodiments of the present disclosure, the excitation sampling file defines a sampling start time, a sampling end time, and a signal name to be sampled. Wherein the sampling start time is the excitation start time, and the sampling end time is the excitation end time; the signal names required to be sampled are consistent with the signal names in the preset excitation signal list.
S104, sampling a preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file.
In some embodiments of the present disclosure, the simulation waveform of the preset excitation signal may be sampled based on the excitation sampling file, a first file is generated according to a sampling result, and then a format of the first file is adjusted according to a format of the simulation excitation file that may be identified by the target simulation tool, so as to obtain a corresponding simulation excitation file.
In some embodiments, the first file may be a Comma Separated Value (CSV) file. Wherein a CSV file typically stores tabular data (numbers and text) in plain text, whereas plain text means that the file is a sequence of characters, free of data that must be interpreted like binary digits. In addition, CSV files are typically composed of any number of records separated by some sort of linefeed; each record consists of fields, the separators between the fields are other characters or strings, most commonly commas or tab, and all records have exactly the same sequence of fields.
For example, the target simulation tool may be a Finesim simulator, and since the generated first file is not in a stimulus file format that can be directly recognized by the Finesim simulator, the first file may be adjusted according to the stimulus file format that can be recognized by the Finesim simulator, and the adjusted first file is used as a simulation stimulus file that can be recognized by the simulator.
It will be appreciated that steps S102 to S104 described above may be performed automatically by a script program without human intervention, and thus, the automated mode is efficient in saving manpower and reducing the possibility of error for generating a large number of simulation incentives.
According to the simulation excitation file generation method, the excitation start identifier and the excitation end identifier are added to the time sequence feature text corresponding to the circuit to be detected, so that after the circuit to be detected is simulated based on the time sequence feature text, the excitation start time and the excitation end time can be obtained according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result; according to the excitation start time, the excitation end time and the preset excitation signal list, an excitation sampling file is generated, and the preset excitation signals are sampled according to the excitation sampling file, so that a corresponding simulation excitation file can be automatically generated, a large amount of time and labor can be effectively saved, the possibility of errors is reduced, and the verification efficiency of the integrated circuit is improved.
Based on the descriptions in the foregoing embodiments, referring to fig. 2, fig. 2 is a second schematic step flow diagram of a method for generating a simulation excitation file according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the method for generating the simulation excitation file includes:
s201, completing preset preparation work.
In a possible embodiment, the preparation comprises:
1. determining a simulation clock signal of the circuit to be tested in a simulation process, wherein the frequency of the simulation clock signal is N times of the frequency of a clock signal adopted when the circuit to be tested is in a preset working mode; wherein N is a positive integer.
Alternatively, the frequency of the simulated clock signal may be 2 times the frequency of the clock signal used when the circuit to be tested is in the fastest operating mode.
It can be understood that the embodiment of the disclosure simulates the circuit to be tested by the frequency-doubled simulation clock signal, so that signal sampling points in the simulation process can be increased, the integrity of the sampling points is ensured, and the time sequence of the excitation signal is obtained more accurately.
2. The method comprises the steps of obtaining an original time sequence characteristic text corresponding to a circuit to be tested, and respectively adding an excitation start identifier and an excitation end identifier at a time sequence starting position and a time sequence ending position in the original time sequence characteristic text to obtain the time sequence characteristic text.
In some embodiments of the present disclosure, it is assumed that the timing characteristic text includes a simulation start command "PWRUP4FSM (150)" and a simulation end command (deselect_cmd (20)), and during a simulation of a circuit to be tested, when a simulation tool runs to the simulation start command, a corresponding command is started to be input to the circuit to be tested, including a mode register setting (Mode Register Setting, MRS) initialization, a read/write command, and the like; and stopping inputting the command to the circuit to be tested when the simulation tool runs to the simulation ending command, thereby ending the simulation. The excitation start identifier may be located in a line where a simulation start command is located in the time sequence feature text, and the excitation end identifier may be located in a line where a simulation end command is located in the time sequence feature text.
For example, assuming that the excitation Start is identified as "formulation Start" and the excitation end is identified as "formulation Done", the following may be included in the timing feature text:
in some embodiments of the present disclosure, after determining the timing characteristic text corresponding to the circuit under test, expected simulation data corresponding to the timing characteristic text may be further determined.
In some embodiments of the present disclosure, the expected simulation data may be added to the timing signature text.
3. A list of stimulus signals that need to generate a stimulus is determined.
In some embodiments of the present disclosure, signals involved in the simulated excitation file to be generated may be predetermined, and then an excitation signal list may be determined, where the excitation signal list includes signal names of the signals involved in the simulated excitation file, so as to capture corresponding signals from the simulated waveforms.
S202, simulating a circuit to be tested.
In some embodiments of the present disclosure, a preset simulation tool may be used to simulate the circuit to be tested based on the above-mentioned time sequence feature text, so as to obtain a simulation result.
Alternatively, the simulation tool may be a finesim simulator.
S203, processing the simulation result to obtain the excitation start time and the excitation end time.
In some embodiments of the present disclosure, after obtaining the simulation result, the excitation start identifier and the excitation end identifier are found in the simulation result log file, and the excitation start time and the excitation end time are determined according to time points corresponding to the excitation start identifier and the excitation end identifier in the simulation result log file.
By way of example, assume that the log file of the simulation results obtained is as follows:
203988125.0ps：top.PWRUP4FSM DESELECT cycle is 170
203988125.0ps：top.PWRUP4FSM Simulation Start
……
205135625.0ps：top.sample_Simulation＝＝＝Simulation Done＝＝＝
……
then the excitation Start time is determined to be 203988125.0ps by identifying an excitation Start mark 'Simulation Start' in the Simulation result; and determining that the excitation ending time is 205135625ps by identifying an excitation ending mark 'Simulation Done' in the Simulation result.
In some embodiments of the present disclosure, when the expected simulation data is added to the timing feature text, the expected simulation data may also be obtained from the simulation result by identifying a keyword (e.g., fineisim_check) corresponding to the expected simulation data in the simulation result.
S204, generating an excitation sampling file according to the excitation start time, the excitation end time and a preset excitation signal list.
In some embodiments of the present disclosure, the incentive sample file may be a script file written based on verilog language.
The excitation sampling file defines a sampling start time, a sampling end time, and a signal name to be sampled. Wherein the sampling start time is the excitation start time, and the sampling end time is the excitation end time; the signal names required to be sampled are consistent with the signal names in the preset excitation signal list.
S205, sampling a preset excitation signal based on the excitation sampling file, and generating a first file according to a sampling result.
In some embodiments, the first file may be a CSV file.
S206, adjusting the first file according to the format of the simulation excitation file which can be identified by the target simulation tool, and obtaining the simulation excitation file.
In some embodiments of the present disclosure, the target simulation tool may be a Finesim simulator, and since the generated CSV file is not in a stimulus file format that can be directly recognized by the Finesim simulator, the first file may be adjusted according to the stimulus file format that can be recognized by the Finesim simulator, and the adjusted first file may be used as a simulation stimulus file that can be recognized by the simulator.
In a possible implementation, if the first file is a CSV file and the target simulation tool is a Finesim simulator, the first file may be adjusted according to a stimulus file format that is recognizable by the Finesim simulator by using the following modification operations:
(1) And deleting the redundant identification of the first file head line.
(2) And replacing commas in the first file with spaces.
(3) And deleting the sampling value corresponding to the simulation clock signal in the first file.
The simulation clock signal does not exist in the circuit to be tested, and only the sampling points are added, so that two columns of sampling values corresponding to the simulation clock signal in the first file can be deleted.
(4) And adjusting each excitation time in the first file according to the duration of the initialization flow corresponding to the target simulation tool.
In some embodiments of the present disclosure, each excitation time in the first file may be transformed into a point in time of the initialization procedure corresponding to the deletion target simulation tool.
(5) Vector timing characteristics definition data (Vector Pattern Definition) and waveform parameter setting data (Waveform Parameter Setting) are added to the first file.
Through the modification operation, the simulation excitation file which can be identified by the Finesim simulator can be obtained.
It will be appreciated that steps S202 to S106 described above may be performed automatically by a script program without human intervention, and thus, the automated mode is efficient in saving manpower and reducing the possibility of error for generating a large number of simulation incentives.
In some embodiments of the present disclosure, the generated simulated stimulus file may be validated using a command truth table (Command Truth Table) to determine if the generated simulated stimulus file is accurate.
The command truth table may be used to define the relation between the bits of the physical address and the commands, including activate command, read command, write command, etc.
In some embodiments of the present disclosure, expected simulation data obtained from simulation results may also be utilized to verify the generated simulated excitation file to determine whether the generated simulated excitation file is accurate.
In some embodiments of the present disclosure, the command truth table and the expected simulation data may be used to verify the generated simulation excitation file at the same time to determine whether the generated simulation excitation file is accurate.
In some embodiments of the present disclosure, if the generated simulated stimulus file has an error, the generated simulated stimulus file may be corrected based on the command truth table or the expected simulation data.
The method for generating the simulation excitation file can automatically generate and check the simulation excitation file corresponding to the simulation waveform, so that a large amount of time and labor can be effectively saved, the possibility of errors is reduced, and the verification efficiency of the integrated circuit is improved.
Based on the descriptions in the foregoing embodiments, referring to fig. 3, fig. 3 is a schematic step flow diagram of a method for generating a simulation excitation file according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the method for generating the simulation excitation file includes:
s301, determining a time sequence characteristic text corresponding to the circuit to be tested, wherein the time sequence characteristic text comprises an excitation start identifier and an excitation end identifier.
S302, simulating the circuit to be tested based on the time sequence characteristic text, and obtaining excitation start time and excitation end time according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result.
S303, generating an excitation sampling file according to the excitation start time, the excitation end time and a preset excitation signal list.
S304, sampling a preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file.
The content executed in steps S301 to S304 is identical to the content executed in steps S101 to S104, and specific reference may be made to the description in the above embodiment, which is not repeated here.
S305, determining the operation time of each command in the time sequence feature text, and adding each command into the simulation excitation file according to the operation time of each command and each excitation time in the simulation excitation file.
It will be appreciated that one of the purposes of integrated circuit design verification is to detect the presence of a bug in a program running on an integrated circuit. In the conventional technology, in the process of debugging (debug) after the simulation is finished, a signal in a simulation waveform of a circuit to be tested is generally required to be checked to determine what a command is at a certain moment in excitation, and the debugging efficiency is low.
In some embodiments of the present disclosure, the commands are added to the simulation excitation file based on the operation time of the commands in the time sequence feature text, so that the signals in the simulation waveform can be not checked in the debugging process, and how the commands at a certain moment are determined directly from the simulation excitation file, and what is expected to be the result.
According to the method for generating the simulation excitation file, various commands in the time sequence characteristic text are added into the simulation excitation file, and compared with a common simulation excitation file, reference can be provided for later-stage circuit debugging, and the debugging efficiency is effectively improved.
Based on the foregoing description of the embodiments, the embodiment of the present disclosure further provides a device for generating a simulation excitation file, and referring to fig. 4, fig. 4 is a schematic program module diagram of the device for generating a simulation excitation file provided in the embodiment of the present disclosure, where the device for generating a simulation excitation file includes:
the determining module 401 is configured to determine a timing characteristic text corresponding to the circuit to be tested, where the timing characteristic text includes an excitation start identifier and an excitation end identifier.
And the simulation module 402 is configured to simulate the circuit to be tested based on the time sequence feature text, and obtain an excitation start time and an excitation end time according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result.
The first processing module 403 is configured to generate an excitation sampling file according to the excitation start time, the excitation end time, and a preset excitation signal list.
And the second processing module 404 is configured to sample a preset excitation signal according to the excitation sampling file, and generate a corresponding simulation excitation file.
In some embodiments of the present disclosure, the determining module 401 is configured to:
the original time sequence characteristic text corresponding to the circuit to be tested is obtained, and the excitation start identifier and the excitation end identifier are respectively added to the time sequence starting position and the time sequence ending position of the original time sequence characteristic text to obtain the time sequence characteristic text.
In some embodiments of the present disclosure, the second processing module 404 is configured to:
sampling the preset excitation signal based on the excitation sampling file to generate a first file;
and adjusting the first file according to a simulation excitation file format which can be identified by the target simulation tool to obtain the simulation excitation file.
In some embodiments of the present disclosure, a clock module is further included for:
determining a simulation clock signal of the circuit to be tested in a simulation process, wherein the frequency of the simulation clock signal is N times of the frequency of a clock signal adopted when the circuit to be tested is in a preset working mode; wherein N is a positive integer.
In some embodiments of the present disclosure, the second processing module 404 is configured to:
deleting a sampling value corresponding to the simulation clock signal in the first file;
according to the duration of the initialization flow corresponding to the target simulation tool, adjusting each excitation time in the first file;
vector timing feature definition data and waveform parameter setting data are added to the first file.
In some embodiments of the present disclosure, the second processing module 404 is further configured to:
determining the operation time of each command in the time sequence characteristic text;
and adding the commands into the simulation excitation file according to the operation time of the commands and the excitation time of the simulation excitation file.
In some embodiments of the present disclosure, the determining module 401 is further configured to:
determining expected simulation data corresponding to the time sequence feature text, and adding the expected simulation data into the time sequence feature text;
the simulation module 402 is also configured to:
and acquiring the expected simulation data from the simulation result according to the keywords corresponding to the expected simulation data.
In some embodiments of the present disclosure, the foregoing apparatus further includes a verification module configured to:
and verifying the simulation excitation file based on a command truth table corresponding to the preset excitation signal and/or the expected simulation data.
It should be noted that, in the embodiment of the disclosure, the specific execution content of the determining module 401, the simulating module 402, the first processing module 403, and the second processing module 404 may refer to the relevant content in the embodiment shown in fig. 1 to 3, which is not described herein.
Further, based on what is described in the foregoing embodiments, there is also provided in an embodiment of the disclosure an electronic device including at least one processor and a memory; wherein the memory stores computer-executable instructions; the at least one processor executes computer-executable instructions stored in the memory to implement the steps in the method for generating a simulation excitation file as described in the foregoing embodiment, which is not described herein.
For a better understanding of the embodiments of the present disclosure, referring to fig. 5, fig. 5 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present disclosure.
As shown in fig. 5, the electronic device 50 of the present embodiment includes: a processor 501 and a memory 502; wherein:
a memory 502 for storing computer-executable instructions;
the processor 501 is configured to execute the computer-executable instructions stored in the memory to implement the steps in the method for generating a simulation excitation file described in the foregoing embodiment, and specifically, reference may be made to the description related to the foregoing method embodiment.
Alternatively, the memory 502 may be separate or integrated with the processor 501.
When the memory 502 is provided separately, the device further comprises a bus 503 for connecting the memory 502 and the processor 501.
Further, based on the foregoing embodiments, a computer readable storage medium is further provided in the embodiments of the present disclosure, where computer executable instructions are stored in the computer readable storage medium, and when the processor executes the computer executable instructions, the steps in the method for generating the simulation excitation file described in the foregoing embodiments are implemented, which is not described herein again.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of modules is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple modules may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules described above as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in the embodiments of the present disclosure may be integrated in one processing unit, or each module may exist alone physically, or two or more modules may be integrated in one unit. The integrated units of the modules can be realized in a form of hardware or a form of hardware and software functional units.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (18)

1. A method for generating a simulated stimulus file, the method comprising:
determining a time sequence characteristic text corresponding to a circuit to be tested, wherein the time sequence characteristic text comprises an excitation start identifier and an excitation end identifier;
simulating the circuit to be tested based on the time sequence characteristic text, and obtaining excitation start time and excitation end time according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result;
generating an excitation sampling file according to the excitation starting time, the excitation ending time and a preset excitation signal list;
and sampling a preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file.
2. The method of claim 1, wherein determining the timing characteristic text corresponding to the circuit under test comprises:
the original time sequence characteristic text corresponding to the circuit to be tested is obtained, and the excitation start identifier and the excitation end identifier are respectively added to the time sequence starting position and the time sequence ending position of the original time sequence characteristic text to obtain the time sequence characteristic text.
3. The method of claim 1, wherein the sampling the preset excitation signal according to the excitation sampling file to generate a corresponding simulated excitation file comprises:
sampling the preset excitation signal based on the excitation sampling file to generate a first file;
and adjusting the first file according to a simulation excitation file format which can be identified by the target simulation tool to obtain the simulation excitation file.
4. The method of claim 3, wherein prior to simulating the circuit under test based on the timing characteristic text, further comprising:
determining a simulation clock signal of the circuit to be tested in a simulation process, wherein the frequency of the simulation clock signal is N times of the frequency of a clock signal adopted when the circuit to be tested is in a preset working mode; wherein N is a positive integer.
5. The method of claim 4, wherein the adjusting the first file according to a simulation stimulus file format recognizable by a target simulation tool comprises:
deleting a sampling value corresponding to the simulation clock signal in the first file;
according to the duration of the initialization flow corresponding to the target simulation tool, adjusting each excitation time in the first file;
vector timing feature definition data and waveform parameter setting data are added to the first file.
6. The method as recited in claim 1, further comprising:
determining the operation time of each command in the time sequence characteristic text;
and adding the commands into the simulation excitation file according to the operation time of the commands and the excitation time of the simulation excitation file.
7. The method of claim 1, wherein prior to simulating the circuit under test based on the timing characteristic text, further comprising:
determining expected simulation data corresponding to the time sequence feature text, and adding the expected simulation data into the time sequence feature text;
after the circuit to be tested is simulated based on the time sequence characteristic text, the method further comprises the following steps:
and acquiring the expected simulation data from the simulation result according to the keywords corresponding to the expected simulation data.
8. The method as recited in claim 7, further comprising:
and verifying the simulation excitation file based on a command truth table corresponding to the preset excitation signal and/or the expected simulation data.
9. A simulated stimulus file generation apparatus, comprising:
the determining module is used for determining a time sequence characteristic text corresponding to the circuit to be tested, wherein the time sequence characteristic text comprises an excitation start identifier and an excitation end identifier;
the simulation module is used for simulating the circuit to be tested based on the time sequence characteristic text, and obtaining excitation start time and excitation end time according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result;
the first processing module is used for generating an excitation sampling file according to the excitation starting time, the excitation ending time and a preset excitation signal list;
and the second processing module is used for sampling a preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file.
10. The apparatus of claim 9, wherein the determining module is configured to:
the original time sequence characteristic text corresponding to the circuit to be tested is obtained, and the excitation start identifier and the excitation end identifier are respectively added to the time sequence starting position and the time sequence ending position of the original time sequence characteristic text to obtain the time sequence characteristic text.
11. The apparatus of claim 9, wherein the second processing module is configured to:
sampling the preset excitation signal based on the excitation sampling file to generate a first file;
and adjusting the first file according to a simulation excitation file format which can be identified by the target simulation tool to obtain the simulation excitation file.
12. The apparatus of claim 11, further comprising a clock module to:
determining a simulation clock signal of the circuit to be tested in a simulation process, wherein the frequency of the simulation clock signal is N times of the frequency of a clock signal adopted when the circuit to be tested is in a preset working mode; wherein N is a positive integer.
13. The apparatus of claim 12, wherein the second processing module is configured to:
deleting a sampling value corresponding to the simulation clock signal in the first file;
according to the duration of the initialization flow corresponding to the target simulation tool, adjusting each excitation time in the first file;
vector timing feature definition data and waveform parameter setting data are added to the first file.
14. The apparatus of claim 9, wherein the second processing module is further configured to:
determining the operation time of each command in the time sequence characteristic text;
and adding the commands into the simulation excitation file according to the operation time of the commands and the excitation time of the simulation excitation file.
15. The apparatus of claim 9, wherein the determining module is further configured to:
determining expected simulation data corresponding to the time sequence feature text, and adding the expected simulation data into the time sequence feature text;
the simulation module is also used for:
and acquiring the expected simulation data from the simulation result according to the keywords corresponding to the expected simulation data.
16. The apparatus of claim 15, further comprising a verification module configured to:
and verifying the simulation excitation file based on a command truth table corresponding to the preset excitation signal and/or the expected simulation data.
17. An electronic device, comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing computer-executable instructions stored in the memory causes the at least one processor to perform the method of generating a simulated stimulus file according to any of claims 1 to 8.
18. A computer readable storage medium having stored therein computer executable instructions which, when executed by a processor, implement the method of generating a simulated stimulus file according to any of claims 1 to 8.
CN202210705169.1A 2022-06-21 2022-06-21 Method and equipment for generating simulation excitation file Pending CN117350206A (en)

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