CN116069635A

CN116069635A - SOC system testing method and device, computer equipment and storage medium

Info

Publication number: CN116069635A
Application number: CN202310024842.XA
Authority: CN
Inventors: 邹勇贤; 刘全木
Original assignee: Mico Microelectronics Shenzhen Co ltd
Current assignee: Mico Microelectronics Shenzhen Co ltd
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2023-05-05

Abstract

The application relates to an integrated chip test technology, and discloses a test method of an SOC system, which comprises the following steps: deploying a test scene on an SOC system, and generating a first test case corresponding to the test scene, wherein the test scene comprises at least one of a verification IP, a virtual machine compiler and an FPGA platform compiler; determining a test function according to a test requirement, and generating a second test case corresponding to the test function according to the first test case, wherein the test function comprises at least one of connection detection, time sequence detection, simulation information control, simulation waveform control, coverage rate control and DUT code control; and executing all the second test cases aiming at the SOC system to obtain a test result. The application also discloses a testing device of the SOC system, computer equipment and a computer readable storage medium. The application aims to improve the test efficiency of the SOC system.

Description

SOC system testing method and device, computer equipment and storage medium

Technical Field

The present disclosure relates to the field of integrated chip testing technologies, and in particular, to a testing method and apparatus for an SOC system, a computer device, and a computer readable storage medium.

Background

SOC (System on Chip) is referred to as a system-on-chip (or system-on-chip), meaning that it is a product, which is an integrated circuit with dedicated targets, containing the complete system and having the entire contents of embedded software. Currently, SOC is widely used in many fields such as consumer electronics, high-end manufacturing, network communication, home appliances, and internet of things. Because the SOC has the characteristics of high design technical threshold and long design period, SOC verification is an indispensable and critical ring in modern digital integrated circuit design flow.

Currently, when the SOC system is verified, when the related test environments are complex and the test functions are numerous, related engineers need to perform various functional tests one by one aiming at various test environments, and the whole process is low in efficiency.

The foregoing is merely provided to facilitate an understanding of the principles of the present application and is not admitted to be prior art.

Disclosure of Invention

The main purpose of the present application is to provide a testing method of an SOC system, a testing device of an SOC system, a computer device and a computer readable storage medium, which aim to improve the testing efficiency of an SOC system.

In order to achieve the above object, the present application provides a testing method of an SOC system, including the following steps:

deploying a test scene on an SOC system, and generating a first test case corresponding to the test scene, wherein the test scene comprises at least one of a verification IP, a virtual machine compiler and an FPGA platform compiler;

determining a test function according to a test requirement, and generating a second test case corresponding to the test function according to the first test case, wherein the test function comprises at least one of connection detection, time sequence detection, simulation information control, simulation waveform control, coverage rate control and DUT code control;

and executing all the second test cases aiming at the SOC system to obtain a test result.

Optionally, after the step of executing all the second test cases for the SOC system to obtain a test result, the method further includes:

and carrying out system iterative updating on the SOC system according to the test result.

Optionally, the step of performing system iterative updating on the SOC system according to the test result includes:

analyzing the test result by utilizing a pre-trained neural network model to obtain correction data;

performing system iterative updating on the SOC system by utilizing the correction data;

the neural network model is trained based on a plurality of training samples in advance, and each training sample comprises a test result sample and correction data corresponding to the test result sample.

Optionally, the test method of the SOC system further includes:

detecting whether the test value in the test result accords with the expected value in the second test case or not;

and if not, executing the step of carrying out system iterative updating on the SOC system according to the test result.

Optionally, after the step of performing system iterative updating on the SOC system according to the test result, the method further includes:

and returning to execute the step of deploying the test scene on the SOC system and generating a first test case corresponding to the test scene based on the updated SOC system.

In order to achieve the above object, the present application further provides a testing device of an SOC system, including:

the system comprises a test scene management module, a test scene management module and a test module, wherein the test scene management module is used for deploying a test scene on an SOC system and generating a first test case corresponding to the test scene, and the test scene comprises at least one of a verification IP, a virtual machine compiler and an FPGA platform compiler;

the test function module is used for determining a test function according to a test requirement and generating a second test case corresponding to the test function according to the first test case, wherein the test function comprises at least one of connection detection, time sequence detection, simulation information control, simulation waveform control, coverage rate control and DUT code control;

and the verification module is used for executing all the second test cases aiming at the SOC system to obtain a test result.

To achieve the above object, the present application further provides a computer apparatus, including: the system comprises a memory, a processor and a test program of the SOC system, wherein the test program of the SOC system is stored in the memory and can run on the processor, and the test program of the SOC system realizes the steps of the test method of the SOC system when being executed by the processor.

In order to achieve the above object, the present application further provides a computer readable storage medium having stored thereon a test program of an SOC system, which when executed by a processor, implements the steps of the test method of an SOC system as described above.

According to the testing method of the SOC system, the testing device of the SOC system, the computer equipment and the computer readable storage medium, the SOC system is enabled to be covered by a sufficient testing scene, and unified testing of functions such as connection detection, time sequence detection, simulation information control, simulation waveform control, coverage rate control and DUT code control can be completed by combining with management of the testing function module, and finally, a complete SOC testing flow is realized, so that useful key information extraction is realized quickly, different testing scenes are simulated and compared with each other, and the problem is positioned quickly, and therefore, the efficiency of testing the SOC system is improved.

Drawings

FIG. 1 is a schematic diagram illustrating steps of a testing method of an SOC system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a testing device of an SOC system according to an embodiment of the present application;

fig. 3 is a schematic block diagram of an internal structure of a computer device according to an embodiment of the present application.

The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to explain the present application and should not be construed as limiting the present application, and all other embodiments obtained by persons of ordinary skill in the art without creative efforts based on the embodiments in the present application are within the scope of protection of the present application.

Referring to fig. 1, in an embodiment, the test method of the SOC system includes:

step S10, deploying a test scene on an SOC system, and generating a first test case corresponding to the test scene, wherein the test scene comprises at least one of a verification IP, a virtual machine compiler and an FPGA platform compiler;

step S20, determining a test function according to a test requirement, and generating a second test case corresponding to the test function according to the first test case, wherein the test function comprises at least one of connection detection, time sequence detection, simulation information control, simulation waveform control, coverage rate control and DUT code control;

and step S30, executing all the second test cases aiming at the SOC system to obtain a test result.

In this embodiment, the terminal may be an SOC system, or may be a control device that establishes communication connection with the SOC system, or may be a test device of the SOC system.

The terminal may deploy various test scenarios on the SOC system, including at least one of a verification IP, a virtual machine compiler, and an FPGA (Field Programmable Gate Array ) platform compiler, as described in step S10.

Optionally, the verification IP (Verification IP) is to implement verification IP to replace a host (CPU (central processing unit, central processing unit) and DMA (Direct Memory Access )) through a virtual interface, and implement different access scenario tests by using UVM (Universal Verification Methodology, general verification methodology) to verify use cases. The method has good randomness under the constraint in the test environment corresponding to the verification IP, and can be applied to the debugging of the minimum SOC system to complete the test process.

Optionally, the virtual machine compiler compiles the built C code through a Linux simulation tool, and then the CPU executes the test case, so that relevant testers can conveniently expand the test case in charge of the testers based on the verification mode. Wherein, if the minimum SOC system is confirmed by the mode of verifying IP and the preparation is finished, the waveform comparison can be performed by utilizing the virtual machine compiler, so that the progress of the virtual machine compiling environment can be improved.

Optionally, the FPGA platform compiler builds engineering by using software such as Keil, compiles a C program, and then writes the C program into the FPGA platform for simulation debugging. If the FPGA simulation encounters a problem or the simulation platform needs to be confirmed again, the relevant program can be loaded to the CPU to execute the scene, so that the simulation progress is accelerated.

Optionally, the terminal can default to perform full test scene deployment on the verification IP, the virtual machine compiler and the FPGA platform compiler on the SOC system; of course, the related testers can also select at least one test scene for deployment according to actual test requirements.

Optionally, according to various test scenarios deployed on the SOC system, a corresponding test case is created for each test scenario. It should be noted that, the Test Case refers to a description of a Test task performed on a specific software product, which embodies a Test scheme, a method, a technique and a policy; the content of the method comprises a test target, a test environment, input data, a test step, an expected result, a test script and the like, and finally a document is formed. Briefly, a test case is a set of test inputs, execution conditions, and expected results tailored for a particular goal to verify that a particular software requirement is met.

Optionally, after the test scenario is deployed on the SOC system, the terminal may detect a test environment corresponding to the corresponding test scenario. In addition, the related testers can be pre-written with test case templates, test scripts corresponding to each test scene, and the like. Therefore, based on the test environment, the test case template and the test script corresponding to each test scene, the terminal can generate the test case (marked as the first test case) corresponding to each test scene.

It should be noted that the first test case does not belong to a complete test case, but lacks key contents such as a test target, a test step, an expected result, and the like, so that the first test case needs to be perfected by executing step S20.

As described in step S20, a plurality of corresponding test function modules may be provided according to the type of test function provided by the terminal. Wherein the types of test functions include at least one of wire detection, timing detection, simulation information control (the simulation information may include simulation time), simulation waveform control, coverage control, and DUT code control.

Alternatively, for the test function of the wire-bonding test, a first test function module may be established. The test logic of the first test functional module is: using UVM grammar, inputting a specific sequence signal at a source end, and detecting the specific sequence at a destination end so as to establish a correct connection relation; combining the test script to determine all signal bit widths to be checked, source end signal paths and corresponding target signal paths; the first test functional module can ensure that the expected signals are connected correctly, the test of the whole SOC system can be checked according to the needs, and the BUG caused by the connection problem can be removed rapidly especially in the initial stage of verification and the new IP integration.

Alternatively, for the test function of timing detection, a second test function module may be established. The test logic of the second test functional module is: the script language is used for eliminating time sequence violations caused by asynchronous reasons and the like, confirming the eliminated violations, retaining real violation information and realizing the rapid extraction of useful information; the second test function module can be started during the post-simulation.

Optionally, for the test function controlled by the simulation information, a third test function module may be established. The test logic of the third test functional module is: information output is carried out on the key nodes (the key nodes can help to promote the grasp of the simulation process), verification conditions are known in time, and then simulation time is controlled in time according to the key nodes; when the third test function module is matched with the first test function module, the UVM can be utilized to provide strong simulation information control, and simulation can be stopped in time when necessary; the second test function module and the third test function module are written in a C language mode, so that necessary simulation information is added in the C language when a scene is required to be written, specific behaviors of a CPU can be detected through the third test function module, simulation processes are conveniently known in time output, simulation results are judged according to node information, and meanwhile verification results Report (feedback) can be obtained along with new verification information, and therefore accurate collection of the verification results is achieved rapidly, unnecessary manual intervention of human eyes is reduced, and the efficiency of information automation management is improved.

Optionally, for the test function of the simulated waveform control, a fourth test function module may be established. The test logic of the fourth test functional module is: extracting waveform information of useful modules according to test requirements, and reducing unnecessary simulation resources; different parameters are built in advance, and dump file effective rtl (Real Time Logistics) information is controlled, so that flexible scheduling is facilitated during system simulation.

Optionally, for the coverage controlled test function, a fifth test function module may be established. The test logic of the fifth test functional module is: extracting coverage information of useful modules according to test requirements (for example, coverage information of partial modules or the whole system can be selected according to requirements); in addition, the module can manage and control the functional coverage rate and the code coverage rate, and according to the coverage rate information, a verifier is convenient to complement verification test items, and the integrity of SOC system test is improved.

Alternatively, a sixth test function module may be established for the DUT code controlled test function. The test logic of the sixth test functional module is: because DUT codes can be flexibly controlled according to the needs, minimum system codes, FPGA codes, system simulation codes, netlist after synthesis and the like can be provided; the minimum system is a simple adjustable system (integrated with a CPU, a bus and a storage module), so that the minimum system can be used as a minimum module for the engineering development of the most basic FPGA; for FPGA codes, some simulation modules have different interfaces, and the simulation modules are distinguished by definition; the system simulation code is the code actually designed and used; the Netlist code is the code used by the comprehensive back end, and can be used for verifying the Netlist of the SOC system.

Optionally, the terminal determines the function of the SOC system to be tested in each test scenario according to the test requirement. The default test requirement of the system is to perform full-function test on each test scene; of course, the related testers can also select the functions required to be tested in each test scene (at least one test function is selected in each test scene) according to the actual requirements, and write out the corresponding test requirements.

Alternatively, the selected test functions may or may not be the same for different test scenarios. For example, for a combination of test scenarios of validation IP and virtual machine compiler, the test functions for wire detection may be selected for validation IP, while the test functions for wire detection and timing detection may be selected for virtual machine compiler; or, for verifying the combination of the IP and the virtual machine compiler and the pair of test scenes, test functions such as connection line detection, time sequence detection, simulation information control, simulation waveform control, coverage rate control, DUT code control and the like can be selected.

Optionally, after the terminal determines the test function corresponding to each test scene according to the test requirement, the first test case corresponding to each test scene is perfected according to the test function corresponding to each test scene so as to generate the second test case corresponding to each test scene.

It should be understood that, according to the attribute and the test logic corresponding to the test function, the key contents such as the test target, the test step, the expected result (including the expected value) and the like corresponding to the test case can be obtained. For example, for connection detection, the corresponding test target is a certain expected signal, the test step is a test procedure described by the test logic, and the expected value is that the expected signal is correctly connected.

It should be noted that, since different test scenarios correspond to different test environments, even if the test functions are the same for different test scenarios, some values obtained by the test scenarios may be the same or different (for example, the obtained expected values may or may not be the same).

Optionally, when the same test scenario corresponds to multiple test functions, multiple second test cases may be written respectively on the basis of the corresponding first test case (for example, for the test functions a, b, and c, on the basis of the first test case a, a+a, a+b, and a+c second test cases are written); alternatively, multiple test functions may be written into a second test case based on the first test case (e.g., for a, b, and c test functions, a+ (a, b, and c) second test cases may be written based on the first test case a).

In step S30, after obtaining the second test cases corresponding to each test scenario, the terminal may aggregate all the second test cases into a test case list, and execute the second test cases sequentially by executing the test case list. When each second test case is executed, the second test case can be associated with the test function related to the second test case, and the related test function module is called for testing.

Optionally, after the second test cases are executed, the terminal may obtain a test value obtained by each second test case and an expected value written in the second test case, and compare and output the test values to generate a test result.

In an embodiment, flexible combination of test scene management and test function module management is realized through scripts (relevant testers can autonomously select corresponding test scenes and test function combinations according to proficiency of own scripts), makefile is selected for scheduling management control, and a test list of the SOC system under three test scenes is built according to a test list in a verification scheme. In the test process, if the simulation process finds problems, the relevant testers only need to return to the test list to confirm that the code modification is correct, the existing SOC function is not affected, the test efficiency of the SOC system is improved to a great extent, the convergence of the SOC system can be accelerated by the method, the problems in different stages can be positioned timely and quickly, the verification time is shortened greatly, and the test efficiency is improved.

Therefore, the SOC system obtains sufficient test scene coverage, and then combines with test function module management, so that the functional tests of detecting the correctness of an integrated connecting line, checking the correctness of a time sequence, outputting an effective log signal and controlling flexible scheduling of a simulation process, controlling useful layered waveform files, realizing complete collection of functional coverage and code coverage, flexible control of effective codes DUT at different stages of SOC integration and the like can be completed, and finally, a complete SOC test flow is realized, thereby quickly realizing useful key information extraction, simulating different test scenes and comparing with each other, and quickly positioning the problem, thereby improving the efficiency of SOC system test.

In an embodiment, based on the foregoing embodiment, after the step of executing all the second test cases for the SOC system to obtain a test result, the method further includes:

In this embodiment, after the terminal obtains the test result of the SOC system, the test result may be output to the associated device of the related tester, so as to be checked by the tester. Therefore, when a tester finds that the SOC system has problems (if a certain functional test fails), only the regression test list is needed to correct corresponding system codes so as to update the system iteration of the SOC system, and the SOC system verification environment is iterated repeatedly, so that the convergence of the SOC system is quickened, the simulation from the minimum system to the SOC code is realized, the simulation from the netlist is quickly connected, the verification efficiency of each process is improved, the problems in different stages can be quickly positioned in time, the verification time is greatly shortened, and the test efficiency is improved.

Or, the step of performing system iterative updating on the SOC system according to the test result includes:

In one embodiment, the terminal may be pre-trained with a neural network model based on artificial intelligence techniques. The neural network model is obtained through multiple iterative training based on multiple training samples (thousands of training samples).

Optionally, each training sample includes at least one test result sample, the test result samples being divided into test passing samples and test failing samples, wherein in the test passing samples, the test value meets the expected value; in test failure samples, the test value does not correspond to the expected value.

Optionally, for the test failure samples, corresponding correction data may also be included. It should be noted that, the test engineer may locate the cause of the test failure according to various test failure samples in advance, find a way of solving the test failure, and write a corresponding correction code as correction data of the SOC system.

Alternatively, the number of test passing samples and the number of test failing samples may be 1:1, may be 1:2, or 1:3 (preferably 1:3).

Therefore, when the neural network model carries out iterative training for a plurality of times based on a certain number of training samples, the correlation characteristics of the correction data corresponding to various test results can be continuously learned. And after the model training reaches convergence, the neural network model has the capability of generating corresponding correction data based on the input test result.

Optionally, after the terminal obtains the test result of the SOC system, the test result may be input to a neural network model trained in advance, so as to analyze the test result by using the neural network model, and generate corresponding correction data.

Optionally, after the terminal obtains the correction data output by the neural network model, the system iteration update can be performed on the SOC system based on the correction data.

Therefore, the automatic positioning of the test problem in the test result of the SOC system is realized, corresponding correction data is automatically generated, and the SOC system is subjected to iterative updating, so that the cost of manually positioning the test problem and modifying codes is saved, and the test efficiency can be correspondingly improved in a scene of carrying out repeated iterative tests on the SOC system (namely, after each test is finished, the system can quickly enter the next test through quick correction and updating of the system).

In an embodiment, based on the foregoing embodiment, the testing method of the SOC system further includes:

In this embodiment, after the terminal obtains the test result of the SOC system, it may first check, one by one, whether each test value in the test result corresponds to the expected value in the corresponding second test case.

Optionally, if the terminal detects that at least one test value is inconsistent with the corresponding expected value, the step of performing system iterative updating on the SOC system according to the test result may be performed, and the test result inconsistent with the test value and the corresponding second test case are output together for a tester to check, so that the tester can quickly locate problems occurring in different stages in time, return to the test list, and correct the corresponding system code to perform system iterative updating on the SOC system; or inputting the test result with the non-conforming test value into a pre-trained neural network system to generate corresponding correction data by using the neural network system, so as to perform system iterative updating on the SOC system.

Optionally, if the terminal detects that the test values of all the test results are consistent with the corresponding expected values, it may be determined that the SOC system test is passed (i.e., the SOC system reaches convergence).

In an embodiment, after the step of performing system iterative updating on the SOC system according to the test result, the method further includes:

In this embodiment, after the terminal performs system iterative update on the SOC system based on the test result, the step of deploying the test scenario on the SOC system and generating the first test case corresponding to the test scenario (i.e. returning to the execution step S10) may be performed back based on the updated SOC system until the SOC system reaches convergence, so that the SOC system verification environment may be iterated repeatedly, thereby accelerating the SOC system convergence, implementing the quick connection from the minimum system to the SOC code simulation, and then to the netlist simulation, so as to improve the verification efficiency of each process, further improve the overall test efficiency, and continuously perfect the SOC system.

Referring to fig. 2, in an embodiment of the present application, there is further provided a test device Z10 of an SOC system, including:

the test scene management module Z11 is used for deploying a test scene on the SOC system and generating a first test case corresponding to the test scene, wherein the test scene comprises at least one of a verification IP, a virtual machine compiler and an FPGA platform compiler;

the test function module Z12 is used for determining a test function according to a test requirement and generating a second test case corresponding to the test function according to the first test case, wherein the test function comprises at least one of connection detection, time sequence detection, simulation information control, simulation waveform control, coverage rate control and DUT code control;

and the verification module Z13 is used for executing all the second test cases aiming at the SOC system to obtain a test result.

Referring to fig. 3, a computer device is further provided in an embodiment of the present application, and the internal structure of the computer device may be as shown in fig. 3. The computer device includes a processor, a memory, a communication interface, and a database connected by a system bus. Wherein the processor is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used for storing a test program of the SOC system. The communication interface of the computer device is used for data communication with an external terminal. The input device of the computer device is used for receiving signals input by external equipment. The computer program, when executed by a processor, implements a method of testing an SOC system as described in the above embodiments.

Those skilled in the art will appreciate that the architecture shown in fig. 3 is merely a block diagram of a portion of the architecture in connection with the present application and is not intended to limit the computer device to which the present application is applied.

Furthermore, the present application also proposes a computer readable storage medium comprising a test program of an SOC system, which when executed by a processor implements the steps of the test method of an SOC system as described in the above embodiments. It is understood that the computer readable storage medium in this embodiment may be a volatile readable storage medium or a nonvolatile readable storage medium.

In summary, in the testing method of the SOC system, the testing device of the SOC system, the computer device and the computer readable storage medium provided in the embodiments of the present application, the SOC system is covered by a sufficient testing scene, and then, in combination with the management of the testing function module, the unified testing of functions such as connection detection, timing detection, simulation information control, simulation waveform control, coverage rate control and DUT code control can be completed, and finally, a complete SOC testing process is realized, so that useful key information extraction is rapidly realized, and different testing scenes are simulated and compared with each other, so that the problem is rapidly positioned, and the efficiency of the SOC system testing is improved.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium provided herein and used in embodiments may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, apparatus, article or method that comprises the element.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the claims, and all equivalent structures or equivalent processes using the descriptions and drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the claims of the present application.

Claims

1. A method for testing an SOC system, comprising:

2. The method for testing an SOC system of claim 1, wherein after the step of executing all the second test cases for the SOC system to obtain a test result, further comprises:

3. The method for testing the SOC system of claim 2, wherein the step of performing a system iteration update on the SOC system according to the test result includes:

4. A test method of an SOC system according to claim 2 or 3, further comprising:

5. A method for testing an SOC system according to claim 2 or 3, further comprising, after the step of performing a system iterative update on the SOC system according to the test result:

6. A test module of an SOC system, comprising:

7. A computer device comprising a memory, a processor and a test program of an SOC system stored on the memory and executable on the processor, which when executed by the processor, implements the steps of the test method of an SOC system as claimed in any of claims 1 to 5.

8. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a test program of an SOC system, which when executed by a processor, implements the steps of the test method of an SOC system according to any of claims 1 to 5.