CN116031232A

CN116031232A - Packaging carrier plate, preparation method thereof, circuit substrate, packaging structure and electronic equipment

Info

Publication number: CN116031232A
Application number: CN202111536692.8A
Authority: CN
Inventors: 李志海; 郭钜添; 解松林
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-10-27
Filing date: 2021-12-15
Publication date: 2023-04-28
Also published as: WO2023071446A1

Abstract

The application discloses a packaging carrier plate, a preparation method thereof, a circuit substrate, a packaging structure and electronic equipment. Wherein, this encapsulation carrier plate includes: the first circuit layer comprises a first dielectric layer and a metal wire filled in the hollowed-out area of the first dielectric layer; a laminated structure laminated on the first wiring layer, the laminated structure comprising: the second dielectric layer, the second circuit layer and the third dielectric layer are sequentially stacked, and the via holes penetrating through the third dielectric layer, the second circuit layer and the second dielectric layer and the conductive materials filled in the via holes; the second circuit layer comprises a fourth dielectric layer and a metal wire filled in the hollow area of the fourth dielectric layer, and the via hole penetrates through the metal wire of the second circuit layer; the first circuit layer and the second circuit layer in the stacked structure adjacent thereto are electrically connected by a conductive material. The method is used for realizing the packaging carrier plate with high circuit precision and low cost.

Description

Packaging carrier plate, preparation method thereof, circuit substrate, packaging structure and electronic equipment

Cross Reference to Related Applications

The present application claims priority from the chinese patent application with application number 202111258938.X, entitled "a package structure", filed on day 27, 10, 2021, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to semiconductor packaging technology, and more particularly, to a packaging carrier, a method for manufacturing the same, a circuit substrate, a packaging structure, and an electronic device.

Background

The packaging carrier plate is an important component of chip packaging, and along with the continuous evolution of moore's law, the process requirement of a wafer is higher and higher, and correspondingly, the processing precision of the inner-layer circuit of the packaging carrier plate is also higher and more precise. Currently, the conventional processes for manufacturing the package carrier include a subtractive Process, a Modified Semi-Additive Process (MSAP) Process, a Semi-Additive Process (SAP) Process, and the like. In the process of forming the package carrier by subtractive process, as shown in fig. 1, a dielectric layer 02 and a copper foil 03 are laminated on a carrier 01, and then drilling, electroless copper plating 04, exposure and development of a photoresist 05, electroplating copper 06, photoresist 05 removal, flash etching of a portion of the copper foil 03, and electroless copper plating 04 are sequentially performed to obtain a circuit pattern. However, the copper foil 03 used in the subtractive process is thicker, the circuit accuracy is limited when the thicker copper layer is finally etched, and in the photoetching process, the side wall of the photoresist is easy to incline after development, so that the circuit accuracy is affected, and therefore, the line width/line distance of the package carrier formed by the subtractive process can reach about 40 μm. The MSAP process for forming the package carrier is also shown in fig. 1, and is different from the subtractive process in that an ultra-thin copper foil of about 3 μm is used, so that the problem of circuit accuracy caused by photoetching a thicker copper layer can be avoided, and the circuit accuracy is improved. However, the disadvantage is that the ultra-thin copper foil is expensive, the line precision is still affected by the exposure and development factors of the photoresist, and the line width/line distance can reach about 20 μm. As shown in FIG. 2, the process of forming the package carrier by SAP technology omits ultra-thin copper foil compared with MSAP technology, and directly electroless copper plating 04 is performed on the dielectric layer 02, so that the copper layer is thinner, and the circuit precision is further improved, but the electroless copper plating 04 is performed on the dielectric layer 02 directly, the binding force is met, special materials are required to be used for the dielectric layer 02, the cost is high, the circuit precision is still influenced by photoresist exposure development factors, and the line width/line distance can reach about 10 mu m generally.

Therefore, providing a package carrier with high circuit accuracy and low cost is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The application provides a packaging carrier plate, a preparation method thereof, a circuit substrate, a packaging structure and electronic equipment, and the packaging carrier plate is used for providing the packaging carrier plate with high circuit precision and low cost.

In a first aspect, the present application provides a method for preparing a circuit substrate, which may include the steps of: providing a carrier plate, wherein the carrier plate is provided with two surfaces which are oppositely arranged; forming a metal layer on at least one of two surfaces of the carrier plate; forming a first dielectric layer on one side of each metal layer far away from the carrier plate; forming a plurality of hollowed-out areas in the first dielectric layer by adopting a laser ablation process; then, metal wiring is formed in each hollow area of the first dielectric layer. In the circuit substrate formed by the preparation method, the metal wiring is formed in the hollowed-out area in the first dielectric layer, so that the precision of the hollowed-out area determines the precision of the metal wiring in the circuit substrate, and the hollowed-out area in the first dielectric layer is formed by adopting a laser ablation process. In the specific implementation, the line width (width of the metal wires)/line distance (minimum pitch between the metal wires) can be made to be 10 μm or less.

It should be noted that, in the method for manufacturing a circuit substrate provided in the embodiment of the present application, when a metal layer, a first dielectric layer, a hollowed-out area, and a metal trace are formed on two surfaces of a carrier, the order of forming the film layers on the two surfaces is not limited, so long as the order of forming the film layers on each surface is ensured to be: the metal layer, the first dielectric layer, the hollow area and the metal wiring are all needed. For example, the metal layer, the first dielectric layer, the hollowed-out area and the metal wire may be formed on one surface in sequence, and then the metal layer, the first dielectric layer, the hollowed-out area and the metal wire may be formed on the other surface in sequence; of course, the film layers on the two surfaces may be alternately formed.

In specific implementation, the material and shape of the carrier plate are not limited, and the carrier plate is used for carrying the film layer formed later.

The material of the metal layer is not limited in this application, and may be gold, silver, copper, platinum, tin, or the like. In a specific implementation, the metal layer may be formed on the surface of the carrier plate by a lamination process, a deposition process, or the like.

The metal layer may be a copper foil layer, which may be formed on the surface of the carrier plate using a lamination process.

In a specific implementation, the first dielectric layer may be formed on the metal layer by a lamination process or a coating process using a semi-cured material.

By way of example, the material of the first dielectric layer may be a material including at least one of bismaleimide triazine resin, polyaramid fiber, epoxy resin, polyphenylene oxide, or glass fiber, without limitation.

The thickness of the first dielectric layer is not limited, and the first dielectric layer can be designed according to actual requirements. Generally, the thinner the thickness of the first dielectric layer, the higher the accuracy of the hollowed-out area formed by the laser ablation process.

The shape of the hollowed-out area in the first dielectric layer can be a hole shape, a linear shape or a groove shape, and the like, and the hollowed-out area is specifically designed according to the required pattern of the metal wiring.

The material of the metal wire is not limited in this application, and for example, the material of the metal wire may be gold, silver, copper, platinum, tin, or the like.

The manner in which the metal traces are formed is also not limited in this application. For example, since the metal layer is disposed under the first dielectric layer, the metal traces may be directly formed in each hollowed-out area of the first dielectric layer by electroplating. Therefore, the conventional electroless plating step can be omitted, and special materials are not needed, so that the method can be realized by adopting the conventional process and the conventional materials, and the cost is low.

In a second aspect, the present application further provides a circuit substrate, which may include: a carrier plate having two surfaces disposed opposite each other; a metal layer on at least one of the two surfaces; the first dielectric layer is positioned on one side of each metal layer far away from the carrier plate, and a plurality of hollowed-out areas are formed in the first dielectric layer; and metal wires filled in the hollow areas of the first dielectric layer. Because the principle of the circuit substrate for solving the problem is similar to that of the circuit substrate preparation method, the implementation of the circuit substrate can be referred to the implementation of the circuit substrate preparation method, and the repetition is omitted.

In the circuit substrate, as the metal wiring is filled in the hollowed-out area in the first dielectric layer, the precision of the hollowed-out area determines the precision of the metal wiring in the circuit substrate, and the hollowed-out area in the first dielectric layer can be formed by adopting a laser ablation process, compared with the method of forming the hollowed-out area by adopting a photoetching process, the method can avoid the influence of the exposure and development factors of photoresist on the precision, so that the circuit precision of the circuit substrate can be higher.

Further, since the circuit substrate provided by the application is high in circuit precision, the circuit substrate can be used for preparing the high-precision packaging carrier plate.

In a third aspect, the present application further provides a method for preparing a package carrier, where the method may include the following steps:

step S201, providing two circuit substrates provided in the second aspect of the present application, where each circuit substrate includes one metal layer and one first dielectric layer; one of the two circuit substrates is a first circuit substrate, and the other circuit substrate is a second circuit substrate. In specific implementation, the materials of the film layers named in the first circuit substrate and the second circuit substrate may be the same or different, for example, the materials of the first dielectric layer in the first circuit substrate and the materials of the first dielectric layer in the second circuit substrate may be the same or different, which is not limited herein. However, in practical production, a plurality of circuit substrates are generally formed on a large carrier board at the same time, and then cut to form a plurality of independent circuit substrates, so that the materials of the same named film layers in different circuit substrates are the same.

Step S202, laminating a second dielectric layer between the first circuit substrate and the second circuit substrate, wherein the carrier plate of the first circuit substrate and the carrier plate of the second circuit substrate are both positioned at one side far away from the second dielectric layer, namely, the metal wiring side of the first circuit substrate and the metal wiring side of the second circuit substrate are oppositely arranged.

In a specific implementation, the material of the second dielectric layer may be a material including at least one of bismaleimide triazine resin, polyaramid fiber, epoxy resin, polyphenylene oxide, or glass fiber, which is not limited herein.

For example, to improve the consistency of the materials between adjacent dielectric layers, the material of the second dielectric layer may be the same as the material of the first dielectric layer in the first circuit substrate and the material of the first dielectric layer in the second circuit substrate.

Step S203, removing the carrier plate and the metal layer in the second circuit substrate.

In step S204, a third dielectric layer is formed on a side of the first dielectric layer of the second circuit substrate away from the second dielectric layer.

In a specific implementation, the third dielectric layer may be formed on the metal layer by a lamination process or a coating process using a semi-cured material.

By way of example, the material of the third dielectric layer may be a material including at least one of bismaleimide triazine resin, polyaramid fiber, epoxy resin, polyphenylene oxide, or glass fiber, without limitation.

The thickness of the third dielectric layer is not limited, and can be designed according to practical requirements. Generally, the thinner the thickness of the third dielectric layer, the higher the accuracy of the hollowed-out area formed by the laser ablation process.

Step S205, forming a via hole penetrating the third dielectric layer, the metal trace in the second circuit substrate and the second dielectric layer by a laser ablation process.

In the present application, since the via hole needs to penetrate the third dielectric layer, the metal trace in the second circuit substrate, and the second dielectric layer, the thinner the thickness of the film layer that the via hole needs to penetrate, the more advantageous the improvement of the precision. Therefore, the thicknesses of the third dielectric layer, the second dielectric layer and the first dielectric layer can be set according to the performance requirements of actual products, so that the thicknesses are as thin as possible.

Step S206, forming conductive material in the via hole to electrically connect the metal trace in the first circuit substrate with the metal trace in the second circuit substrate.

The conductive material in the via is not limited in this application, and may be gold, silver, copper, platinum, tin, or the like, for example.

The formation of the conductive material in the via is not limited in this application, and any manner of forming the conductive material in the via may be implemented. Illustratively, the conductive material may be formed in the via directly by electroplating.

Step S207, removing the carrier plate and the metal layer in the first circuit substrate, thereby forming the package carrier plate.

In a specific implementation, the circuit substrate with metal traces on one side and the circuit substrate with metal traces on both sides provided in the above embodiment may also be used to prepare a package carrier, and the preparation method of the package carrier may include the following steps: step S301, three circuit substrates are provided, wherein one circuit substrate is a first circuit substrate, the other two circuit substrates are both second circuit substrates, metal wires are arranged on two sides of the first circuit substrate, and metal wires are arranged on one side of the second circuit substrate. In a specific implementation, the first circuit substrate has two sides, and for any side of the first circuit substrate, the following steps are continuously performed: step S302, a second dielectric layer is laminated between the first circuit substrate and the second circuit substrate, and the carrier of the first circuit substrate and the carrier of the second circuit substrate are both located at a side far away from the second dielectric layer, i.e. the metal wiring side of the first circuit substrate is opposite to the metal wiring side of the second circuit substrate. Step S303, removing the carrier plate and the metal layer in the second circuit substrate. Step S304, a third dielectric layer is formed on one side of the first dielectric layer of the second circuit substrate away from the second dielectric layer. Step S305, forming a via hole penetrating the third dielectric layer, the metal trace in the second circuit substrate and the second dielectric layer by a laser ablation process. Step S306, forming conductive material in the via hole to electrically connect the metal trace in the first circuit substrate with the metal trace in the second circuit substrate. Finally, after steps S302 to S306 are performed on both sides of the first circuit substrate, step S307 is performed to strip the carrier and the metal layer in the first circuit substrate, thereby forming two package carrier.

According to the preparation method provided by the embodiment of the application, since each layer of metal wiring is formed by adopting the circuit substrate provided by the application, compared with a circuit layer formed by adopting a photoetching process, the packaging carrier plate formed in the application can realize high precision of each layer of metal wiring. Also, since the metal traces are already embedded in the first dielectric layer, the third dielectric layer located between adjacent metal traces can make the thickness of the dielectric material between the two metal traces thinner than if the dielectric material is directly filled between the two metal traces. In addition, in the application, the third dielectric layer is used for replacing photoresist, and the via holes communicated with different metal wiring layers are formed through a laser ablation process, so that the accuracy of the via holes in the packaging loading plate can be improved, and the overall circuit accuracy of the packaging loading plate is improved. Finally, the bottom of the via hole is directly contacted with the metal wire, the step of conventional electroless plating can be omitted, and the conductive material can be electroplated in the via hole without using special materials, so that the conductive material can be realized by adopting the conventional process and the conventional materials, and the cost is lower.

The above embodiments of the present application are only described by taking two circuit layers formed in a package carrier as an example, and of course, a plurality of circuit layers may also be formed in the package carrier, and the method of continuously stacking the circuit layers in the package carrier may refer to steps S202 to S206. The following is a schematic description of a circuit layer stacked in the package carrier.

Further, the preparation method can further comprise: providing a third circuit substrate, wherein one side of the third circuit substrate is provided with a metal wire, and the second dielectric layer, the first dielectric layer, the metal wire, the third dielectric layer and the conductive material which are positioned above the first circuit substrate are of a first stacked structure; a second dielectric layer is pressed between the first stacking structure and the third circuit substrate, and the carrier plate of the third circuit substrate is positioned at one side far away from the first stacking structure. And removing the carrier plate and the metal layer in the third circuit substrate. A third dielectric layer is formed on the first dielectric layer of the third circuit substrate. And forming a via hole penetrating the newly formed third dielectric layer, the metal wire in the third circuit substrate and the newly formed second dielectric layer through a laser ablation process. Conductive material is formed in the via hole to electrically connect the metal trace in the second circuit substrate with the metal trace in the third circuit substrate.

And so on, the circuit layer can be continuously formed in the package carrier, and the description is omitted here.

Optionally, when stacking the last layer of wiring in the package carrier, forming a via hole penetrating the third dielectric layer, the metal wiring in the second circuit substrate and the second dielectric layer, a first via hole penetrating the third dielectric layer may be formed by a laser ablation process; and forming a second via penetrating the second dielectric layer and the metal wire in the second circuit substrate through a laser ablation process, wherein the orthographic projection of the first via on the first circuit substrate covers the orthographic projection of the second via on the first circuit substrate.

Further, in the present application, after forming the conductive material in the via hole, it may further include: and removing the third dielectric layer and the conductive material above the metal wire in the second circuit substrate. In the formed package carrier, the laminated structure only comprises the second dielectric layer and the second circuit layer, so that the thickness of the package carrier can be further reduced.

In a fourth aspect, the present application further provides a package structure, where the package carrier may include: the first circuit layer and the stacked structure stacked on the first circuit layer. The first circuit layer may include a first dielectric layer and a metal trace filled in the hollow region of the first dielectric layer. The laminated structure can comprise a second dielectric layer, a second circuit layer and a third dielectric layer which are laminated in sequence, a via hole penetrating through the third dielectric layer, the second circuit layer and the second dielectric layer, and a conductive material filled in the via hole; in the laminated structure, the second circuit layer is positioned between the second dielectric layer and the third dielectric layer, and the second dielectric layer is positioned at one side close to the first circuit layer; the second circuit layer may include a fourth dielectric layer (i.e. the first dielectric layer in the second circuit substrate used in the manufacturing process) and metal traces filled in the hollow areas of the fourth dielectric layer; the first wiring layer and the second wiring layer in the stacked structure adjacent thereto may be electrically connected by a conductive material in the via hole.

The packaging sealing plate provided by the embodiment of the application, because each layer of metal wire is formed by adopting the circuit substrate provided by the application, compared with the circuit layer formed by adopting the photoetching process, the packaging carrier plate formed in the application can realize high precision of each layer of metal wire. Also, since the metal traces are already embedded in the first dielectric layer, the third dielectric layer located between adjacent metal traces can make the thickness of the dielectric material between the two metal traces thinner than if the dielectric material is directly filled between the two metal traces. In addition, in the application, the third dielectric layer is used for replacing photoresist, and the via holes communicated with different metal wiring layers are formed through a laser ablation process, so that the accuracy of the via holes in the packaging loading plate can be improved, and the overall circuit accuracy of the packaging loading plate is improved. Finally, the bottom of the via hole is directly contacted with the metal wire, the step of conventional electroless plating can be omitted, and the conductive material can be electroplated in the via hole without using special materials, so that the conductive material can be realized by adopting the conventional process and the conventional materials, and the cost is lower.

Alternatively, in the package carrier of the present application, a multi-layered laminate structure may be laminated on the first wiring layer. Each laminated layer structure can comprise a second dielectric layer, a second circuit layer and a third dielectric layer which are laminated in sequence, a via hole penetrating through the third dielectric layer, the second circuit layer and the second dielectric layer, and a conductive material filled in the via hole; the second wiring layer in any adjacent two-layered structure is electrically connected by the conductive material in the adjacent two-layered structure.

Optionally, in the package carrier, in the stacked structure farthest from the first circuit layer, the via hole in the stacked structure includes a first via hole penetrating through the third dielectric layer, and a second via hole penetrating through the metal trace in the second circuit layer and the second dielectric layer; the orthographic projection of the first via on the first circuit layer covers the orthographic projection of the second via on the first circuit layer. This increases the area of the conductive material on the outermost side of the package carrier, thereby increasing the conductive contact area of the package carrier with other electrical devices.

In this application, solder masks and the like may be further included on both sides of the package carrier, which is not limited herein.

Optionally, in this application, in order to improve the consistency of materials, at least two dielectric layers of the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are the same. Of course, in implementation, different materials may be used for the different dielectric layers, which is not limited herein.

Optionally, in the present application, the materials of the metal traces in different circuit layers are the same. Thus, different circuit layers can be formed by adopting the same process, and the cost can be reduced.

Of course, in the implementation, the materials of the metal traces in different circuit layers may also be different.

Alternatively, in the present application, the conductive material in the via may be the same as the material of the metal trace in the wiring layer.

In a fifth aspect, the present application further provides a package structure, including a package carrier, and a chip encapsulated on one side of the package carrier, where the package carrier is a package carrier according to the fourth aspect or various embodiments of the fourth aspect. Since the principle of the package structure for solving the problem is similar to that of the aforementioned package carrier, the implementation of the package structure can be referred to the implementation of the aforementioned package carrier, and the repetition is omitted.

In one possible implementation, the package structure may be formed by: in preparing the package carrier, after a target number of wiring layers are formed on the first wiring substrate, the chips are bonded on a side away from the first wiring substrate before removing the carrier and the metal layers in the first wiring substrate. And adopting a plastic packaging material to plastic package the chip. And removing the carrier plate and the metal layer in the first circuit substrate.

Further, a solder mask layer may be formed on a side of the package carrier facing away from the chip, which is not limited herein.

Furthermore, solder balls can be implanted at one side of the packaging carrier plate away from the chip, so that the packaging structure can be conveniently welded with the circuit board subsequently.

Correspondingly, the embodiment of the application also provides another packaging structure which comprises a packaging loading plate and a chip which is molded on one side of the packaging loading plate. The package carrier may include at least one stacked layer structure, each stacked layer structure including a second dielectric layer, a circuit layer and a third dielectric layer, wherein the circuit layer includes a first dielectric layer and a metal trace filled in a hollow region of the first dielectric layer. The laminated layer structure is provided with a via hole penetrating through the second dielectric layer, the metal wire of the circuit layer and the third dielectric layer, and the via hole is filled with conductive materials.

In one possible implementation, the package structure may be formed by: and adopting a plastic packaging material to plastic package the chip. And pressing a second dielectric layer between the plastic packaging material and the circuit substrate. And removing the carrier plate and the metal layer in the circuit substrate, forming a third dielectric layer on one side of the first dielectric layer far away from the second dielectric layer, forming a via hole penetrating the third dielectric layer, the metal wire in the circuit substrate and the second dielectric layer through a laser ablation process, and forming a conductive material in the via hole, thereby forming a laminated layer structure. Then, pressing a second dielectric layer between the laminated structure and the circuit substrate; and removing the carrier plate and the metal layer in the circuit substrate, forming a third dielectric layer on one side of the first dielectric layer far away from the second dielectric layer, forming a via hole penetrating the third dielectric layer, the metal wire in the circuit substrate and the second dielectric layer through a laser ablation process, and forming a conductive material in the via hole, thereby forming a second laminated layer structure.

In a specific implementation, when the package carrier of the package structure includes a multi-layer stack structure, the steps of: pressing a second dielectric layer between the laminated structure and the circuit substrate; and removing the carrier plate and the metal layer in the circuit substrate, forming a third dielectric layer on one side of the first dielectric layer far away from the second dielectric layer, forming a via hole penetrating the third dielectric layer, the metal wire in the circuit substrate and the second dielectric layer through a laser ablation process, and forming a conductive material in the via hole. The stacked structure until the target layer number is formed is not described herein.

In a sixth aspect, the present application further provides an electronic device, including: a housing, a circuit board located within the housing, and a package structure as in various embodiments of the fifth aspect; the packaging structure is positioned on the circuit board and is electrically connected with the circuit board. Illustratively, the circuit board is a PCB. Because the principle of the electronic device for solving the problem is similar to that of the aforementioned packaging structure, the implementation of the electronic device can refer to the implementation of the aforementioned packaging structure, and the repetition is omitted.

The technical effects achieved by the fifth to sixth aspects may be described with reference to any one of the possible designs of the fourth aspect, and the description thereof is not repeated here.

Drawings

Fig. 1 is a schematic structural diagram of a manufacturing process of a package carrier in the related art;

fig. 2 is a schematic structural diagram of another manufacturing process of a package carrier in the related art;

fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 4 is a flowchart of a method for manufacturing a circuit substrate according to an embodiment of the present application;

fig. 5a to 5c are schematic structural diagrams illustrating a process for manufacturing a circuit substrate according to an embodiment of the present disclosure;

fig. 6 is a schematic top view of a first dielectric layer according to an embodiment of the present disclosure;

fig. 7 is a schematic cross-sectional structure of a circuit substrate according to an embodiment of the present disclosure;

fig. 8 is a schematic cross-sectional structure of another circuit substrate according to an embodiment of the present disclosure;

fig. 9 is a flowchart of a method for manufacturing a package carrier according to an embodiment of the present application;

fig. 10a to fig. 10e are schematic structural diagrams illustrating a manufacturing process of a package carrier according to an embodiment of the present application;

fig. 11 is a schematic cross-sectional structure of a package carrier according to an embodiment of the present disclosure;

Fig. 12 is a schematic structural diagram of directly laminating two metal wires according to an embodiment of the present disclosure;

fig. 13 is a flowchart of a method for manufacturing a package carrier according to an embodiment of the present application, in which a circuit layer is continuously formed;

fig. 14a to 14e are schematic structural diagrams illustrating a preparation process of continuously forming a circuit layer in a package carrier according to an embodiment of the present application;

fig. 15 is a schematic cross-sectional structure of another package carrier according to an embodiment of the disclosure;

FIG. 16 is a schematic cross-sectional view of a via in a package carrier according to an embodiment of the present disclosure;

fig. 17 is a schematic cross-sectional structure of another package carrier according to an embodiment of the disclosure;

fig. 18 is a schematic perspective view of a package carrier according to an embodiment of the present application;

fig. 19 is a schematic cross-sectional structure of another package carrier according to an embodiment of the disclosure;

fig. 20 is a schematic cross-sectional structure of another package carrier according to an embodiment of the disclosure;

fig. 21 is a schematic cross-sectional structure of a package structure according to an embodiment of the present disclosure;

fig. 22a and 22b are schematic structural diagrams illustrating a manufacturing process of a package structure according to an embodiment of the present application;

fig. 23 is a schematic cross-sectional structure of another package structure according to an embodiment of the disclosure;

Fig. 24 is a schematic cross-sectional structure of another package structure according to an embodiment of the disclosure;

fig. 25a to 25c are schematic structural diagrams illustrating a manufacturing process of a package structure according to an embodiment of the present application;

fig. 26 is a schematic cross-sectional structure of another package structure according to an embodiment of the present application.

Reference numerals illustrate:

1. a housing; 2, a circuit board;

3. a package structure; 10 packaging a carrier plate;

20. a chip; 101 a carrier plate;

102. a metal layer; 103 a first dielectric layer;

104. a metal wiring; 105 a second dielectric layer;

106. a third dielectric layer; 107 a conductive material;

108. a fourth dielectric layer; 1030 hollow out area;

100. a circuit substrate; 100a first circuit substrate;

100b a second circuit substrate; 100c a third circuit substrate;

v via holes; v1 a first via;

v2 second via holes; ln laminated structure;

210. A plastic packaging material; and 001 solder balls.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings.

The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary.

In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "middle", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific direction, be configured and operated in the specific direction, and thus should not be construed as limiting the present application. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations, not to scale. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the term "connected" should be construed broadly, and for example, it may be a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

In order to facilitate understanding of the package carrier provided in the embodiments of the present application, first, an application scenario thereof will be described. The package carrier provided by the embodiment of the application is used for carrying the chip and can be applied to various electronic equipment. For example, the present invention can be applied to a power supply circuit, a microprocessor (Micro controller Unit, MCU), a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), a Baseband (Baseband) Chip, a System on Chip (SoC) Chip, or the like. It should be noted that the package carrier proposed by embodiments of the present application is intended to include, but not be limited to, application in these and any other suitable types of electronic devices. As shown in fig. 3, an electronic device includes a housing 1 and a circuit board 2 disposed in the housing 1, where a package structure 3 is disposed on the circuit board 2, and the package structure 3 includes a package carrier 10 and a chip 20 encapsulated on a front surface of the package carrier 10. The package carrier 10 is an important component of the package of the chip 20, and along with the continuous evolution of moore's law, the process requirements of the wafer are higher and higher, and correspondingly, the processing precision of the inner circuit of the package carrier 10 is also higher and more precise. Based on the above, the application provides a circuit substrate with high circuit precision and low cost, a packaging loading board prepared based on the circuit substrate, a packaging structure and electronic equipment. The present application will be described in further detail with reference to the accompanying drawings.

Referring to fig. 4, fig. 4 is a flowchart schematically illustrating a method for manufacturing a circuit substrate according to an embodiment of the present application. The preparation method of the circuit substrate can comprise the following steps:

step S101, providing a carrier plate, where the carrier plate has two surfaces disposed opposite to each other.

In step S102, as shown in fig. 5a, a metal layer 102 is formed on at least one of the two surfaces of the carrier 101.

Fig. 5a illustrates an example of forming a metal layer 102 on one surface of a carrier plate 101.

The material of the metal layer is not limited in this application, and may be gold, silver, copper, platinum, tin, or the like.

In a specific implementation, the metal layer may be formed on the surface of the carrier plate by a lamination process, a deposition process, or the like.

In step S103, as shown in fig. 5b, a first dielectric layer 103 is formed on the side of the metal layer 102 away from the carrier 101.

In a specific implementation, the first dielectric layer 103 may be formed on the metal layer by a lamination process or a coating process using a semi-cured material.

By way of example, the material of the first dielectric layer 103 may be a material including at least one of bismaleimide triazine resin, polyaramid fiber, epoxy resin, polyphenylene oxide, or glass fiber, which is not limited herein.

The thickness of the first dielectric layer 103 is not limited in this application, and may be designed according to practical requirements. Generally, the thinner the thickness of the first dielectric layer 103, the higher the precision of the hollowed-out area formed by the laser ablation process.

In step S104, as shown in fig. 5c, a laser ablation process is used to form a plurality of hollowed-out areas 1030 in the first dielectric layer 103.

In this application, the shape of the hollowed-out area is not limited, as shown in fig. 6, fig. 6 is a schematic top view structure of the first dielectric layer 103 provided in this embodiment of the present application, and the shape of the hollowed-out area 1030 in the first dielectric layer 103 may be a hole shape, a line shape, a groove shape or the like, and specifically, the hollowed-out area is designed according to a required pattern of the metal trace.

In step S105, as shown in fig. 7, metal traces 104 are formed in each hollow region of the first dielectric layer 103.

In the circuit substrate formed by the preparation method provided by the application, since the metal wiring is formed in the hollowed-out area in the first dielectric layer 103, the precision of the hollowed-out area determines the precision of the metal wiring in the circuit substrate, and the hollowed-out area in the first dielectric layer is formed by adopting a laser ablation process. In the specific implementation, the line width (width of the metal wires)/line distance (minimum pitch between the metal wires) can be made to be 10 μm or less.

It should be noted that, in the method for manufacturing a circuit substrate provided in the embodiment of the present application, when a metal layer, a first dielectric layer, a hollowed-out area, and a metal trace are formed on two surfaces of the carrier 101, the order of forming the film layers on the two surfaces is not limited, so long as the order of forming the film layers on each surface is ensured to be: the semiconductor device comprises a metal layer, a first dielectric layer, a hollowed-out area and a metal wiring. For example, the metal layer, the first dielectric layer, the hollowed-out area and the metal wire may be formed on one surface in sequence, and then the metal layer, the first dielectric layer, the hollowed-out area and the metal wire may be formed on the other surface in sequence; of course, the film layers on the two surfaces may be alternately formed.

In this application, the first dielectric layer 103 and the metal trace 104 formed in the hollowed-out area of the first dielectric layer 103 are referred to as a circuit layer. In the present application, when the metal layer 102 and the wiring layer are sequentially formed on only one surface of the carrier plate 101, the formed wiring substrate is as shown in fig. 7, the wiring substrate 100 includes the carrier plate 101, the metal layer 102 being located on one surface of the carrier plate 101; the first dielectric layer 103 is located at one side of the metal layer 102 far away from the carrier 101, and the first dielectric layer 103 has a plurality of hollow areas; each of the hollowed-out areas is filled with a metal trace 104.

In the present application, when a metal layer and a circuit layer are sequentially formed on both surfaces of a carrier, the formed circuit substrate is as shown in fig. 8, and the circuit substrate 100 includes a carrier 101, and metal layers 102 respectively located on both surfaces of the carrier 101; the first dielectric layers 103 are positioned on one side of each metal layer 102 far away from the carrier plate, and each first dielectric layer 103 is provided with a plurality of hollow areas; each of the hollowed-out areas is filled with a metal trace 104.

In the circuit substrate, since the metal traces 104 are filled in the hollow areas 1030 in the first dielectric layer 103, the accuracy of the hollow areas 1030 determines the accuracy of the metal traces 104 in the circuit substrate, and the hollow areas 1030 in the first dielectric layer 103 can be formed by using a laser ablation process, compared with the formation of the hollow areas 1030 by using a photolithography process, the accuracy can be prevented from being influenced by photoresist exposure developing factors, so that the circuit accuracy of the circuit substrate can be higher.

For an example, taking the circuit substrate shown in fig. 7 as an example to prepare the package carrier, referring to fig. 9, fig. 9 schematically shows a flowchart of a preparation method of the package carrier according to an embodiment of the present application. The method of preparing the encapsulation carrier plate may include the steps of:

in step S201, two circuit substrates as shown in fig. 7 are provided, wherein one circuit substrate is a first circuit substrate and the other circuit substrate is a second circuit substrate.

In specific implementation, the materials of the film layers named in the first circuit substrate and the second circuit substrate may be the same or different, for example, the materials of the first dielectric layer in the first circuit substrate and the materials of the first dielectric layer in the second circuit substrate may be the same or different, which is not limited herein. However, in practical production, a plurality of circuit substrates are generally formed on a large carrier board at the same time, and then cut to form a plurality of independent circuit substrates, so that the materials of the same named film layers in different circuit substrates are the same.

In step S202, as shown in fig. 10a, the second dielectric layer 105 is laminated between the first circuit substrate 100a and the second circuit substrate 100b, and the carrier board 101 of the first circuit substrate 100a and the carrier board 101 of the second circuit substrate 100b are located at a side far away from the second dielectric layer 105, i.e. the metal trace 104 side of the first circuit substrate 100a is opposite to the metal trace 104 side of the second circuit substrate 100 b.

In particular embodiments, the material of the second dielectric layer 105 may be a material including at least one of bismaleimide triazine resin, polyaramid fiber, epoxy resin, polyphenylene oxide, or glass fiber, which is not limited herein.

Illustratively, to improve the uniformity of the material between adjacent dielectric layers, the material of the second dielectric layer 105 may be the same as the material of the first dielectric layer 103 in the first circuit substrate 100a and the material of the first dielectric layer 103 in the second circuit substrate 100 b.

In step S203, as shown in fig. 10b, the carrier 101 and the metal layer 102 in the second circuit substrate 100b are removed.

In step S204, as shown in fig. 10c, a third dielectric layer 106 is formed on the side of the first dielectric layer 103 of the second circuit substrate 100b away from the second dielectric layer 105.

In particular implementations, the third dielectric layer 106 may be formed on the metal layer using a semi-cured material through a lamination process or a coating process.

By way of example, the material of the third dielectric layer 106 may be a material including at least one of bismaleimide triazine resin, polyaramid fiber, epoxy resin, polyphenylene oxide, or glass fiber, without limitation.

The thickness of the third dielectric layer 106 is not limited in this application, and may be designed according to practical requirements. Generally, the thinner the thickness of the third dielectric layer 106, the higher the accuracy of the hollowed-out region formed by the laser ablation process.

In step S205, as shown in fig. 10d, a via V is formed through the third dielectric layer 106, the metal trace 104 in the second circuit substrate 100b, and the second dielectric layer 105 by a laser ablation process.

In the present application, since the via V needs to penetrate the third dielectric layer 106, the metal trace 104 in the second circuit substrate 100b, and the second dielectric layer 105, the thinner the thickness of the film layer through which the via V needs to penetrate, the more advantageous the improvement of the precision. Therefore, the thicknesses of the third dielectric layer 106, the second dielectric layer 105 and the first dielectric layer 103 can be set as thin as possible according to the performance requirements of the actual product.

In step S206, as shown in fig. 10e, a conductive material 107 is formed in the via V to electrically connect the metal trace 104 in the first circuit substrate 100a with the metal trace 104 in the second circuit substrate 100 b.

The conductive material 107 in the via V is not limited in this application, and for example, the conductive material 107 may be gold, silver, copper, platinum, tin, or the like.

The formation method of the conductive material 107 in the via hole V is not limited in this application, and any method can be used to form the conductive material 107 in the via hole V. Illustratively, the conductive material 107 may be formed directly in the via V by electroplating.

In step S207, the carrier 101 and the metal layer 102 in the first circuit board 100a are removed, thereby forming a package carrier 10 as shown in fig. 11.

In specific implementation, the circuit substrate shown in fig. 7 may be combined with the circuit substrate shown in fig. 8 to prepare a package carrier, and the preparation method of the package carrier may include the following steps:

in step S301, two circuit substrates shown in fig. 7 are provided as second circuit substrates, and one circuit substrate shown in fig. 8 is provided as a first circuit substrate.

In a specific implementation, the first circuit substrate has two sides, and for any side of the first circuit substrate, the following steps are continuously performed:

in step S302, as shown in fig. 10a, the second dielectric layer 105 is laminated between the first circuit substrate 100a and the second circuit substrate 100b, and the carrier board 101 of the first circuit substrate 100a and the carrier board 101 of the second circuit substrate 100b are located at a side far away from the second dielectric layer 105, i.e. the metal trace 104 side of the first circuit substrate 100a is opposite to the metal trace 104 side of the second circuit substrate 100 b.

In step S303, as shown in fig. 10b, the carrier 101 and the metal layer 102 in the second circuit substrate 100b are removed.

In step S304, as shown in fig. 10c, a third dielectric layer 106 is formed on the side of the first dielectric layer 103 of the second circuit substrate 100b away from the second dielectric layer 105.

In step S305, as shown in fig. 10d, a via V is formed through the third dielectric layer 106, the metal trace 104 in the second circuit substrate 100b, and the second dielectric layer 105 by a laser ablation process.

In step S306, as shown in fig. 10e, a conductive material 107 is formed in the via V to electrically connect the metal trace 104 in the first circuit substrate 100a with the metal trace 104 in the second circuit substrate 100 b.

Finally, after steps S302 to S306 are performed on both sides of the first circuit substrate, the following steps are performed:

in step S307, the carrier 101 and the metal layer 102 in the first circuit board 100a are stripped, so as to form two package carrier as shown in fig. 11.

Referring to fig. 11, fig. 11 schematically illustrates a structural diagram of a fabricated package carrier using the fabrication method provided in the embodiments of the present application. In the package carrier 10, it may include: a first circuit layer and a laminated structure L1 laminated on the first circuit layer. The first circuit layer may include a first dielectric layer 103 and a metal trace 104 filled in a hollow area of the first dielectric layer 103. The laminated structure L1 may include a second dielectric layer 105, a second circuit layer, and a third dielectric layer 106, a via hole penetrating the third dielectric layer 106, the second circuit layer, and the second dielectric layer 105, and a conductive material 107 filled in the via hole; in the laminated structure L1, the second circuit layer is located between the second dielectric layer 105 and the third dielectric layer 106, and the second dielectric layer 106 is located at a side close to the first circuit layer; the second circuit layer may include a fourth dielectric layer 108 (i.e., the first dielectric layer in the second circuit substrate used in the manufacturing process) and the metal trace 104 filled in the hollow area of the fourth dielectric layer 108; the first wiring layer and the second wiring layer in the stacked structure L1 adjacent thereto may be electrically connected by the conductive material 107 in the via hole.

According to the packaging sealing plate, in the first aspect, since each layer of metal wire is formed by the circuit substrate provided by the application, compared with the circuit layer formed by the photoetching process, the packaging carrier plate formed in the application can achieve high precision of each layer of metal wire. In a second aspect, since the metal traces are already embedded in the first dielectric layer, the third dielectric layer located between adjacent metal traces can be made thinner than the dielectric material filled between two metal traces as shown in fig. 12, i.e. the third dielectric layer only needs to space the two metal traces, whereas the dielectric material in fig. 12 needs to not only fill the gap between the same metal traces but also space the two metal traces, so the amount of dielectric material needed must be sufficient to result in a thicker thickness h of dielectric material between the two metal traces. Therefore, the package carrier can realize thinner thickness. In the third aspect, the third dielectric layer is used for replacing photoresist, and the via holes communicated with different metal wiring layers are formed through a laser ablation process, so that the accuracy of the via holes in the package carrier plate can be improved, and the overall circuit accuracy of the package carrier plate is improved. In the fourth aspect, the bottom of the via hole is directly contacted with the metal wire, so that the conventional electroless plating step can be omitted, and the conductive material can be electroplated in the via hole without using special materials, so that the conductive material can be realized by adopting the conventional process and the conventional materials, and the cost is low.

Further, as shown in fig. 13, the preparation method may further include:

in step S401, as shown in fig. 14a, a third circuit board 100c shown in fig. 7 is provided, and the second dielectric layer 105, the first dielectric layer 103, the metal trace 104, the third dielectric layer 106 and the conductive material 107 are located above the first circuit board 100a to form a first stacked structure L1; a second dielectric layer 105 is pressed between the first stacked structure L1 and the third wiring board 100c, and the carrier board 101 of the third wiring board 100c is located at a side away from the first stacked structure L1.

In step S402, as shown in fig. 14b, the carrier 101 and the metal layer 102 in the third wiring board 100c are removed.

In step S403, as shown in fig. 14c, the third dielectric layer 106 is formed on the first dielectric layer 103 of the third wiring board 100 c.

Step S404, as shown in fig. 14d, forming a via V penetrating the newly formed third dielectric layer 106, the metal trace 104 in the third wiring substrate 100c and the newly formed second dielectric layer 105 by a laser ablation process;

In step S405, as shown in fig. 14e, a conductive material 107 is formed in the via V to electrically connect the metal trace 104 in the second circuit substrate 100b with the metal trace 104 in the third circuit substrate 100 c.

The specific embodiments of step S401 to step S405 can be referred to as step S202 to step 206, and are not described herein.

Referring to fig. 15, fig. 15 schematically illustrates a structural diagram of another package carrier according to an embodiment of the present application. In the package carrier 10, a multilayer laminated structure Ln is laminated on the first wiring layer. In fig. 15, the package carrier 10 is illustrated as an example including three layered laminated structures L1 to Ln. In each laminated layer structure Ln, a second dielectric layer 105, a second circuit layer, and a third dielectric layer 106 that are sequentially laminated, a via hole V that penetrates the third dielectric layer 106, the second circuit layer, and the second dielectric layer 105, and a conductive material 107 filled in the via hole V may be included; the second wiring layer in any adjacent two-layered structure Ln and ln+1 is electrically connected through the conductive material in the adjacent two-layered structure Ln and ln+1.

Referring to fig. 16, in the package carrier 10, in the stacked structure L1 farthest from the first circuit layer, the via V in the stacked structure L1 includes a first via V1 penetrating the third dielectric layer 106, and a second via V2 penetrating the metal trace in the second circuit layer and the second dielectric layer 105; the orthographic projection of the first via hole V1 on the first circuit layer covers the orthographic projection of the second via hole V2 on the first circuit layer, that is, the first via hole V1 covers the second via hole V2, and the area of the first via hole V1 is greater than or equal to the area of the second via hole V2. Thus, as shown in fig. 17, after the conductive material 107 is formed in the via hole V, the area of the conductive material 107 in the via hole on the outermost side of the package carrier 10 can be increased, thereby increasing the conductive contact area of the package carrier 10 with other electric devices.

Thus, in the preparation, when stacking the last layer of wiring, when forming the via hole penetrating the third dielectric layer, the metal wiring in the second circuit substrate and the second dielectric layer, as shown in fig. 16, the first via hole V1 penetrating the third dielectric layer 106 may be formed by a laser ablation process; a second via V2 is then formed through the second dielectric layer 105 and the metal trace 104 in the second wiring substrate by a laser ablation process, and the orthographic projection of the first via V1 on the first wiring substrate (only the first dielectric layer 103 and the metal trace 104 in the first wiring substrate are shown in fig. 16) covers the orthographic projection of the second via V2 on the first wiring substrate.

Further, in the package carrier 10, as shown in fig. 18, in each laminated layer structure Ln, the via hole V in the laminated structure Ln includes a first via hole V1 penetrating the third dielectric layer 106, and a second via hole V2 penetrating the metal trace in the second circuit layer and the second dielectric layer 105; the orthographic projection of the first via hole V1 on the first circuit layer covers the orthographic projection of the second via hole V2 on the first circuit layer, so that the area of the upper surface of the conductive material 107 in the via hole V can be increased, and when the laminated structure Ln is superimposed thereon after the area of the upper surface of the conductive material 107 is increased, even if a certain error occurs in the position of the via hole V formed in the laminated structure Ln, good contact can be formed with the conductive material 107.

In the package carrier 10 provided in the embodiment of the present application, as shown in fig. 18, the pattern of the metal trace 104 in the first dielectric layer 103 may be designed according to the actual product, which is not limited herein. The patterns of the metal traces 104 in the different first dielectric layers 103 are generally different, and the metal traces 104 in the different first dielectric layers 103 may be electrically connected by the conductive material 107 in the via V.

Further, in the present application, after forming the conductive material 107 in the via hole V, it may further include: the third dielectric layer 106 and the conductive material 107 located in the via hole of the third dielectric layer 106 are removed, i.e. the conductive material 107 located above the metal trace 104 in the second wiring substrate 100b is removed. As shown in fig. 19 and 20, in the laminated structure Ln of the package carrier 10, the formed package carrier includes only the second dielectric layer 105 and the second wiring layer, so that the thickness of the package carrier can be further reduced. In the embodiment, the third dielectric layer may not be included in the partial stacked structure Ln, or may not be included in the entire stacked structure, which is not limited herein.

Correspondingly, as shown in fig. 21, the embodiment of the present application further provides a packaging structure 3, which includes any of the above-mentioned packaging carrier boards 10, and a chip 20 encapsulated on one side of the packaging carrier board 10. Since the principle of the package structure 3 for solving the problem is similar to that of the aforementioned package carrier 10, the implementation of the package structure 3 can refer to the implementation of the aforementioned package carrier 10, and the repetition is omitted.

In one possible implementation, the package structure may be formed by:

in step S501, as shown in fig. 22a, after forming a target number of circuit layers on the first circuit board 100a in preparing the package carrier 10, the chip 20 is bonded on a side away from the first circuit board 100a before removing the carrier 101 and the metal layer 102 in the first circuit board 100 a.

In step S502, as shown in fig. 22b, the chip 20 is encapsulated by the encapsulation material 210.

Step S503, removing the carrier board 101 and the metal layer 102 in the first circuit board 100a, thereby forming the package structure 3 as shown in fig. 21.

Further, a solder resist layer or the like may be formed on the package carrier 10 on the side facing away from the chip 20, which is not limited herein.

Further, as shown in fig. 23, solder balls 001 may be implanted on the side of the package carrier 10 away from the chip 20, so as to facilitate subsequent soldering of the package structure 3 to the circuit board.

Accordingly, as shown in fig. 24, another package structure 3 is provided in the embodiment of the present application, which includes a package carrier 10, and a chip 20 encapsulated on one side of the package carrier 10. The package carrier 10 may include at least one laminated layer structure Ln, and in fig. 24, the package carrier 10 includes two laminated layer structures L1 and L2. Each laminated layer structure Ln includes a second dielectric layer 105, a circuit layer and a third dielectric layer 106, where the circuit layer includes a first dielectric layer 103 and a metal wire 104 filled in a hollow area of the first dielectric layer 103. The stacked layer structure Ln has a via V penetrating the second dielectric layer 105, the metal trace 104 of the wiring layer, and the third dielectric layer 106, and the via V is filled with a conductive material 107.

In one possible implementation, the package structure may be formed by:

in step S601, as shown in fig. 25a, the chip 20 is encapsulated by using the encapsulating material 210.

In step S602, as shown in fig. 25b, the second dielectric layer 105 is pressed between the molding compound 210 and the circuit substrate 100.

In step S603, as shown in fig. 25c, the carrier 101 and the metal layer 102 in the circuit substrate 100 are removed, a third dielectric layer 106 is formed on the side of the first dielectric layer 103 away from the second dielectric layer 105, a via hole penetrating the third dielectric layer 106, the metal trace 104 in the circuit substrate 100 and the second dielectric layer 105 is formed by a laser ablation process, and a conductive material 107 is formed in the via hole, thereby forming a laminated layer structure L1.

Step S604, laminating the second dielectric layer 105 between the laminated structure L1 and the circuit substrate 100; the carrier 101 and the metal layer 102 in the circuit substrate 100 are removed, a third dielectric layer 106 is formed on one side of the first dielectric layer 103 away from the second dielectric layer 105, a via hole V penetrating the third dielectric layer 106, the metal trace 104 in the circuit substrate 100 and the second dielectric layer 105 is formed through a laser ablation process, and a conductive material 107 is formed in the via hole V, so as to form a second laminated layer structure L2, further form a package structure 3 as shown in fig. 24, and two laminated layer structures L1 and L2 formed in the package structure 3 form the package carrier 10.

In the embodiment, when the package carrier of the package structure includes a multi-layer stack structure, step S604 may be repeated until a stack structure with a target layer number is formed, which is not described herein.

Further, as shown in fig. 26, solder balls 001 may be implanted on the side of the package carrier 10 away from the chip 20, so as to facilitate subsequent soldering of the package structure 3 to the circuit board.

Correspondingly, the application also provides electronic equipment, as shown in fig. 3, including: a housing 1, a circuit board 2 and a packaging structure 3 which are positioned in the housing 1; the package structure 3 is located on the circuit board 2, and the package module 3 is electrically connected with the circuit board 2. The circuit board may be, for example, a PCB. Since the principle of the electronic device for solving the problem is similar to that of the aforementioned packaging structure 3, the implementation of the electronic device can refer to the implementation of the aforementioned packaging structure 3, and the repetition is omitted.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. A package carrier (10), characterized by comprising:

the first circuit layer comprises a first dielectric layer (103) and a metal wire (104) filled in a hollowed-out area of the first dielectric layer (103);

a laminated structure (Ln) laminated on the first wiring layer, the laminated structure (Ln) comprising: a second dielectric layer (105), a second circuit layer, and a third dielectric layer (106) which are sequentially stacked, a via hole (V) penetrating the third dielectric layer (106), the second circuit layer, and the second dielectric layer (105), and a conductive material (107) filled in the via hole (V); wherein:

the second dielectric layer (105) is positioned on the side close to the first circuit layer, and the second circuit layer is positioned between the second dielectric layer (105) and the third dielectric layer (106);

the second circuit layer comprises a fourth dielectric layer (108) and a metal wire (104) filled in a hollowed-out area of the fourth dielectric layer (108), and the via penetrates through the metal wire (104) of the second circuit layer;

The first wiring layer and the second wiring layer in the laminated structure (Ln) adjacent thereto are electrically connected by the conductive material (107).

2. Package carrier (10) according to claim 1, wherein a plurality of layers of the laminate structure (Ln) are laminated on the first wiring layer;

the second wiring layer in any adjacent two layers of the laminated structure (Ln) is electrically connected through the conductive material (107) in the adjacent two layers of the laminated structure (Ln).

3. Package carrier (10) according to claim 1 or 2, characterized in that in the stack (Ln) furthest from the first circuit layer, the vias (V) in the stack (Ln) comprise: a first via (V1) through the third dielectric layer (106), and a second via (V2) through the metal trace (104) in the second wiring layer and the second dielectric layer (105);

the orthographic projection of the first via hole (V1) on the first circuit layer covers the orthographic projection of the second via hole (V2) on the first circuit layer.

4. A package carrier (10) according to any of claims 1-3, characterized in that at least two of the first dielectric layer (103), the second dielectric layer (105), the third dielectric layer (106) and the fourth dielectric layer (108) are of the same material.

5. The package carrier (10) of any of claims 1-4, wherein the metal traces (104) in the first trace layer are of the same material as the metal traces (104) in the second trace layer.

6. The package carrier (10) according to any of claims 1-5, wherein the conductive material (107) is the same material as the metal traces (104).

7. A package structure (3) comprising a package carrier (10) according to any of claims 1-6, and a chip (20) encapsulated on one side of the package carrier.

8. An electronic device, characterized by comprising a housing (1), a circuit board (2) located within the housing (1), and the encapsulation structure (3) as claimed in claim 7 located on the circuit board (2).

9. A wiring substrate (100), comprising:

a carrier plate (101), the carrier plate (101) having two surfaces arranged opposite to each other;

a metal layer (102) on at least one of the two surfaces;

a first dielectric layer (103) located at one side of the metal layer (102) away from the carrier plate (101), wherein the first dielectric layer (103) is provided with a plurality of hollow areas (1030);

and metal wires (104) filled in the hollow areas (1030) of the first dielectric layer (103).

10. A method of manufacturing a circuit substrate (100), comprising:

providing a carrier plate (101), wherein the carrier plate (101) is provided with two surfaces which are oppositely arranged;

forming a metal layer (102) on at least one of the two surfaces;

forming a first dielectric layer (103) on one side of each metal layer (102) away from the carrier plate (101);

forming a plurality of hollowed-out areas (1030) in each first dielectric layer (103) by adopting a laser ablation process;

and forming a metal wire (104) in each hollowed-out area (1030) of each first dielectric layer (103).

11. The method of claim 10, wherein forming a metal trace (104) in each of the hollowed-out regions (1030) of each of the first dielectric layers (103) comprises:

and forming a metal wire (104) in each hollowed-out area (1030) of each first dielectric layer (103) by adopting an electroplating mode.

12. A method of manufacturing a package carrier (10), comprising:

providing two circuit substrates (100 a and 100 b) according to claim 9, wherein each circuit substrate (100 a and 100 b) comprises one metal layer (102) and one first dielectric layer (103), one circuit substrate is a first circuit substrate (100 a) and the other circuit substrate is a second circuit substrate (100 b);

A second dielectric layer (105) is pressed between the first circuit substrate (100 a) and the second circuit substrate (100 b), and the carrier plate (101) of the first circuit substrate (100 a) and the carrier plate (101) of the second circuit substrate (100 b) are both positioned at one side far away from the second dielectric layer (105);

removing the carrier plate (101) and the metal layer (102) in the second circuit substrate (100 b);

forming a third dielectric layer (106) on a side of the first dielectric layer (103) of the second circuit substrate (100 b) away from the second dielectric layer (105);

forming a via (V) through the third dielectric layer (106), the metal trace (104) in the second wiring substrate (100 b) and the second dielectric layer (105) by a laser ablation process;

forming a conductive material (107) in the via (V) to electrically connect the metal trace (104) in the first wiring substrate (100 a) with the metal trace (104) in the second wiring substrate (100 b);

and removing the carrier plate (101) and the metal layer (102) in the first circuit substrate (100 a).

13. The method of manufacturing according to claim 12, wherein forming a conductive material (107) in the via (V) comprises:

a conductive material (107) is formed in the via hole (V) by electroplating.

14. The method of manufacturing according to claim 12 or 13, wherein forming via holes (V) through the third dielectric layer (106), the metal tracks (104) in the second wiring substrate (100 b) and the second dielectric layer (105) by a laser ablation process comprises:

forming a first via (V1) through the third dielectric layer (106) by a laser ablation process;

a second via (V2) penetrating the second dielectric layer (105) and the metal trace (104) in the second circuit substrate (100 b) is formed by a laser ablation process, and the orthographic projection of the first via (V1) on the first circuit substrate (100 a) covers the orthographic projection of the second via (V2) on the first circuit substrate (100 a).

15. The method of manufacturing according to any of the claims 12-14, characterized in that after forming the conductive material (107) in the via (V), it further comprises:

-removing the third dielectric layer (106) and the conductive material (107) located in the via of the third dielectric layer (106).

16. A method of manufacturing a package carrier (10), comprising:

providing three circuit substrates (100 a and 100 b) according to claim 9, wherein one of the three circuit substrates is a first circuit substrate (100 a), and the other two circuit substrates are second circuit substrates (100 b), the first circuit substrate (100 a) comprises two metal layers (102) and two first dielectric layers (103), and each second circuit substrate comprises one metal layer (102) and one first dielectric layer (103);

The first wiring substrate (100 a) has two sides, for either side of the first wiring substrate (100 a):

superposing the second circuit substrate (100 b) on the first circuit substrate (100 a), and laminating a second dielectric layer (105) between the first circuit substrate (100 a) and the second circuit substrate (100 b), wherein the carrier plate (101) of the first circuit substrate (100 a) and the carrier plate (101) of the second circuit substrate (100 b) are both positioned at one side far away from the second dielectric layer (105);

after the conductive material (107) is formed on both sides of the first wiring substrate (100 a), the carrier (101) and the metal layer (102) in the first wiring substrate (100 a) are stripped.

17. The method of manufacturing according to claim 16, wherein forming a conductive material (107) in the via (V) comprises:

a conductive material (107) is formed in the via hole (V) by electroplating.

18. The method of manufacturing according to claim 16 or 17, wherein forming via holes (V) through the third dielectric layer (106), the metal tracks (104) in the second wiring substrate (100 b) and the second dielectric layer (105) by a laser ablation process comprises:

19. The method of manufacturing according to any of the claims 16-18, characterized in that after forming the conductive material (107) in the via (V), it further comprises: