WO2023071446A1

WO2023071446A1 - Package carrier, preparation method therefor, circuit substrate, package structure, and electronic device

Info

Publication number: WO2023071446A1
Application number: PCT/CN2022/113348
Authority: WO
Inventors: 李志海; 郭钜添; 解松林
Original assignee: 华为技术有限公司
Priority date: 2021-10-27
Filing date: 2022-08-18
Publication date: 2023-05-04
Also published as: CN116031232A

Abstract

Disclosed are a package carrier, a preparation method therefor, a circuit substrate, a package structure and an electronic device. The package carrier comprises a first circuit layer, wherein the first circuit layer comprises a first dielectric layer and metal traces filling a hollowed-out area of the first dielectric layer; and a laminated structure stacked on the first circuit layer, wherein the laminated structure comprises: a second dielectric layer, a second circuit layer and a third dielectric layer which are sequentially arranged one above the other, via holes running through the third dielectric layer, the second circuit layer and the second dielectric layer, and a conductive material filling the via holes. The second circuit layer comprises a fourth dielectric layer and metal traces filling a hollowed-out area of the fourth dielectric layer, and the via holes run through the metal traces of the second circuit layer. The first circuit layer is electrically connected, by means of the conductive material, to the second circuit layer in the laminated structure adjacent to the first circuit layer. The invention is used for realizing a package carrier which is high in circuit precision and low in cost.

Description

Encapsulation carrier, its preparation method, circuit substrate, encapsulation structure and electronic equipment

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 202111258938.X and the application title "a packaging structure" filed with the China Patent Office on October 27, 2021, the entire contents of which are incorporated in this application by reference; This application claims the priority of the Chinese patent application submitted to the China Patent Office on December 15, 2021, with the application number 202111536692.8 and the application title "Packaging carrier board, its preparation method, circuit substrate, packaging structure and electronic equipment". The entire contents are incorporated by reference in this application.

technical field

The present application relates to the technical field of semiconductor packaging, in particular to a packaging carrier, a preparation method thereof, a circuit substrate, a packaging structure and electronic equipment.

Background technique

As the packaging carrier is an important part of chip packaging, with the continuous evolution of Moore's law, the process requirements of the wafer are getting higher and higher. Correspondingly, the processing accuracy of the inner circuit of the packaging carrier is becoming more and more precise. At present, the commonly used process methods for making packaging substrates include subtractive process, modified semi-additive process (MSAP) process and semi-additive process (Semi-Additive Process, SAP) process. Among them, the process of forming the packaging carrier by the subtractive process is shown in Figure 1. The dielectric layer 02 and copper foil 03 are laminated on the carrier 01, and then drilling, electroless copper plating 04, and photoresist 05 are exposed and developed in sequence. , Electroplating copper 06, removing photoresist 05, flash etching part of copper foil 03 and chemically plated copper 04 to obtain a circuit pattern. However, the copper foil 03 used in the subtractive process is relatively thick, and the line accuracy is limited when the thicker copper layer is finally etched, and in the photolithography process, the side wall of the photoresist is prone to tilt after development, which affects the line accuracy. Therefore, the packaging substrate formed by the subtractive process usually has a line width/line spacing of about 40 μm. The process of forming the packaging carrier board by MSAP process is also shown in Figure 1. The difference from the subtractive process is that it uses an ultra-thin copper foil of about 3 μm, which can avoid the problem of circuit accuracy caused by photolithography of thicker copper layers and improve line precision. But the disadvantage is that ultra-thin copper foil is more expensive, and the line accuracy will still be affected by the exposure and development of photoresist. Usually, the line width/line spacing can reach about 20 μm. The process of forming the packaging carrier board by the SAP process is shown in Figure 2. Compared with the MSAP process, the ultra-thin copper foil is omitted, and the electroless copper 04 is directly plated on the dielectric layer 02, and the copper layer is thinner, which further improves the circuit accuracy. However, in order to directly perform electroless copper plating 04 on the dielectric layer 02 and meet the bonding force, the dielectric layer 02 must use special materials, the cost is high, and the circuit accuracy will still be affected by the photoresist exposure and development factors, usually the line The width/line spacing can reach about 10μm.

Therefore, it is a technical problem urgently needed to be solved by those skilled in the art to provide a packaging substrate with high circuit accuracy and low cost.

Contents of the invention

The present application provides a packaging carrier, a preparation method thereof, a circuit substrate, a packaging structure and electronic equipment, which are used to provide a packaging carrier with high circuit precision and low cost.

In a first aspect, the present application provides a method for preparing a circuit substrate. The preparation method may include the following steps: providing a carrier plate with two opposite surfaces; at least one of the two surfaces of the carrier plate forming a metal layer on the surface; forming a first dielectric layer on the side of each metal layer away from the carrier; using a laser ablation process to form a plurality of hollowed out areas in the first dielectric layer; Metal traces are formed in the area. In the circuit substrate formed by this preparation method, since the metal traces are formed in the hollowed out area in the first dielectric layer, the accuracy of the hollowed out area determines the accuracy of the metal traces in the circuit substrate, and the second The hollow area in the first dielectric layer is formed by laser ablation process. Compared with the formation of hollow area by photolithography process, the accuracy can be avoided from being affected by photoresist exposure and development factors, so a circuit substrate with higher line precision can be prepared. In specific implementation, the line width (the width of the metal lines)/line space (the minimum space between the metal lines) can be made below 10 μm.

It should be noted that, in the preparation method of the circuit substrate provided in the embodiment of the present application, when the metal layer, the first dielectric layer, the hollow area and the metal wiring are formed on both surfaces of the carrier, the present application There is no limitation on the order of forming the film layers on the two surfaces, as long as the order of forming the film layers on each surface is: metal layer, first dielectric layer, hollow area and metal wiring. Exemplarily, the present application may first sequentially form a metal layer, a first dielectric layer, a hollow area, and metal wiring on one surface, and then sequentially form a metal layer, a first dielectric layer, and a hollow area on the other surface. Areas and metal traces; of course, the film layers on the two surfaces can also be formed alternately.

In specific implementation, the present application does not limit the material and shape of the carrier, which is used to carry the subsequently formed film layer.

The present application does not limit the material of the metal layer, which may be gold, silver, copper, platinum, tin and the like. In a specific implementation, the metal layer can be formed on the surface of the carrier board through a pressing process, a deposition process, and other methods.

Exemplarily, the metal layer may be a copper foil layer, and the copper foil layer may be formed on the surface of the carrier by a lamination process.

In a specific implementation, the first dielectric layer may be formed on the metal layer by using a semi-cured material through a lamination process or a coating process.

Exemplarily, the material of the first dielectric layer may be a material containing at least one of bismaleimide triazine resin, polyaramide fiber, epoxy resin, polyphenylene ether or glass fiber, which is not described herein. limited.

The present application does not limit the thickness of the first dielectric layer, which can be designed according to actual requirements. Generally speaking, the thinner the thickness of the first dielectric layer, the higher the accuracy of the hollowed-out area formed by the subsequent laser ablation process.

The shape of the hollowed out area is not limited in this application, and the shape of the hollowed out area in the first dielectric layer may be a hole shape, a line shape, or a groove shape, etc., and it is specifically designed according to the pattern of the metal wiring required.

The present application does not limit the material of the metal wiring, for example, the material of the metal wiring may be gold, silver, copper, platinum, tin or the like.

The present application also does not limit the method of forming metal traces. Exemplarily, since a metal layer is disposed under the first dielectric layer, metal traces can be directly formed in each hollowed-out area of the first dielectric layer by means of electroplating. In this way, the steps of conventional electroless plating can be avoided, and no special materials need to be used, so it can be realized by using conventional processes and conventional materials, and the cost is low.

In a second aspect, the present application also provides a circuit substrate, which may include: a carrier plate with two opposite surfaces; a metal layer located on at least one of the two surfaces; a metal layer located on each metal layer The first dielectric layer on the side away from the carrier board, and has a plurality of hollowed out areas in the first dielectric layer; metal traces filled in each hollowed out area of the first dielectric layer. Since the problem-solving principle of the circuit substrate is similar to the aforementioned method for preparing a circuit substrate, the implementation of the circuit substrate can refer to the implementation of the aforementioned method for preparing a circuit substrate, and repeated descriptions will not be repeated here.

In the circuit substrate, since the metal traces are filled in the hollowed-out area in the first dielectric layer, the accuracy of the hollowed-out area determines the accuracy of the metal traces in the circuit substrate, and the hollowed-out area in the first dielectric layer can use The formation of the laser ablation process, compared with the formation of the hollow area by the photolithography process, can avoid the accuracy being affected by the exposure and development of the photoresist, so the circuit accuracy of the circuit substrate can be higher.

Further, since the circuit substrate provided by the present application has relatively high circuit accuracy, the above circuit substrate can be used to prepare a high-precision packaging carrier.

In a third aspect, the present application also provides a method for preparing a packaging carrier, which may include the following steps:

Step S201, providing two circuit substrates provided in the second aspect of the present application, and each circuit substrate includes one layer of the metal layer and one layer of the first dielectric layer; in the two circuit substrates, One of the circuit substrates is a first circuit substrate, and the other circuit substrate is a second circuit substrate. In specific implementation, the materials of the film layers with the same name in the first circuit substrate and the second circuit substrate can be the same or different, for example, the material of the first dielectric layer in the first circuit substrate is the same as that of the second dielectric layer in the second circuit substrate. The material properties of a dielectric layer may be the same or different, which is not limited herein. However, in actual production, multiple circuit substrates are generally formed on a large carrier at the same time, and then cut to form multiple independent circuit substrates, so that the materials of the same-named film layers in different circuit substrates are the same.

Step S202, pressing the second dielectric layer between the first circuit substrate and the second circuit substrate, and the carrier plate of the first circuit substrate and the carrier plate of the second circuit substrate are located on the side away from the second dielectric layer, That is, the metal trace side of the first circuit substrate is opposite to the metal trace side of the second circuit substrate.

In a specific implementation, the material of the second dielectric layer may be a material containing at least one of bismaleimide triazine resin, polyaramide fiber, epoxy resin, polyphenylene ether or glass fiber, where Not limited.

Exemplarily, in order to improve the consistency of materials between adjacent dielectric layers, the material of the second dielectric layer may be the same as the material of the first dielectric layer in the first circuit substrate and the material of the first dielectric layer in the second circuit substrate. The materials are all the same.

Step S203, removing the carrier board and the metal layer in the second circuit substrate.

Step S204, forming a third dielectric layer on the side of the first dielectric layer of the second circuit substrate away from the second dielectric layer.

In a specific implementation, the third dielectric layer may be formed on the metal layer by using a semi-cured material through a lamination process or a coating process.

Exemplarily, the material of the third dielectric layer may be a material containing at least one of bismaleimide triazine resin, polyaramide fiber, epoxy resin, polyphenylene ether or glass fiber, which is not described herein. limited.

The present application does not limit the thickness of the third dielectric layer, which can be designed according to actual requirements. Generally speaking, the thinner the thickness of the third dielectric layer, the higher the accuracy of the hollowed-out area formed by the subsequent laser ablation process.

Step S205 , forming a via hole penetrating through the third dielectric layer, the metal wiring in the second circuit substrate, and the second dielectric layer by a laser ablation process.

In this application, since the via holes need to penetrate the third dielectric layer, the metal traces in the second circuit substrate, and the second dielectric layer, the thinner the thickness of the film layer that the via holes need to penetrate, the more conducive to the accuracy. improve. Therefore, the thicknesses of the third dielectric layer, the second dielectric layer and the first dielectric layer can be set as thin as possible according to the performance requirements of the actual product.

Step S206 , forming a conductive material in the via hole, so as to electrically connect the metal traces in the first circuit substrate to the metal traces in the second circuit substrate.

The present application does not limit the conductive material in the via hole, for example, the conductive material may be gold, silver, copper, platinum, tin or the like.

The present application does not limit the method of forming the conductive material in the via hole, and any method can be used to form the conductive material in the via hole. Exemplarily, the conductive material may be directly formed in the via hole by electroplating.

Step S207 , removing the carrier and the metal layer in the first circuit substrate, thereby forming a packaging carrier.

In specific implementation, it is also possible to use the circuit substrate with metal traces on one side provided in the above-mentioned embodiments in combination with the circuit substrate with metal traces on both sides to prepare a package carrier board, and the preparation method of the package carrier board may include the following steps : Step S301, providing three circuit substrates, among the three circuit substrates, one of the circuit substrates is the first circuit substrate, and the other two circuit substrates are the second circuit substrates, and both sides of the first circuit substrate have metal traces , one side of the second circuit substrate has metal traces. In a specific implementation, the first circuit substrate has two sides, and for either side of the first circuit substrate, the following steps are continued: step S302, pressing the second interposer between the first circuit substrate and the second circuit substrate electrical layer, and the carrier plate of the first circuit substrate and the carrier plate of the second circuit substrate are both located on the side away from the second dielectric layer, that is, the metal trace side of the first circuit substrate and the metal trace side of the second circuit substrate One side is oppositely set. Step S303, removing the carrier board and the metal layer in the second circuit substrate. Step S304, forming a third dielectric layer on the side of the first dielectric layer of the second circuit substrate away from the second dielectric layer. Step S305 , forming a via hole penetrating through the third dielectric layer, the metal wiring in the second circuit substrate, and the second dielectric layer by a laser ablation process. Step S306 , forming a conductive material in the via hole, so as to electrically connect the metal traces in the first circuit substrate to the metal traces in the second circuit substrate. Finally, after steps S302 to S306 are performed on both sides of the first circuit substrate, step S307 is performed to peel off the carrier and the metal layer in the first circuit substrate, thereby forming two packaging carriers.

In the preparation method provided in the embodiment of the present application, since each layer of metal wiring is formed by using the circuit substrate provided in the present application, compared with the circuit layer formed by photolithography, the package carrier formed in the present application can achieve each High precision of metal traces on one layer. Moreover, since the metal wiring has been embedded in the first dielectric layer, the third dielectric layer located between adjacent metal wiring layers, compared with directly filling the dielectric material between two layers of metal wiring, The thickness of the dielectric material between the two layers of metal traces can be made thinner. In addition, in this application, the third dielectric layer is used to replace the photoresist, and the via holes connecting different metal wiring layers are formed through the laser ablation process, which can improve the precision of the via holes in the package carrier, thereby improving the reliability of the package carrier. overall line accuracy. Finally, in this application, the bottom of the via hole is directly in contact with the metal trace, which can save the conventional electroless plating step, and can electroplate conductive materials in the via hole without using special materials, so it can be realized by using conventional processes and conventional materials. , the cost is lower.

The above-mentioned embodiments of the present application are only described by forming two layers of circuit layers in the package carrier as an example. Of course, multiple circuit layers can also be formed in the package carrier. The method of continuing to stack the circuit layers in the package carrier can be Refer to step S202 to step 206. In the following, a schematic description will be made by taking the continuous stacking of one circuit layer in the package carrier as an example.

Further, the preparation method may further include: providing a third circuit substrate, one side of the third circuit substrate has metal traces, so that the second dielectric layer, the first dielectric layer, and the metal traces are located above the first circuit substrate. , the third dielectric layer and the conductive material are a first stack structure; a layer of second dielectric layer is laminated between the first stack structure and the third circuit substrate, and the carrier of the third circuit substrate is located away from the first stack structure side. The carrier board and the metal layer in the third circuit substrate are removed. A third dielectric layer is formed on the first dielectric layer of the third circuit substrate. A via hole penetrating through the newly formed third dielectric layer, the metal traces in the third circuit substrate and the newly formed second dielectric layer is formed by a laser ablation process. A conductive material is formed in the via hole to electrically connect the metal traces in the second circuit substrate to the metal traces in the third circuit substrate.

By analogy, it is also possible to continue to form a circuit layer in the packaging substrate, which will not be repeated here.

Optionally, when forming the via holes penetrating through the third dielectric layer, the metal traces in the second circuit substrate, and the second dielectric layer when stacking the last layer of wiring lines in the package package board, you can first pass A laser ablation process forms a first via hole penetrating through the third dielectric layer; then a second via hole penetrating through the second dielectric layer and metal traces in the second circuit substrate is formed through a laser ablation process, and the first via hole The orthographic projection of the hole on the first circuit substrate covers the orthographic projection of the second via hole on the first circuit substrate.

Further, in the present application, after forming the conductive material in the via hole, it may further include: removing the third dielectric layer and the conductive material above the metal wiring in the second circuit substrate. In the formed package carrier, only the second dielectric layer and the second circuit layer are included in the laminated structure, which can further reduce the thickness of the package carrier.

In a fourth aspect, the present application also provides a packaging structure, in which the packaging substrate may include: a first circuit layer and a stacked structure stacked on the first circuit layer. Wherein, the first circuit layer may include a first dielectric layer and metal wirings filled in the hollow area of the first dielectric layer. The laminated structure may include a second dielectric layer, a second wiring layer, and a third dielectric layer stacked in sequence, a via hole penetrating through the third dielectric layer, the second wiring layer, and the second dielectric layer, and a via hole filled in the The conductive material in the via hole; in the laminated structure, the second circuit layer is located between the second dielectric layer and the third dielectric layer, and the second dielectric layer is located on the side close to the first circuit layer; and the second The wiring layer may include a fourth dielectric layer (that is, the first dielectric layer in the second wiring substrate used in the preparation process) and metal traces filled in the hollow area of the fourth dielectric layer; the first wiring layer It can be electrically connected with the second circuit layer in the stacked structure adjacent to it through the conductive material in the via hole.

For the package sealing plate provided in the embodiment of the present application, since each layer of metal wiring is formed by using the circuit substrate provided in the present application, compared with the circuit layer formed by photolithography, the package carrier formed in the present application can achieve High precision of metal traces on each layer. Moreover, since the metal wiring has been embedded in the first dielectric layer, the third dielectric layer located between adjacent metal wiring layers, compared with directly filling the dielectric material between two layers of metal wiring, The thickness of the dielectric material between the two layers of metal traces can be made thinner. In addition, in this application, the third dielectric layer is used to replace the photoresist, and the via holes connecting different metal wiring layers are formed through the laser ablation process, which can improve the precision of the via holes in the package carrier, thereby improving the reliability of the package carrier. overall line accuracy. Finally, in this application, the bottom of the via hole is directly in contact with the metal trace, which can save the conventional electroless plating step, and can electroplate conductive materials in the via hole without using special materials, so it can be realized by using conventional processes and conventional materials. , the cost is lower.

Optionally, in the package carrier of the present application, a multi-layer laminate structure may be stacked on the first circuit layer. In each laminated layer structure, it may include a second dielectric layer, a second wiring layer and a third dielectric layer stacked in sequence, through the third dielectric layer, the second wiring layer and the second dielectric layer The via hole, and the conductive material filled in the via hole; the second circuit layer in any adjacent two-layer laminated structure is electrically connected through the conductive material in the adjacent two-layer laminated structure.

Optionally, in the package carrier, in the laminated structure farthest from the first circuit layer, the vias in the laminated structure include a first via that penetrates through the third dielectric layer, and a via that penetrates through the second circuit layer. The metal wiring in the middle and the second via hole in the second dielectric layer; the orthographic projection of the first via hole on the first wiring layer covers the orthographic projection of the second via hole on the first wiring layer. In this way, the area of the conductive material on the outermost side of the package carrier can be increased, thereby increasing the conductive contact area between the package carrier and other electrical devices.

In the present application, solder mask layers and the like may also be included on both sides of the package carrier board, which is not limited here.

Optionally, in the present application, in order to improve the consistency of materials, the materials of at least two dielectric layers among the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are the same. Of course, in specific implementation, different dielectric layers may also use different materials, which is not limited here.

Optionally, in this application, the metal traces in different circuit layers are made of the same material. In this way, different circuit layers can be formed using the same process, thereby reducing costs.

Certainly, during specific implementation, the materials of the metal traces in different circuit layers may also be different.

Optionally, in this application, the conductive material in the via hole may be the same as the material of the metal wiring in the wiring layer.

In the fifth aspect, the present application also provides a package structure, including a package carrier, and a chip molded on one side of the package carrier, wherein the package carrier is as in the fourth aspect or various implementations of the fourth aspect Way package carrier board. Since the problem-solving principle of the packaging structure is similar to that of the aforementioned packaging substrate, the implementation of the packaging structure can refer to the aforementioned implementation of the packaging substrate, and the repetition will not be repeated.

In a feasible implementation, the package structure can be formed through the following steps: when preparing the package carrier, after forming a target number of circuit layers on the first circuit substrate, removing the carrier and Before the metal layer, the chip is bonded on the side away from the first circuit substrate. The chip is encapsulated with plastic encapsulation material. The carrier board and the metal layer in the first circuit substrate are removed.

Further, a solder resist layer and the like may also be formed on the side of the package carrier away from the chip, which is not limited herein.

Further, solder balls can also be implanted on the side of the package carrier away from the chip, so as to facilitate subsequent soldering of the package structure to the circuit board.

Correspondingly, the embodiment of the present application also provides another package structure, including a package carrier, and a chip molded on one side of the package carrier. The package carrier may include at least one laminated structure, each layered laminated structure includes a second dielectric layer, a circuit layer and a third dielectric layer, wherein the circuit layer includes the first dielectric layer and is filled in the first Metal traces in the cutout area of the dielectric layer. The stacked layer structure has a via hole penetrating through the second dielectric layer, the metal wiring of the circuit layer and the third dielectric layer, and the via hole is filled with conductive material.

In a feasible implementation manner, the encapsulation structure may be formed through the following steps: encapsulating the chip with a plastic encapsulation material. The second dielectric layer is pressed between the molding material and the circuit substrate. Remove the carrier plate and metal layer in the circuit substrate, form a third dielectric layer on the side of the first dielectric layer away from the second dielectric layer, and form a metal through the third dielectric layer and circuit substrate by laser ablation process The traces and the via holes of the second dielectric layer form a conductive material in the via holes, thereby forming a layered structure. Next, press-bond the second dielectric layer between the laminated structure and the circuit substrate; remove the carrier plate and the metal layer in the circuit substrate, and form a third dielectric layer on the side of the first dielectric layer away from the second dielectric layer , forming via holes penetrating through the third dielectric layer, metal traces in the circuit substrate, and the second dielectric layer through a laser ablation process, and forming conductive materials in the via holes, thereby forming a second layered layer structure.

In specific implementation, when the encapsulation carrier of the package structure includes a multi-layer laminated structure, it can be repeatedly performed: pressing the second dielectric layer between the laminated structure and the circuit substrate; removing the carrier and metal in the circuit substrate layer, forming a third dielectric layer on the side of the first dielectric layer away from the second dielectric layer, and forming through the third dielectric layer, metal traces in the circuit substrate, and the second dielectric layer through a laser ablation process Vias, in which conductive material is formed. Up to the formation of the laminated structure with the target number of layers, details will not be described here.

In a sixth aspect, the present application also provides an electronic device, including: a housing, a circuit board located in the housing, and the packaging structure according to various implementations of the fifth aspect; the packaging structure is located on the circuit board, and the packaging The structure is electrically connected to the circuit board. Exemplarily, the circuit board is a PCB. Since the problem-solving principle of the electronic device is similar to that of the aforementioned packaging structure, the implementation of the electronic device can refer to the implementation of the aforementioned packaging structure, and the repetition will not be repeated.

The technical effects that can be achieved from the fifth aspect to the sixth aspect can be described with reference to the technical effects that can be achieved by any possible design in the fourth aspect, and will not be repeated here.

Description of drawings

Fig. 1 is a structural schematic diagram of a preparation process of a packaging carrier in the related art;

FIG. 2 is a schematic structural diagram of the preparation process of another packaging carrier in the related art;

FIG. 3 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

FIG. 4 is a flow chart of a method for preparing a circuit substrate provided in an embodiment of the present application;

5a to 5c are structural schematic diagrams of a preparation process of a circuit substrate provided in an embodiment of the present application;

FIG. 6 is a schematic top view structure diagram of a first dielectric layer provided by an embodiment of the present application;

FIG. 7 is a schematic cross-sectional structure diagram of a circuit substrate provided in an embodiment of the present application;

FIG. 8 is a schematic cross-sectional structure diagram of another circuit substrate provided by an embodiment of the present application;

FIG. 9 is a flow chart of a method for preparing a packaging carrier provided in an embodiment of the present application;

Fig. 10a to Fig. 10e are schematic structural diagrams of the preparation process of a packaging carrier provided by the embodiment of the present application;

FIG. 11 is a schematic cross-sectional structure diagram of a package carrier provided in an embodiment of the present application;

FIG. 12 is a schematic structural diagram of direct lamination of two layers of metal traces provided by the embodiment of the present application;

FIG. 13 is a flow chart of continuing to form a circuit layer in the method for preparing a package carrier provided in the embodiment of the present application;

14a to 14e are structural schematic diagrams of the preparation process for continuing to form a circuit layer in a package carrier provided by the embodiment of the present application;

Fig. 15 is a schematic cross-sectional structure diagram of another package carrier provided by the embodiment of the present application;

FIG. 16 is a schematic cross-sectional structure diagram of a via hole in a package substrate provided by an embodiment of the present application;

Fig. 17 is a schematic cross-sectional structure diagram of another package carrier provided by the embodiment of the present application;

FIG. 18 is a schematic diagram of a three-dimensional structure of a packaging carrier provided by an embodiment of the present application;

Fig. 19 is a schematic cross-sectional structure diagram of another package carrier provided by the embodiment of the present application;

Fig. 20 is a schematic cross-sectional structure diagram of another package carrier provided by the embodiment of the present application;

Fig. 21 is a schematic cross-sectional structure diagram of a packaging structure provided by an embodiment of the present application;

Fig. 22a and Fig. 22b are structural schematic diagrams of the preparation process of a packaging structure provided by the embodiment of the present application;

FIG. 23 is a schematic cross-sectional structure diagram of another package structure provided by the embodiment of the present application;

FIG. 24 is a schematic cross-sectional structure diagram of another package structure provided by the embodiment of the present application;

25a to 25c are structural schematic diagrams of the preparation process of a packaging structure provided by the embodiment of the present application;

FIG. 26 is a schematic cross-sectional structure diagram of another package structure provided by the embodiment of the present application.

Explanation of reference signs:

1 shell; 2 circuit board;

3 package structure; 10 package carrier board;

20 chips; 101 carrier boards;

102 metal layer; 103 first dielectric layer;

104 metal traces; 105 second dielectric layer;

106 third dielectric layer; 107 conductive material;

108 fourth dielectric layer; 1030 hollow area;

100 Circuit substrate; 100a The first circuit substrate;

100b the second circuit substrate; 100c the third circuit substrate;

V Via; V1 The first via;

V2 second via; Ln stacked structure;

210 molding compound; 001 solder ball.

Detailed ways

In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings.

The terms used in the following examples are for the purpose of describing particular examples only, and are not intended to limit the application. As used in the specification and appended claims of this application, the singular expressions "a", "an", "above", "the" and "this" are intended to also include such as "one or multiple" unless the context clearly indicates otherwise.

In the description of this application, it should be noted that the terms "middle", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientation construction and operation, therefore should not be construed as limiting the application. The words expressing position and direction described in this application are all described by taking the accompanying drawings as an example, but changes can also be made according to needs, and all changes are included in the protection scope of this application. The drawings in this application are only used to illustrate the relative positional relationship and do not represent the true scale. In addition, the terms "first" and "second" are used for descriptive purposes only, and should not be understood as indicating or implying relative importance.

In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; It can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.

In order to facilitate the understanding of the packaging carrier provided by the embodiment of the present application, firstly, its application scenario is explained. The packaging carrier proposed in the embodiment of the present application is used to carry chips, and can be applied to various electronic devices. For example, it can be applied to power supply circuit, microprocessor (Micro controller Unit, MCU), central processing unit (Central Processing Unit, CPU), image processor (Graphics Processing Unit, GPU), baseband (Baseband) chip, or system on chip ( System on Chip, SoC) chips, etc. It should be noted that the packaging substrate proposed by the embodiments of the present application is intended to include, but not be limited to, applications in these and any other suitable types of electronic devices. Exemplarily, as shown in FIG. 3 , the electronic device includes a casing 1 and a circuit board 2 disposed in the casing 1. The circuit board 2 is provided with a package structure 3, and the package structure 3 includes a package carrier 10 and a plastic package. Chip 20 on the front side of package substrate 10 . The package carrier 10 is an important part of the package of the chip 20. With the continuous evolution of Moore's Law, the process requirements of the wafer are getting higher and higher. Correspondingly, the processing accuracy of the inner layer circuit of the package carrier 10 is also increasing precision. Based on this, the present application provides a circuit substrate with high circuit accuracy and low cost, a package carrier prepared based on the circuit substrate, a package structure and electronic equipment. The application will be described in further detail below in conjunction with the accompanying drawings.

Referring to FIG. 4 , FIG. 4 schematically shows a flowchart of a method for manufacturing a circuit substrate provided by an embodiment of the present application. The preparation method of the circuit substrate may include the following steps:

Step S101 , providing a carrier board, the carrier board has two opposite surfaces.

Step S102 , as shown in FIG. 5 a , forming a metal layer 102 on at least one of the two surfaces of the carrier 101 .

Wherein, FIG. 5 a illustrates by taking the formation of the metal layer 102 on one surface of the carrier 101 as an example.

The present application does not limit the material of the metal layer, which may be gold, silver, copper, platinum, tin and the like.

In a specific implementation, the metal layer can be formed on the surface of the carrier board through a pressing process, a deposition process, and other methods.

Step S103 , as shown in FIG. 5 b , forming a first dielectric layer 103 on a side of the metal layer 102 away from the carrier 101 .

In a specific implementation, the first dielectric layer 103 may be formed on the metal layer by using a semi-cured material through a pressing process or a coating process.

Exemplarily, the material of the first dielectric layer 103 may be a material containing at least one of bismaleimide triazine resin, polyaramide fiber, epoxy resin, polyphenylene ether or glass fiber, where Not limited.

The present application does not limit the thickness of the first dielectric layer 103, which can be designed according to actual requirements. Generally speaking, the thinner the thickness of the first dielectric layer 103 is, the higher the precision of the hollowed-out area formed by the subsequent laser ablation process is.

Step S104 , as shown in FIG. 5 c , a plurality of hollow areas 1030 are formed in the first dielectric layer 103 by using a laser ablation process.

The shape of the hollowed-out area is not limited in this application. As shown in FIG. 6, FIG. The shape can be hole-like, line-like or groove-like, etc., specifically designed according to the pattern of the metal wiring required.

Step S105 , as shown in FIG. 7 , forming metal wires 104 in each hollow area of the first dielectric layer 103 .

In the circuit substrate formed by the preparation method provided in this application, since the metal wiring is formed in the hollowed-out area in the first dielectric layer 103, the precision of the hollowed-out area determines the precision of the metal wiring in the circuit substrate. , while the hollowed-out area in the first dielectric layer is formed by laser ablation process, which can avoid the precision being affected by photoresist exposure and development factors compared with the formation of hollowed-out area by photolithography process, so the line with higher line precision can be prepared substrate. In specific implementation, the line width (the width of the metal lines)/line space (the minimum space between the metal lines) can be made below 10 μm.

It should be noted that, in the method for preparing the circuit substrate provided in the embodiment of the present application, when the metal layer, the first dielectric layer, the hollow area and the metal wiring are formed on both surfaces of the carrier 101, the present The application does not limit the order of forming the film layers on the two surfaces, as long as the order of the film layers formed on each surface is guaranteed to be: metal layer, first dielectric layer, hollow area and metal wiring. Exemplarily, the present application may first sequentially form a metal layer, a first dielectric layer, a hollow area, and metal wiring on one surface, and then sequentially form a metal layer, a first dielectric layer, and a hollow area on the other surface. Areas and metal traces; of course, the film layers on the two surfaces can also be formed alternately.

In this application, the first dielectric layer 103 and the metal traces 104 formed in the hollow area of the first dielectric layer 103 are referred to as circuit layers. In the present application, when the metal layer 102 and the circuit layer are sequentially formed on only one surface of the carrier 101, the formed circuit substrate is shown in FIG. The metal layer 102 on the surface; the first dielectric layer 103 located on the side of the metal layer 102 away from the carrier 101, and the first dielectric layer 103 has a plurality of hollowed out areas; each hollowed out area is filled with metal traces 104 .

In the present application, when the metal layer and the circuit layer are sequentially formed on both surfaces of the carrier board, the formed circuit substrate is shown in FIG. The metal layer 102 on each surface; the first dielectric layer 103 located on the side of each metal layer 102 away from the carrier, and each first dielectric layer 103 has a plurality of hollowed out areas; each hollowed out area is filled with metal Trace 104.

In this circuit substrate, since the metal traces 104 are filled in the hollowed-out area 1030 in the first dielectric layer 103, the precision of the hollowed-out area 1030 determines the precision of the metal traces 104 in the circuit substrate, and the first dielectric layer 103 The hollow area 1030 in the circuit board can be formed by laser ablation process. Compared with the process of forming the hollow area 1030 by photolithography process, the accuracy can be avoided from being affected by photoresist exposure and development factors, so the circuit substrate can have higher circuit accuracy.

Exemplarily, taking the circuit substrate shown in FIG. 7 as an example to prepare a package carrier, refer to FIG. 9 , which schematically shows a flow chart of a method for preparing a package carrier provided by an embodiment of the present application. The preparation method of the encapsulation carrier board may include the following steps:

Step S201 , providing two circuit substrates as shown in FIG. 7 , wherein one circuit substrate is a first circuit substrate, and the other circuit substrate is a second circuit substrate.

In specific implementation, the materials of the film layers with the same name in the first circuit substrate and the second circuit substrate can be the same or different, for example, the material of the first dielectric layer in the first circuit substrate is the same as that of the second dielectric layer in the second circuit substrate. The material properties of a dielectric layer may be the same or different, which is not limited herein. However, in actual production, multiple circuit substrates are generally formed on a large carrier at the same time, and then cut to form multiple independent circuit substrates, so that the materials of the same-named film layers in different circuit substrates are the same.

Step S202, as shown in FIG. 10a, press the second dielectric layer 105 between the first circuit substrate 100a and the second circuit substrate 100b, and the carrier 101 of the first circuit substrate 100a and the carrier of the second circuit substrate 100b The boards 101 are located away from the second dielectric layer 105, that is, the side of the metal trace 104 of the first circuit substrate 100a is opposite to the side of the metal trace 104 of the second circuit substrate 100b.

In a specific implementation, the material of the second dielectric layer 105 may be a material containing at least one of bismaleimide triazine resin, polyaramide fiber, epoxy resin, polyphenylene ether or glass fiber. This is not limited.

Exemplarily, in order to improve the consistency of materials between adjacent dielectric layers, the material of the second dielectric layer 105 can be the same as the material of the first dielectric layer 103 in the first circuit substrate 100a and the first material of the second circuit substrate 100b. The materials of the dielectric layer 103 are all the same.

Step S203, as shown in FIG. 10b, remove the carrier 101 and the metal layer 102 in the second circuit substrate 100b.

In step S204 , as shown in FIG. 10 c , a third dielectric layer 106 is formed on the side of the first dielectric layer 103 of the second circuit substrate 100 b away from the second dielectric layer 105 .

In a specific implementation, the third dielectric layer 106 may be formed on the metal layer by using a semi-cured material through a lamination process or a coating process.

Exemplarily, the material of the third dielectric layer 106 may be a material containing at least one of bismaleimide triazine resin, polyaramide fiber, epoxy resin, polyphenylene ether or glass fiber, where Not limited.

The present application does not limit the thickness of the third dielectric layer 106, which can be designed according to actual requirements. Generally speaking, the thinner the thickness of the third dielectric layer 106 is, the higher the precision of the hollowed-out area formed by the subsequent laser ablation process is.

Step S205 , as shown in FIG. 10 d , forming a via hole V penetrating through the third dielectric layer 106 , the metal wiring 104 in the second circuit substrate 100 b and the second dielectric layer 105 by a laser ablation process.

In this application, since the via hole V needs to penetrate the third dielectric layer 106, the metal wiring 104 in the second circuit substrate 100b, and the second dielectric layer 105, the thinner the thickness of the film layer that the via hole V needs to penetrate , the more conducive to the improvement of accuracy. Therefore, the thicknesses of the third dielectric layer 106 , the second dielectric layer 105 and the first dielectric layer 103 can be set as thin as possible according to the performance requirements of the actual product.

Step S206 , as shown in FIG. 10 e , form a conductive material 107 in the via hole V, so as to electrically connect the metal traces 104 in the first circuit substrate 100 a to the metal traces 104 in the second circuit substrate 100 b.

The present application does not limit the conductive material 107 in the via hole V, for example, the conductive material 107 may be gold, silver, copper, platinum, tin or the like.

The present application does not limit the method of forming the conductive material 107 in the via hole V, and it may be any method that can realize the formation of the conductive material 107 in the via hole V. Referring to FIG. Exemplarily, the conductive material 107 may be directly formed in the via hole V by electroplating.

Step S207 , removing the carrier 101 and the metal layer 102 in the first circuit substrate 100 a, thereby forming a packaging carrier 10 as shown in FIG. 11 .

In specific implementation, the circuit substrate as shown in FIG. 7 can also be used in combination with the circuit substrate as shown in FIG. 8 to prepare the packaging carrier. The method for preparing the packaging carrier may include the following steps:

Step S301 , providing two circuit substrates as shown in FIG. 7 as a second circuit substrate, and providing one circuit substrate as shown in FIG. 8 as a first circuit substrate.

During specific implementation, the first circuit substrate has two sides, and for any side of the first circuit substrate, continue to perform the following steps:

Step S302, as shown in FIG. 10a, press-bond the second dielectric layer 105 between the first circuit substrate 100a and the second circuit substrate 100b, and the carrier 101 of the first circuit substrate 100a and the carrier of the second circuit substrate 100b The boards 101 are located away from the second dielectric layer 105, that is, the side of the metal trace 104 of the first circuit substrate 100a is opposite to the side of the metal trace 104 of the second circuit substrate 100b.

Step S303, as shown in FIG. 10b, remove the carrier 101 and the metal layer 102 in the second circuit substrate 100b.

In step S304 , as shown in FIG. 10 c , a third dielectric layer 106 is formed on the side of the first dielectric layer 103 of the second circuit substrate 100 b away from the second dielectric layer 105 .

Step S305 , as shown in FIG. 10 d , forming a via hole V penetrating through the third dielectric layer 106 , the metal wiring 104 in the second circuit substrate 100 b and the second dielectric layer 105 by laser ablation process.

Step S306 , as shown in FIG. 10 e , form a conductive material 107 in the via hole V, so as to electrically connect the metal traces 104 in the first circuit substrate 100 a to the metal traces 104 in the second circuit substrate 100 b.

Finally, after steps S302 to S306 are performed on both sides of the first circuit substrate, the following steps are performed:

Step S307 , peeling off the carrier 101 and the metal layer 102 in the first circuit substrate 100 a, thereby forming two packaging carriers as shown in FIG. 11 .

Referring to FIG. 11 , FIG. 11 exemplarily shows a schematic structural diagram of a packaging carrier prepared by using the preparation method provided by the embodiment of the present application. The packaging substrate 10 may include: a first circuit layer and a stacked structure L1 stacked on the first circuit layer. Wherein, the first circuit layer may include a first dielectric layer 103 and a metal wire 104 filled in the hollow area of the first dielectric layer 103 . The laminated structure L1 may include the second dielectric layer 105, the second wiring layer and the third dielectric layer 106 which are stacked in sequence, and the third dielectric layer 106, the second wiring layer and the second dielectric layer 105 pass through hole, and the conductive material 107 filled in the via hole; in this laminated structure L1, the second wiring layer is located between the second dielectric layer 105 and the third dielectric layer 106, and the second dielectric layer 105 is located close to One side of the first circuit layer; and the second circuit layer may include a fourth dielectric layer 108 (that is, the first dielectric layer in the second circuit substrate used in the preparation process) and the fourth dielectric layer 108 filled The metal wiring 104 in the hollow area; the first wiring layer and the second wiring layer in the adjacent laminated structure L1 can be electrically connected through the conductive material 107 in the via hole.

In the package sealing plate provided by the embodiment of the present application, in the first aspect, since each layer of metal wiring is formed by using the circuit substrate provided by the application, compared with the circuit layer formed by the photolithography process, the package formed in the application The carrier board can realize the high precision of each layer of metal traces. In the second aspect, since the metal wiring has been embedded in the first dielectric layer, the third dielectric layer between the adjacent metal wiring layers and the two layers of metal wiring as shown in Figure 12 Compared with filling the dielectric material, the thickness of the dielectric material between the two layers of metal traces can be made thinner, that is, the third dielectric layer in this application only needs to separate the two layers of metal traces, and Figure 12 The dielectric material not only needs to fill the gap between the metal traces of the same layer, but also needs to separate the two layers of metal traces. Therefore, the amount of dielectric material required must be sufficient, so that the gap between the two layers of metal traces The thickness h of the dielectric material between them is thicker. Therefore, the packaging carrier of the present application can achieve a thinner thickness. In the third aspect, in this application, the third dielectric layer is used instead of photoresist, and vias connected to different metal wiring layers are formed by laser ablation process, which can improve the precision of the vias in the packaging substrate, thereby improving the packaging performance. The overall circuit accuracy of the board. In the fourth aspect, in this application, the bottom of the via hole is directly in contact with the metal trace, which can avoid the conventional electroless plating step, and can electroplate conductive materials in the via hole without using special materials. Therefore, using conventional processes and conventional materials is easy Achievable and low cost.

Further, as shown in Figure 13, the preparation method may also include:

Step S401, as shown in FIG. 14a, provide a third circuit substrate 100c as shown in FIG. The third dielectric layer 106 and the conductive material 107 are the first stacked structure L1; a layer of the second dielectric layer 105 is laminated between the first stacked structure L1 and the third circuit substrate 100c, and the third circuit substrate 100c carries The board 101 is located on a side away from the first stack structure L1.

Step S402, as shown in FIG. 14b, remove the carrier 101 and the metal layer 102 in the third circuit substrate 100c.

Step S403, as shown in FIG. 14c, forming a third dielectric layer 106 on the first dielectric layer 103 of the third circuit substrate 100c.

Step S404, as shown in FIG. 14d , forming vias through the newly formed third dielectric layer 106 , the metal traces 104 in the third circuit substrate 100c and the newly formed second dielectric layer 105 by laser ablation process V;

Step S405 , as shown in FIG. 14 e , form a conductive material 107 in the via hole V, so as to electrically connect the metal traces 104 in the second circuit substrate 100 b to the metal traces 104 in the third circuit substrate 100 c.

The specific implementation manners of step S401 to step S405 can refer to step S202 to step 206, which will not be repeated here.

Referring to FIG. 15 , FIG. 15 exemplarily shows a schematic structural diagram of another packaging carrier provided by an embodiment of the present application. In the package carrier 10 , a multi-layer laminated structure Ln is laminated on the first circuit layer. Wherein, in FIG. 15 , the three-layer laminated structures L1 -Ln included in the packaging substrate 10 are taken as an example for illustration. In each laminated structure Ln, it may include the second dielectric layer 105, the second circuit layer and the third dielectric layer 106 which are sequentially stacked, passing through the third dielectric layer 106, the second circuit layer and the second The via hole V of the dielectric layer 105, and the conductive material 107 filled in the via hole V; the second circuit layer in any adjacent two-layer laminated structure Ln and Ln+1 passes through the adjacent two-layer laminated structure The conductive materials in Ln and Ln+1 are electrically connected.

Referring to FIG. 16 , in the package carrier 10 , in the laminated structure L1 farthest from the first circuit layer, the vias V in the laminated structure L1 include the first vias V1 penetrating through the third dielectric layer 106 , And the second via hole V2 that runs through the metal wiring in the second wiring layer and the second dielectric layer 105; the orthographic projection of the first via hole V1 on the first wiring layer covers the second via hole V2 on the first wiring layer Orthographic projection, that is, the first via hole V1 covers the second via hole V2, and the area of the first via hole V1 is greater than or equal to the area of the second via hole V2. In this way, as shown in FIG. 17 , after the conductive material 107 is formed in the via hole V, the area of the conductive material 107 in the outermost via hole of the package carrier 10 can be increased, thereby increasing the conductive contact between the package carrier 10 and other electrical devices. area.

In this way, during preparation, when stacking the last layer of wiring lines, when forming via holes penetrating through the third dielectric layer, the metal wiring in the second circuit substrate, and the second dielectric layer, as shown in FIG. 16 , The first via hole V1 penetrating through the third dielectric layer 106 may be formed first by a laser ablation process; then the second via hole V1 penetrating the second dielectric layer 105 and the metal wiring 104 in the second circuit substrate is formed by a laser ablation process. The via hole V2, and the orthographic projection of the first via hole V1 on the first circuit substrate (only the first dielectric layer 103 and the metal wiring 104 in the first circuit substrate are shown in FIG. 16 ) covers the second via hole V2 Orthographic projection on the first circuit substrate.

Further, in this application, as shown in FIG. 18 , in the package substrate 10 , in each layer of the stacked structure Ln, the via hole V in the stacked structure Ln includes the first through the third dielectric layer 106 . A via hole V1, and a second via hole V2 penetrating through the metal wiring in the second circuit layer and the second dielectric layer 105; the orthographic projection of the first via hole V1 on the first circuit layer covers the second via hole V2 in The orthographic projection of the first circuit layer, in this way, can increase the area of the upper surface of the conductive material 107 in the via hole V, so that when the area of the upper surface of the conductive material 107 is increased, when the laminated structure Ln is superimposed thereon, Even if a certain error occurs in the position of the via hole V formed in the stacked structure Ln, good contact with the conductive material 107 can still be formed.

In the package carrier 10 provided in the embodiment of the present application, as shown in FIG. 18 , the pattern of the metal wiring 104 in the first dielectric layer 103 can be designed according to the actual product, and is not limited here. Generally, the patterns of the metal wires 104 in different first dielectric layers 103 are different, and the metal wires 104 in different first dielectric layers 103 can be electrically connected through the conductive material 107 in the via hole V.

Further, in this application, after forming the conductive material 107 in the via hole V, it may also include: removing the third dielectric layer 106 and the conductive material 107 located in the via hole of the third dielectric layer 106, that is, removing The conductive material 107 is located above the metal traces 104 in the second circuit substrate 100b. The formed package carrier is shown in FIGS. 19 and 20 . In the laminated structure Ln of the package carrier 10 , only the second dielectric layer 105 and the second circuit layer are included, which can further reduce the thickness of the package carrier. In specific implementation, the third dielectric layer may not be included in part of the stacked structure Ln, or the third dielectric layer may not be included in all the stacked structures, which is not limited herein.

Correspondingly, as shown in FIG. 21 , the embodiment of the present application also provides a package structure 3 , including any package carrier 10 described above, and a chip 20 plastic-sealed on one side of the package carrier 10 . Since the principle of solving the problem of the packaging structure 3 is similar to that of the aforementioned packaging substrate 10 , the implementation of the packaging structure 3 can refer to the implementation of the aforementioned packaging substrate 10 , and the repetition will not be repeated.

In a feasible implementation, the encapsulation structure can be formed through the following steps:

Step S501, as shown in FIG. 22a, when preparing the package carrier 10, after forming a target number of circuit layers on the first circuit substrate 100a, before removing the carrier 101 and the metal layer 102 in the first circuit substrate 100a, The chip 20 is bonded on the side away from the first circuit substrate 100a.

In step S502 , as shown in FIG. 22 b , the chip 20 is molded with a plastic packaging material 210 .

Step S503 , removing the carrier 101 and the metal layer 102 in the first circuit substrate 100 a, thereby forming the package structure 3 as shown in FIG. 21 .

Further, a solder resist layer and the like may also be formed on the side of the package carrier 10 away from the chip 20 , which is not limited here.

Further, as shown in FIG. 23 , solder balls 001 may also be implanted on the side of the package carrier 10 away from the chip 20 , so as to facilitate subsequent soldering of the package structure 3 to the circuit board.

Correspondingly, as shown in FIG. 24 , the embodiment of the present application also provides another package structure 3 , including a package carrier 10 and a chip 20 plastic-sealed on one side of the package carrier 10 . The package carrier 10 may include at least one layer of laminated structures Ln. In FIG. 24 , the package carrier 10 includes two layers of laminated structures L1 and L2 for illustration. Each layered structure Ln includes a second dielectric layer 105, a circuit layer and a third dielectric layer 106, wherein the circuit layer includes the first dielectric layer 103 and the hollow area filled in the first dielectric layer 103 Metal traces 104 . The stacked layer structure Ln has a via hole V penetrating through the second dielectric layer 105 , the metal wiring 104 of the circuit layer and the third dielectric layer 106 , and the via hole V is filled with a conductive material 107 .

In step S601 , as shown in FIG. 25 a , the chip 20 is molded with a molding material 210 .

Step S602 , as shown in FIG. 25 b , press-bond the second dielectric layer 105 between the molding material 210 and the circuit substrate 100 .

Step S603, as shown in FIG. 25c, remove the carrier plate 101 and the metal layer 102 in the circuit substrate 100, form the third dielectric layer 106 on the side of the first dielectric layer 103 away from the second dielectric layer 105, and laser burn The etching process forms via holes penetrating through the third dielectric layer 106 , the metal traces 104 in the circuit substrate 100 and the second dielectric layer 105 , and forms a conductive material 107 in the via holes, thereby forming a stacked structure L1 .

Step S604, pressing the second dielectric layer 105 between the laminated structure L1 and the circuit substrate 100; removing the carrier 101 and the metal layer 102 in the circuit substrate 100, and keeping the first dielectric layer 103 away from the second dielectric layer A third dielectric layer 106 is formed on one side of the circuit board 105, and a via hole V penetrating through the third dielectric layer 106, the metal wiring 104 in the circuit substrate 100, and the second dielectric layer 105 is formed by a laser ablation process. Conductive material 107 is formed in the package structure 3 to form the second layered structure L2, and then the package structure 3 shown in FIG.

In a specific implementation, when the package carrier of the package structure includes a multi-layer laminated structure, step S604 may be repeated until a laminated structure with a target number of layers is formed, which will not be repeated here.

Further, as shown in FIG. 26 , solder balls 001 may also be implanted on the side of the package carrier 10 away from the chip 20 , so as to facilitate subsequent soldering of the package structure 3 to the circuit board.

Correspondingly, the present application also provides an electronic device, as shown in FIG. 3 , comprising: a housing 1, a circuit board 2 located in the housing 1, and a packaging structure 3; the packaging structure 3 is located on the circuit board 2, and The packaging module 3 is electrically connected to the circuit board 2 . Exemplarily, the circuit board may be a PCB. Since the problem-solving principle of the electronic device is similar to that of the aforementioned packaging structure 3 , the implementation of the electronic device can refer to the implementation of the aforementioned packaging structure 3 , and repeated descriptions will not be repeated here.

Apparently, those skilled in the art can make various changes and modifications to this application without departing from the protection scope of this application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A packaging carrier (10), characterized in that it comprises:

A first circuit layer, the first circuit layer comprising a first dielectric layer (103) and metal traces (104) filled in the hollow area of the first dielectric layer (103);

A laminated structure (Ln) stacked on the first circuit layer, the laminated structure (Ln) comprising: a second dielectric layer (105), a second circuit layer and a third dielectric layer stacked in sequence (106), penetrating through the via hole (V) of the third dielectric layer (106), the second circuit layer and the second dielectric layer (105), and filling the via hole (V) Conductive material (107) in; wherein:

The second dielectric layer (105) is located on a side close to the first circuit layer, and the second circuit layer is located between the second dielectric layer (105) and the third dielectric layer (106) between;

The second wiring layer includes a fourth dielectric layer (108) and metal wiring (104) filled in the hollow area of the fourth dielectric layer (108), and the via hole runs through the second The metal wiring (104) of the circuit layer;

The first wiring layer is electrically connected to the second wiring layer in the stacked structure (Ln) adjacent thereto through the conductive material (107).
The packaging carrier (10) according to claim 1, characterized in that, multiple layers of the laminated structure (Ln) are stacked on the first circuit layer;

The second circuit layer in any two adjacent layers of the stacked structure (Ln) is electrically connected through the conductive material (107) in the two adjacent layers of the stacked structure (Ln) .
The package carrier (10) according to claim 1 or 2, characterized in that, in the stacked structure (Ln) farthest from the first circuit layer, all the stacked structures (Ln) in the stacked structure (Ln) The via hole (V) includes: a first via hole (V1) penetrating through the third dielectric layer (106), and a metal trace (104) penetrating through the second circuit layer and the second dielectric layer A second via (V2) of layer (105);

The orthographic projection of the first via hole (V1) on the first circuit layer covers the orthographic projection of the second via hole (V2) on the first circuit layer.
The package carrier (10) according to any one of claims 1-3, characterized in that, the first dielectric layer (103), the second dielectric layer (105), the third dielectric layer The materials of the electrical layer (106) and at least two dielectric layers in the fourth dielectric layer (108) are the same.
The package carrier board (10) according to any one of claims 1-4, characterized in that, the metal wiring (104) in the first wiring layer and the metal wiring (104) in the second wiring layer ( 104) The material is the same.
The package carrier (10) according to any one of claims 1-5, characterized in that, the conductive material (107) is the same material as the metal wiring (104).
A package structure (3), characterized by comprising the package carrier (10) according to any one of claims 1-6, and a chip (20) plastic-sealed on one side of the package carrier.
An electronic device, characterized in that it comprises a housing (1), a circuit board (2) located in the housing (1), and the circuit board (2) located on the circuit board (2) according to claim 7 Encapsulation structure (3).
A circuit substrate (100), characterized in that it comprises:

a carrier (101), the carrier (101) has two opposite surfaces;

a metal layer (102) on at least one of said two surfaces;

A first dielectric layer (103) located on the side of the metal layer (102) away from the carrier (101), and the first dielectric layer (103) has a plurality of hollow areas (1030);

Metal traces (104) filled in each hollow area (1030) of the first dielectric layer (103).
A method for preparing a circuit substrate (100), characterized in that it comprises:

A carrier (101) is provided, the carrier (101) has two opposite surfaces;

forming a metal layer (102) on at least one of said two surfaces;

forming a first dielectric layer (103) on a side of each of the metal layers (102) away from the carrier (101);

forming a plurality of hollow areas (1030) in each of the first dielectric layers (103) by using a laser ablation process;

Metal traces (104) are formed in each of the hollow areas (1030) of each of the first dielectric layers (103).
The preparation method according to claim 10, characterized in that forming metal wirings (104) in each of the hollow areas (1030) of each of the first dielectric layers (103) comprises:

Metal wiring (104) is formed in each of the hollow areas (1030) of each of the first dielectric layers (103) by means of electroplating.
A method for preparing a packaging carrier (10), characterized in that it comprises:

Two circuit substrates (100a and 100b) as claimed in claim 9 are provided, and each of the circuit substrates (100a and 100b) includes one layer of the metal layer (102) and one layer of the first dielectric layer (103), among the two circuit substrates, one circuit substrate is a first circuit substrate (100a), and the other circuit substrate is a second circuit substrate (100b);

A second dielectric layer (105) is pressed between the first circuit substrate (100a) and the second circuit substrate (100b), and the carrier (101) of the first circuit substrate (100a) and The carrier boards (101) of the second circuit substrate (100b) are located on the side away from the second dielectric layer (105);

removing the carrier (101) and metal layer (102) in the second circuit substrate (100b);

forming a third dielectric layer (106) on a side of the first dielectric layer (103) of the second circuit substrate (100b) away from the second dielectric layer (105);

Forming through the third dielectric layer (106), the metal traces (104) in the second circuit substrate (100b) and the via holes ( V);

Conductive material (107) is formed in the via hole (V), so that the metal traces (104) in the first circuit substrate (100a) and the metal traces in the second circuit substrate (100b) (104) electrical connection;

The carrier (101) and metal layer (102) in the first circuit substrate (100a) are removed.
The preparation method according to claim 12, characterized in that forming a conductive material (107) in the via hole (V) comprises:

A conductive material (107) is formed in the via hole (V) by electroplating.
The preparation method according to claim 12 or 13, characterized in that the metal wiring (104) penetrating through the third dielectric layer (106) and the second circuit substrate (100b) is formed by a laser ablation process ) and the via hole (V) of the second dielectric layer (105), including:

forming a first via hole (V1) penetrating through the third dielectric layer (106) by a laser ablation process;

A second via hole (V2) penetrating through the second dielectric layer (105) and the metal wiring (104) in the second circuit substrate (100b) is formed by a laser ablation process, and the first via The orthographic projection of the hole (V1) on the first circuit substrate (100a) covers the orthographic projection of the second via hole (V2) on the first circuit substrate (100a).
The preparation method according to any one of claims 12-14, characterized in that, after forming the conductive material (107) in the via hole (V), further comprising:

The third dielectric layer (106) and the conductive material (107) within the via holes of the third dielectric layer (106) are removed.
A method for preparing a packaging carrier (10), characterized in that it comprises:

Three circuit substrates (100a and 100b) as claimed in claim 9 are provided, among the three circuit substrates, one of the circuit substrates is the first circuit substrate (100a), and the other two circuit substrates are The second circuit substrate (100b), the first circuit substrate (100a) includes two layers of the metal layer (102) and two layers of the first dielectric layer (103), each of the second circuit substrates each comprising a layer of the metal layer (102) and a layer of the first dielectric layer (103);

The first circuit substrate (100a) has two sides, for any side of the first circuit substrate (100a):

One second circuit substrate (100b) is superimposed on the first circuit substrate (100a), and a second circuit substrate (100b) is pressed between the first circuit substrate (100a) and the second circuit substrate (100b). Dielectric layer (105), and the carrier (101) of the first circuit substrate (100a) and the carrier (101) of the second circuit substrate (100b) are located away from the second dielectric layer ( 105) one side;

removing the carrier (101) and metal layer (102) in the second circuit substrate (100b);

forming a third dielectric layer (106) on a side of the first dielectric layer (103) of the second circuit substrate (100b) away from the second dielectric layer (105);

Forming through the third dielectric layer (106), the metal traces (104) in the second circuit substrate (100b) and the via holes ( V);

Conductive material (107) is formed in the via hole (V), so that the metal wiring (104) in the first circuit substrate (100a) and the metal wiring in the second circuit substrate (100b) (104) electrical connection;

After the conductive material (107) is formed on both sides of the first circuit substrate (100a), the carrier (101) and metal layer (102) in the first circuit substrate (100a) are stripped off.
The preparation method according to claim 16, characterized in that forming a conductive material (107) in the via hole (V) comprises:

A conductive material (107) is formed in the via hole (V) by electroplating.
The preparation method according to claim 16 or 17, characterized in that the metal wiring (104) penetrating through the third dielectric layer (106) and the second circuit substrate (100b) is formed by a laser ablation process ) and the via hole (V) of the second dielectric layer (105), including:

forming a first via hole (V1) penetrating through the third dielectric layer (106) by a laser ablation process;

A second via hole (V2) penetrating through the second dielectric layer (105) and the metal wiring (104) in the second circuit substrate (100b) is formed by a laser ablation process, and the first via The orthographic projection of the hole (V1) on the first circuit substrate (100a) covers the orthographic projection of the second via hole (V2) on the first circuit substrate (100a).
The preparation method according to any one of claims 16-18, characterized in that, after forming the conductive material (107) in the via hole (V), further comprising:

The third dielectric layer (106) and the conductive material (107) within the via holes of the third dielectric layer (106) are removed.