CN115988155A - Splicing display method and display system - Google Patents
Splicing display method and display system Download PDFInfo
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Abstract
The embodiment of the invention relates to the technical field of video processing, and discloses a splicing display method and a display system, wherein the method comprises the following steps: after the multi-channel video signals are input to the video coding access terminal, controlling the video coding access terminal to perform compression coding on the multi-channel video signals and packaging the multi-channel video signals into Ethernet data packets; sending the Ethernet data packet to an Ethernet chip, and controlling the Ethernet chip to convert the Ethernet data packet into a Serdes signal; controlling the Serdes signal to enter an optical module so that the Serdes signal is transmitted to the optical fiber switching host; sending the communication data output by the optical fiber switching host to any video decoding and splicing terminal; controlling a video decoding splicing terminal to extract communication data so as to obtain a plurality of paths of target video signals; and according to the configuration parameters of the splicing display, the multi-path target video signals are output to a video interface after being subjected to video processing. The invention can effectively reduce the encoding and decoding delay and realize the low-delay networking transmission of the video signal.
Description
Technical Field
The invention relates to the technical field of video processing, in particular to a splicing display method and a splicing display system.
Background
At present, the large-screen splicing is realized by adopting an H.264/H.265 coding and decoding scheme and a standard Ethernet transmission mode in the market, and the technology has the advantages of high compression ratio, small occupied bandwidth and flexible large-scale networking, but the technology has the defects of long delay and low image quality in practice.
Other lossless compression schemes adopted in the industry need to occupy extremely high bandwidth, if uncompressed, 1-path 1080P60 video transmission needs to have a transmission rate of more than 3Gbps, and 1-path 4K30 video needs to have a transmission rate of 6 Gbps. Most of the devices are limited by transmission bandwidth and networking scale, and the general FPGA lossless video transmission can only realize the seat function, so that the devices cannot be applied to large-screen display splicing of multi-channel videos.
Disclosure of Invention
The embodiment of the invention discloses a splicing display method and a splicing display system, which can effectively reduce coding and decoding delay and realize low-delay networking transmission of video signals.
The first aspect of the embodiments of the present invention discloses a tiled display method, including:
after a plurality of paths of video signals are input to a video coding access terminal, controlling the video coding access terminal to perform compression coding on the plurality of paths of video signals and packaging the signals into Ethernet data packets;
sending the Ethernet data packet to an Ethernet chip, and controlling the Ethernet chip to convert the Ethernet data packet into a Serdes signal;
controlling the Serdes signal to enter an optical module so that the Serdes signal is transmitted to an optical fiber switching host;
sending the communication data output by the optical fiber switching host to any video decoding and splicing terminal;
controlling the video decoding and splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals;
and controlling the video decoding and splicing terminal to perform video processing on the multi-path target video signals according to the configuration parameters of splicing display, and outputting the processed target video data to a video interface.
As another optional implementation manner, in the first aspect of the embodiment of the present invention, after the multiple video signals are input to the video coding access terminal, the controlling, by the video coding access terminal, an operation of performing compression coding on the multiple video signals and encapsulating the multiple video signals into ethernet packets includes:
inputting the multi-channel video signals to a video encoder so that the multi-channel video signals are converted into RGB digital signals;
storing the RGB digital signals into a first storage space;
after receiving a video coding control command, reading the RGB digital signals from the first storage space;
and carrying out compression coding and packaging on the RGB digital signal by adopting a run length coding mode to obtain the Ethernet data packet.
As another optional implementation manner, in the first aspect of the embodiment of the present invention, the sending the ethernet packet to an ethernet chip and controlling the ethernet chip to convert the ethernet packet into a Serdes signal includes:
and sending the Ethernet data packet to the Ethernet chip in an RGMII protocol format so that the Ethernet chip converts the Ethernet data packet into the Serdes signal.
As another optional implementation manner, in the first aspect of the embodiment of the present invention, the controlling the video decoding and splicing terminal to perform an extraction operation on the communication data to obtain multiple channels of target video signals includes:
after the video decoding and splicing terminal receives the communication data, decoding the communication data to extract an initial video signal and a control signal; wherein the control signal includes the configuration parameter;
decoding the initial video signal by adopting a run length decoding mode to obtain a plurality of paths of target video signals;
storing the multiple paths of target video signals into a second storage space;
and after receiving a control instruction of display timing and a scaling process, reading out the multiple paths of target video signals from the second storage space.
As another optional implementation manner, in the first aspect of the embodiment of the present invention, the controlling, according to configuration parameters of a splicing display, the video decoding and splicing terminal to perform video processing on the multiple paths of target video signals, and output processed target video data to a video interface includes:
cutting and scaling the multi-path target video signals;
according to the configuration parameters, carrying out layer superposition and OSD superposition on the multi-path target video signals subjected to cutting and scaling processing to obtain the target video data;
and sending the target video data to a DVI interface driving module so as to output the target video data to a DVI decoder chip for display output.
As another optional implementation manner, in the first aspect of the embodiment of the present invention, the method further includes:
the sending synchronization of the data is realized among the video coding access terminals in a mode of connecting synchronous signals in series;
and the display synchronization of the pictures is realized by connecting the video decoding splicing terminals in series through the synchronous signals.
As another optional implementation manner, in the first aspect of the embodiment of the present invention, the sending the communication data output by the fiber switching host to any video decoding and splicing terminal includes:
acquiring the configuration parameters sent by user configuration software;
sending the configuration parameters to the fiber switching host;
after the optical fiber switching host combines the configuration parameters and the Serdes signals into the communication data, the communication data is sent to any video decoding and splicing terminal.
A second aspect of an embodiment of the present invention discloses a display system, including:
the first control unit is used for controlling the operation that the video coding access terminal compresses and codes the multi-channel video signals and packages the multi-channel video signals into Ethernet data packets after the multi-channel video signals are input to the video coding access terminal;
the generating and controlling unit is used for sending the Ethernet data packet to an Ethernet chip and controlling the Ethernet chip to convert the Ethernet data packet into a Serdes signal;
the second control unit is used for controlling the Serdes signals to enter the optical module so that the Serdes signals are sent to the optical fiber switching host;
the sending unit is used for sending the communication data output by the optical fiber switching host to any video decoding and splicing terminal;
the third control unit is used for controlling the video decoding and splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals;
and the fourth control unit is used for controlling the video decoding and splicing terminal to perform video processing on the multi-channel target video signals according to the configuration parameters of splicing display and outputting the processed target video data to a video interface.
As another optional implementation, in a second aspect of the embodiment of the present invention, the first control unit includes:
an input subunit, configured to input the multiple channels of video signals to a video encoder, so that the multiple channels of video signals are converted into RGB digital signals;
the first storage subunit is used for storing the RGB digital signals into a first storage space;
the first reading subunit is used for reading the RGB digital signals from the first storage space after receiving a video coding control command;
and the coding subunit is used for performing compression coding and packaging on the RGB digital signal in a run-length coding mode to obtain the Ethernet data packet.
A third aspect of the embodiments of the present invention discloses a display system, including:
a memory storing executable program code;
a processor coupled with the memory;
the processor calls the executable program code stored in the memory to execute the tiled display method disclosed by the first aspect of the embodiment of the invention.
A fourth aspect of the embodiments of the present invention discloses a computer-readable storage medium, which stores a computer program, where the computer program enables a computer to execute a tiled display method disclosed in the first aspect of the embodiments of the present invention.
A fifth aspect of the embodiments of the present invention discloses a computer program product, which, when running on a computer, causes the computer to execute part or all of the steps of any one of the tiled display methods of the first aspect.
A sixth aspect of the present invention discloses an application publishing platform, where the application publishing platform is configured to publish a computer program product, where when the computer program product runs on a computer, the computer is enabled to execute part or all of the steps of any one of the tiled display methods according to the first aspect.
Compared with the prior art, the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, after a plurality of paths of video signals are input to a video coding access terminal, the video coding access terminal is controlled to perform operations of compressing and coding the plurality of paths of video signals and packaging the signals into Ethernet data packets; sending the Ethernet data packet to an Ethernet chip, and controlling the Ethernet chip to convert the Ethernet data packet into a Serdes signal; controlling the Serdes signal to enter an optical module so that the Serdes signal is transmitted to an optical fiber switching host; sending the communication data output by the optical fiber switching host to any video decoding and splicing terminal; controlling the video decoding and splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals; and controlling the video decoding and splicing terminal to perform video processing on the multi-path target video signals according to the configuration parameters of splicing display, and outputting the processed target video data to a video interface. Therefore, the embodiment of the invention can effectively reduce the coding and decoding delay and realize the transmission of the low-delay networking of the video signals.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a tiled display method disclosed in an embodiment of the present invention;
FIG. 2 is a schematic flow chart of another tiled display method disclosed in the embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a display system according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of another display system disclosed in the embodiments of the present invention;
FIG. 5 is a schematic diagram of another display system according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of an overall structure of a display system according to an embodiment of the present invention;
fig. 7 is an internal structural diagram of a video coding access terminal according to an embodiment of the present invention;
FIG. 8 is an internal structural diagram of an optical fiber switch host according to an embodiment of the present invention;
fig. 9 is an internal structural diagram of a video decoding and splicing terminal disclosed in the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first", "second", "third", "fourth", and the like in the description and the claims of the present invention are used for distinguishing different objects, and are not used for describing a specific order. The terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention discloses a splicing display method and a splicing display system, which can effectively reduce coding and decoding delay and realize the transmission of a video signal low-delay network.
The following detailed description is made with reference to the accompanying drawings.
Example one
Referring to fig. 1, fig. 1 is a schematic flow chart of a tiled display method according to an embodiment of the present invention. As shown in fig. 1, the tiled display method may include the following steps.
101. After the multi-channel video signals are input to the video coding access terminal, the display system controls the video coding access terminal to perform operations of compressing, coding and packaging the multi-channel video signals into Ethernet data packets.
As an alternative implementation manner, in an embodiment of the present invention, please refer to fig. 6, where fig. 6 is a schematic structural diagram of an overall scheme of a display system of the present application, and the display system is composed of a video coding access terminal, a fiber switching host, and a video decoding splicing terminal. The figure comprises 8 video coding access terminals, 1 optical fiber switching host and 2 video decoding splicing terminals, and when an actual system is built, the number of the devices can be increased or decreased according to requirements.
As an optional implementation manner, in the embodiment of the present invention, after the multiple video signals are input to the video coding access terminal, the video coding access terminal may perform compression coding on the multiple video signals, encapsulate the multiple video signals into ethernet packets (complying with the non-IP data format of the ethernet protocol), send the ethernet packets to the ethernet chip, convert the ethernet packets into Serdes signals, enter the optical module, and send the Serdes signals to the optical fiber switching host.
102. The display system sends the Ethernet data packet to the Ethernet chip and controls the Ethernet chip to convert the Ethernet data packet into a Serdes signal.
103. The display system controls the Serdes signal to enter the optical module, so that the Serdes signal is transmitted to the optical fiber switching host.
104. And the display system sends the communication data output by the optical fiber switching host to any video decoding and splicing terminal.
As an optional implementation manner, in an embodiment of the present invention, the fiber switching host in this application may be used to perform data crossing and control on a serdes links, and then the system may send communication data output by the fiber switching host to any video decoding splicing terminal, so as to finally implement multi-terminal networking.
105. And the display system controls the video decoding and splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals.
106. And the display system controls the video decoding and splicing terminal to perform video processing on the multi-path target video signals according to the configuration parameters of splicing display, and outputs the processed target video data to the video interface.
As an optional implementation manner, in the embodiment of the present invention, the configuration parameters of the splicing display in the present application may be sent to the optical fiber switching host by the user configuration software, and then sent to the video encoding access terminal and the video decoding splicing terminal.
As an optional implementation manner, in the embodiment of the present invention, after receiving the communication data from the fiber switching host, the video decoding and splicing terminal may extract and recover the video signal from the communication data, where each 1Gbps signal includes 1 video signal. And then, according to configuration parameters of splicing display, cutting, scaling, layer superposition, subtitle superposition and other operations can be carried out on up to 8 paths of video signals, and finally the video signals are output to a DVI video interface.
As an optional implementation manner, in the embodiment of the present invention, a plurality of video coding access terminals, optical fiber switching hosts, and video decoding and splicing terminals may be provided in one display system, so as to implement splicing display of a super-large screen.
As an optional implementation manner, in the embodiment of the present invention, data transmission synchronization may be implemented between multiple video coding access terminals in the present application in a manner of serial connection of synchronization signals, and display synchronization of pictures may be implemented between multiple video decoding splicing terminals in a manner of serial connection of synchronization signals, so as to ensure synchronous output of display pictures of each final splicing screen.
In the tiled display method of fig. 1, a display system is described as an example of an execution subject. It should be noted that the execution main body of the tiled display method in fig. 1 may also be an independent device associated with a display system, and the embodiment of the present invention is not limited.
Therefore, the implementation of the splicing display method described in fig. 1 can effectively reduce the coding and decoding delay, and realize the low-delay networking transmission of video signals.
In addition, by implementing the tiled display method described in fig. 1, synchronous output of display frames of each tiled screen can be ensured.
Example two
Referring to fig. 2, fig. 2 is a schematic flow chart of another tiled display method according to the embodiment of the present invention. As shown in fig. 2, the tiled display method may include the following steps:
201. the display system inputs the plurality of video signals to the video encoder so that the plurality of video signals are converted into RGB digital signals.
202. The display system stores the RGB digital signals into a first storage space.
203. After receiving the video coding control command, the display system reads out the RGB digital signals from the first storage space.
204. The display system adopts a run-length coding mode to compress, code and package the RGB digital signals so as to obtain the Ethernet data packet.
205. The display system sends the ethernet packet to the ethernet chip in the format of RGMII protocol, so that the ethernet chip converts the ethernet packet into a Serdes signal.
As an optional implementation manner, in an embodiment of the present invention, please refer to fig. 7, where fig. 7 is an internal structure diagram of a video coding access terminal disclosed in the embodiment of the present invention, as shown in the figure, an FPGA chip of the video coding access terminal is an FPGA chip adopting the cyclenve series of INTEL corporation, and 2 DDRs are externally connected to the FPGA chip as a buffer space of video frame data. The HDMI video encoder may implement conversion of the video signal of 4K30 into an RGB digital signal.
As an alternative implementation manner, in the embodiment of the present invention, the system may write the RGB digital signals passing through the line buffer and the DDR controller into the external DDR register, and then may read out the video signals according to the video encoding control instruction, and perform video compression encoding. The video compression coding in the application adopts run-length coding (also called run-length coding), and the general computer desktop signals can be compressed to more than 6 times through the run-length coding, namely 4K30 signals which originally need 6Gbps bandwidth to be transmitted can be transmitted only through 1Gbps through the run-length coding. The compressed and coded data is sent to the Ethernet PHY chip for transmission in the format of RGMII protocol. The Ethernet PHY chip converts the RGMII data into serdes signals, and finally the signals are transmitted through the optical module.
206. The display system controls the Serdes signal to enter the optical module, so that the Serdes signal is transmitted to the optical fiber switching host.
207. The display system obtains the configuration parameters sent by the user configuration software.
208. The display system sends the configuration parameters to the fiber switching host.
209. After the optical fiber switching host converges the configuration parameters and the Serdes signals into communication data, the display system sends the communication data to any video decoding splicing terminal.
As an optional implementation manner, in an embodiment of the present invention, please refer to fig. 8, where fig. 8 is an internal structure diagram of an optical fiber switching host disclosed in the embodiment of the present invention, as shown in the figure, the optical fiber switching host may use multiple FPGAs as data switching chips, where one backplane FPGA implements backbone data switching; the FPGA with a plurality of interface boards realizes the exchange of interface branch data; and a CycloneV chip of the main control board is used as a main control chip of the optical fiber exchange host.
As an optional implementation manner, in the embodiment of the present invention, the functions mainly implemented by the optical fiber switch host in the present application include rate configuration of an optical fiber channel, signal routing of each channel, monitoring of an acquisition interface state, and the like. The highest speed of the high-speed transceiver of the FPGA of the backboard and the interface board exceeds 12Gbps, the scheme uses 1Gbps speed standard on an interface, and uses 10Gbps speed standard on data exchange between the backboard and the interface board. The SOC system of the main control board is used as a configuration CPU and is connected with a user configuration computer through a standard Ethernet. And configuring visual interface configuration software installed on a computer, wherein the visual interface configuration software is used for controlling large-screen display and signal allocation, control signals are sent to the optical fiber switching host through the Ethernet, and the SOC of the optical fiber switching host sends configuration information to each FPGA chip to perform data exchange configuration of an optical fiber Serdes channel.
210. After the video decoding and splicing terminal receives the communication data, the display system decodes the communication data to extract an initial video signal and a control signal; the control signal includes configuration parameters.
211. The display system decodes the initial video signal by adopting a run-length decoding mode to obtain a plurality of paths of target video signals.
212. The display system stores the plurality of paths of target video signals into the second storage space.
213. After receiving the control command of the display timing and the scaling process, the display system reads out the multiple paths of target video signals from the second storage space.
214. The display system performs clipping and scaling processing on the multi-path target video signal.
215. And the display system performs layer superposition and OSD superposition on the multi-channel target video signals subjected to cutting and scaling processing according to the configuration parameters to obtain target video data.
216. And the display system sends the target video data to the DVI interface driving module so as to output the target video data to the DVI decoder chip for display output.
As an optional implementation manner, in an embodiment of the present invention, please refer to fig. 9, where fig. 9 is an internal structure diagram of a video decoding and splicing terminal disclosed in the embodiment of the present invention, as shown in the figure, the video decoding and splicing terminal may use an FPGA of Xilinx corporation as a video data processing chip, and the outside may use 4 pieces of 1Gbit DDR as a video frame data buffer space, and use a DVI decoder as a video decoding chip.
As an optional implementation manner, in the embodiment of the present invention, each optical module signal enters an IP core 1G/2.5G Ethernet PCS/pmaorsgmii (servers of XILINX FPGA are converted into an IP core of RGMII) of the FPGA, so that the video decoding and splicing terminal receives data sent by the fiber switching host through a fiber channel, and then the system may control the video decoding and splicing terminal to decode the data, and extract the video signal and the control signal. The control signal is used for configuring display parameters, such as display resolution, layer size, display coordinates, OSD superimposition parameters, and the like. The video signal needs to undergo run-length decoding (i.e. reverse decoding of run-length coding) to obtain real video data, and the real video data is stored in the DDR through a line buffer and a DDR controller. The system can read out the video content which needs to be cut, zoomed and displayed from the DDR controller according to the display time sequence and the zooming process control, then the system can converge the processed video data signals to carry out layer superposition and OSD superposition according to the control parameters, finally the video RGB data can be sent to the DVI interface driving module, and finally the video RGB data is output to the DVI decoder chip to be displayed and output.
As an optional implementation manner, in the embodiment of the present invention, the FPGA chip may be used as a carrier for video encoding, decoding, and transmission, run-length encoding is used to improve the video transmission bandwidth utilization rate, which can achieve 1Gbps bandwidth transmission of 1-channel 4K30 video or 1-channel 1080P60 video, and the characteristics of low delay and flexible programming of the FPGA chip are fully utilized to implement low-delay networking transmission of video signals and large-screen splicing with high image quality, flexible configuration, and high security.
Therefore, by implementing another splicing display method described in fig. 2, the encoding and decoding delay can be effectively reduced, and the transmission of the video signal low-delay networking is realized.
In addition, implementing another tiled display method described in fig. 2 can avoid confusion of tiled patterns due to delay in video transmission.
EXAMPLE III
Referring to fig. 3, fig. 3 is a schematic structural diagram of a display system according to an embodiment of the disclosure. As shown in fig. 3, the display system 300 may include a first control unit 301, a generation and control unit 302, a second control unit 303, a transmission unit 304, a third control unit 305, and a fourth control unit 306, wherein:
a first control unit 301, configured to control the video coding access terminal to perform compression coding on the multiple channels of video signals and encapsulate the multiple channels of video signals into ethernet packets after the multiple channels of video signals are input to the video coding access terminal.
And a generating and controlling unit 302, configured to send the ethernet packet to the ethernet chip, and control the ethernet chip to convert the ethernet packet into a Serdes signal.
And a second control unit 303, configured to control the Serdes signal to enter the optical module, so that the Serdes signal is sent to the optical fiber switching host.
And the sending unit 304 is configured to send the communication data output by the optical fiber switching host to any video decoding and splicing terminal.
And a third control unit 305, configured to control the video decoding and splicing terminal to perform an extraction operation on the communication data to obtain multiple channels of target video signals.
And a fourth control unit 306, configured to control the video decoding and splicing terminal to perform video processing on the multiple paths of target video signals according to the configuration parameters of the splicing display, and output the processed target video data to the video interface.
Therefore, the display system described in fig. 3 can effectively reduce the encoding and decoding delay, and realize the transmission of the video signal low-delay networking.
In addition, implementing the display system described in fig. 3, confusion of the stitching pattern due to delay in video transmission can be avoided.
Example four
Referring to fig. 4, fig. 4 is a schematic structural diagram of another display system according to an embodiment of the disclosure. The display system of fig. 4 is optimized from the display system of fig. 3. Compared with the display system of fig. 3, the first control unit 301 of fig. 4 includes:
an input sub-unit 3011, configured to input the multiple video signals to a video encoder, so that the multiple video signals are converted into RGB digital signals.
The first storage subunit 3012 is configured to store the RGB digital signals in a first storage space.
The first reading subunit 3013 is configured to, after receiving the video coding control instruction, read out the RGB digital signals from the first storage space.
And the encoding subunit 3014 is configured to perform compression encoding and packaging on the RGB digital signals in a run-length encoding manner to obtain an ethernet packet.
Compared to the display system of fig. 3, the generation-and-control unit 302 of fig. 4 includes:
a first sending subunit 3021, configured to send the ethernet packet to the ethernet chip in the format of the RGMII protocol, so that the ethernet chip converts the ethernet packet into a Serdes signal.
Compared to the display system of fig. 3, the third control unit 305 of fig. 4 includes:
the decoding subunit 3051, configured to decode the communication data after the video decoding and splicing terminal receives the communication data, so as to extract an initial video signal and a control signal; the control signal includes configuration parameters.
As an optional implementation manner, in this embodiment of the present invention, the decoding sub-unit 3051 is further configured to decode the initial video signal by using run-length decoding, so as to obtain multiple paths of target video signals.
And a second storage subunit 3052, configured to store the multiple paths of target video signals in the second storage space.
And a second reading sub-unit 3053, configured to, after receiving the control instruction of the display timing and the scaling process, read out the multiple paths of target video signals from the second storage space.
Compared to the display system of fig. 3, the fourth control unit 306 of fig. 4 includes:
the processing subunit 3061 is used to perform cropping and scaling processing on the multiple paths of target video signals.
As an alternative implementation manner, in the embodiment of the present invention, the processing subunit 3061 is further configured to perform, according to the configuration parameter, layer superposition and OSD superposition processing on the multiple paths of target video signals subjected to the cropping and scaling processing, so as to obtain the target video data.
And a second sending subunit 3062, configured to send the target video data to the DVI interface driving module, so as to output the target video data to the DVI decoder chip for display and output.
Compared with the display system of fig. 3, the transmitting unit 304 of fig. 4 includes:
the obtaining subunit 3041 is configured to obtain the configuration parameters sent by the user configuration software.
A third sending subunit 3042, configured to send the configuration parameters to the fiber switch host.
And a fourth sending subunit 3043, configured to send the communication data to any video decoding and splicing terminal after the fiber switching host merges the configuration parameters and the Serdes signal into the communication data.
It can be seen that another display system as described in fig. 4 can be implemented to support a plurality of modes of switching between different rates.
In addition, the display system described in fig. 4 can be implemented to effectively solve the problem that the exchange scale is difficult to expand.
EXAMPLE five
Referring to fig. 7, fig. 7 is a schematic structural diagram of another display system according to an embodiment of the disclosure. As shown in fig. 7, the display system may include:
a memory 501 in which executable program code is stored;
a processor 502 coupled to a memory 501;
the processor 502 calls the executable program code stored in the memory 501 to execute any one of the tiled display methods shown in fig. 1-2.
The embodiment of the invention discloses a computer-readable storage medium which stores a computer program, wherein the computer program enables a computer to execute any one of the splicing display methods shown in the figures 1-2.
Embodiments of the present invention also disclose a computer program product, wherein, when the computer program product is run on a computer, the computer is caused to execute part or all of the steps of the method as in the above method embodiments.
It will be understood by those skilled in the art that all or part of the steps in the methods of the above embodiments may be implemented by instructions associated with a program, which may be stored in a computer-readable storage medium, including a Read-Only Memory (ROM), a Random Access Memory (RAM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), a One-time Programmable Read-Only Memory (OTPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Compact Disc Read-Only Memory (CD-ROM) or other Memory capable of storing data, a magnetic tape, or any other computer-readable medium capable of storing data.
The embodiment of the present invention discloses a splicing display method and a display system, and a specific embodiment is applied in the text to explain the principle and the implementation of the present invention, and the description of the embodiment is only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A tiled display method, comprising:
after a plurality of paths of video signals are input to a video coding access terminal, controlling the video coding access terminal to perform compression coding on the plurality of paths of video signals and packaging the signals into Ethernet data packets;
sending the Ethernet data packet to an Ethernet chip, and controlling the Ethernet chip to convert the Ethernet data packet into a Serdes signal;
controlling the Serdes signal to enter an optical module so that the Serdes signal is transmitted to an optical fiber switching host;
sending the communication data output by the optical fiber switching host to any video decoding splicing terminal;
controlling the video decoding and splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals;
and controlling the video decoding and splicing terminal to perform video processing on the multi-path target video signals according to the configuration parameters of splicing display, and outputting the processed target video data to a video interface.
2. The method according to claim 1, wherein the controlling the video coding access terminal to perform the operations of compression coding and encapsulating the multiple video signals into ethernet packets after the multiple video signals are input to the video coding access terminal comprises:
inputting the multi-channel video signals to a video encoder so that the multi-channel video signals are converted into RGB digital signals;
storing the RGB digital signals into a first storage space;
after receiving a video coding control command, reading the RGB digital signals from the first storage space;
and carrying out compression coding and packaging on the RGB digital signal by adopting a run length coding mode to obtain the Ethernet data packet.
3. The method of claim 2, wherein sending the ethernet packet to an ethernet chip and controlling the ethernet chip to translate the ethernet packet into a Serdes signal comprises:
and sending the Ethernet data packet to the Ethernet chip in an RGMII protocol format so that the Ethernet chip converts the Ethernet data packet into the Serdes signal.
4. The method of claim 3, wherein the controlling the video decoding and splicing terminal to perform the extraction operation on the communication data to obtain multiple target video signals comprises:
after the video decoding and splicing terminal receives the communication data, decoding the communication data to extract an initial video signal and a control signal; wherein the control signal includes the configuration parameter;
decoding the initial video signal by adopting a run length decoding mode to obtain a plurality of paths of target video signals;
storing the multi-path target video signals into a second storage space;
and after receiving a control command of display timing and a scaling process, reading out the multi-channel target video signals from the second storage space.
5. The method according to claim 4, wherein the controlling the video decoding and splicing terminal to perform video processing on the multiple target video signals according to the configuration parameters of the splicing display and output the processed target video data to a video interface comprises:
cutting and scaling the multi-path target video signals;
according to the configuration parameters, carrying out layer superposition and OSD superposition on the multi-path target video signals subjected to cutting and scaling processing to obtain the target video data;
and sending the target video data to a DVI interface driving module so as to output the target video data to a DVI decoder chip for display output.
6. The method of any of claims 1~5, further comprising:
the plurality of video coding access terminals realize data transmission synchronization in a mode of connecting synchronous signals in series;
and the display synchronization of the pictures is realized by connecting the video decoding splicing terminals in series through the synchronous signals.
7. The method according to claim 1, wherein the sending the communication data output by the fiber switching host to any video decoding and splicing terminal comprises:
acquiring the configuration parameters sent by user configuration software;
sending the configuration parameters to the fiber switching host;
after the optical fiber switching host combines the configuration parameters and the Serdes signals into the communication data, the communication data is sent to any video decoding and splicing terminal.
8. A display system, characterized in that the display system comprises:
the first control unit is used for controlling the operation that the video coding access terminal compresses and codes the multi-channel video signals and packages the multi-channel video signals into Ethernet data packets after the multi-channel video signals are input to the video coding access terminal;
the generating and controlling unit is used for sending the Ethernet data packet to an Ethernet chip and controlling the Ethernet chip to convert the Ethernet data packet into a Serdes signal;
the second control unit is used for controlling the Serdes signals to enter the optical module so that the Serdes signals are sent to the optical fiber switching host;
the sending unit is used for sending the communication data output by the optical fiber switching host to any video decoding and splicing terminal;
the third control unit is used for controlling the video decoding and splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals;
and the fourth control unit is used for controlling the video decoding and splicing terminal to perform video processing on the multi-channel target video signals according to the configuration parameters of splicing display and outputting the processed target video data to a video interface.
9. The display system according to claim 8, wherein the first control unit includes:
an input subunit, configured to input the multiple channels of video signals to a video encoder, so that the multiple channels of video signals are converted into RGB digital signals;
the first storage subunit is used for storing the RGB digital signals into a first storage space;
a first reading subunit, configured to, after receiving a video coding control instruction, read out the RGB digital signals from the first storage space;
and the coding subunit is used for performing compression coding and packaging on the RGB digital signal in a run-length coding mode to obtain the Ethernet data packet.
10. A display system, characterized in that the display system comprises:
a memory storing executable program code;
a processor coupled with the memory;
the processor calls the executable program code stored in the memory to execute the tiled display method according to any of claims 1-7.
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| US20050273837A1 (en) * | 2004-05-12 | 2005-12-08 | Oyadomari Randy I | Single master clock control of ethernet data transfer over both a cable TV return path and an ethernet forward path |
| CN111010616A (en) * | 2019-12-23 | 2020-04-14 | 威创集团股份有限公司 | Audio and video transmission method and system based on IP network |
| CN112019863A (en) * | 2020-09-04 | 2020-12-01 | 威创集团股份有限公司 | Control system for video display |
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