CN213403261U

CN213403261U - HDMI video transmission system

Info

Publication number: CN213403261U
Application number: CN202022898733.5U
Authority: CN
Inventors: 熊安永; 尹月桂; 丘世坚
Original assignee: Shenzhen Anruixin Technology Co ltd
Current assignee: Shenzhen Anruixin Technology Co ltd
Priority date: 2020-12-04
Filing date: 2020-12-04
Publication date: 2021-06-08
Anticipated expiration: 2030-12-04

Abstract

The present application relates to an HDMI video transmission system. An external video signal source inputs signals to an HDMI decoding chip through a first HDMI connector, the HDMI decoding chip decodes the input data into video data and audio data and sends the video data and the audio data to a first central processing unit, the first central processing unit processes the received data and then outputs the processed data to a first Ethernet PHY chip for encoding, and then the encoded data is output to a receiver through a first network connector. After receiving the data input by the transmitter, the second network connector in the receiver decodes the data by the second Ethernet PHY chip and outputs the decoded data to the second central processing unit, the second central processing unit processes the received data, and the processed video signal and audio signal are encoded into an outputtable data stream by the HDMI encoding chip and output to the second HDMI connector, so that the transmission of the video signal is realized. The structure of the application has good flexibility, and one or more transmitters and receivers can be arranged according to requirements.

Description

HDMI video transmission system

Technical Field

The application relates to the technical field of video transmission, in particular to an HDMI video transmission system.

Background

HDMI (High Definition Multimedia Interface) is a fully digital video and audio transmission Interface, can provide a data transmission bandwidth of up to 4.96Gbps, and can transmit uncompressed audio signals and High-resolution video signals. Meanwhile, the digital-to-analog or analog-to-digital conversion is not needed before signal transmission, and the transmission of the video-audio signal with the highest quality can be ensured.

The HDMI matrix is a high-performance professional digital signal switching device, which is used for cross switching of a plurality of HDMI signal source inputs and HDMI display device outputs, any signal source can be freely selected by any signal output without interfering other outputs, signal transmission attenuation is reduced to the lowest, and high-fidelity output of video image signals is realized. However, the conventional HDMI matrix has a single mode and cannot be expanded at will, and once the number of displays in a scene exceeds the number of ports of the HDMI matrix, the HDMI matrix can only be replaced by a matrix with more ports.

Disclosure of Invention

In order to facilitate improving the expandability of the HDMI matrix for video transmission, the application provides an HDMI video transmission system.

The application provides a HDMI video transmission system, adopts following technical scheme:

an HDMI video transmission system comprising: a transmitter and a receiver;

the transmitter comprises an HDMI decoding chip, a first central processing unit, a first Ethernet PHY chip and a first network connector; the output end of the HDMI decoding chip is connected with a first central processing unit, the first central processing unit is connected with a first Ethernet PHY chip, and the first Ethernet PHY chip is connected with a first network connector;

the receiver comprises an HDMI coding chip, a second central processing unit, a second Ethernet PHY chip and a second network connector; the input end of the HDMI coding chip is connected with a second central processing unit, the second central processing unit is connected with a second Ethernet PHY chip, and the second Ethernet PHY chip is connected with a second network connector; the first network connector is in communication connection with the second network connector.

By adopting the technical scheme, the HDMI decoding chip can decode the input data stream into parallel video data and audio data and process the parallel video data and the audio data by the central processing unit, and the central processing unit correspondingly processes the received data and outputs the processed data to the Ethernet PHY chip for encoding and then outputs the encoded data to the receiver by the network connector. After receiving the data input by the transmitter, the network connector in the receiver decodes the data by the Ethernet PHY chip and outputs the decoded data to a corresponding part of the central processing unit for processing, and the video and the audio are encoded into an outputable data stream by the HDMI encoding chip and output to the HDMI connector. The application has simple structure, and can increase the transmitter or the receiver as required.

Optionally, the transmitter further includes an HDMI connector, an input end of the HDMI connector is connected to an external video signal source, and an output end of the HDMI connector is connected to an input end of the HDMI decoding chip.

By adopting the technical scheme, the HDMI connector is connected with the external video signal source and the HDMI decoding chip, and uncompressed video signals and audio signals in the video signal source can be input to the HDMI decoding chip through the HDMI connector.

Optionally, the receiver further includes an HDMI connector, an input end of the HDMI connector is connected to an output end of the HDMI encoding chip, and an output end of the HDMI connector is connected to an external device.

By adopting the technical scheme, the HDMI connector is connected with the external equipment and the HDMI coding chip, and the serial data stream coded by the HDMI coding chip can be output to the external equipment through the HDMI connector.

Optionally, the first central processing unit includes a video coding module, a first GPIO interface, and a first MAC chip; the input end of the video coding module and the input end of the first GPIO interface are both connected with the output end of the HDMI decoding chip, the output end of the video coding module and the output end of the first GPIO interface are both connected with the input end of the first MAC chip, and the first MAC chip is connected with the first Ethernet HPY chip.

By adopting the technical scheme, the HDMI decoding chip decodes the video signal source into the video signal and the audio signal, the video coding module processes the video signal, the first GPIO interface processes the audio signal, and the first MAC chip packages the processed video signal and the processed audio signal into the network data frame and transmits the network data frame to the first Ethernet PHY chip.

Optionally, the second central processing unit includes a video decoding module, a second GPIO interface, and a second MAC chip; the second MAC chip is connected with the second Ethernet HPY chip, the input end of the video decoding module and the input end of the second GPIO interface are both connected with the output end of the second MAC chip, and the output end of the video decoding module and the output end of the second GPIO interface are both connected with the input end of the HDMI coding chip.

By adopting the technical scheme, the second MAC chip unpacks the received data frame into the video signal and the audio signal, the video decoding module processes the video signal, the second GPIO interface processes the audio signal, and then the processed video signal and the processed audio signal are transmitted to the HDMI coding chip.

Optionally, the first network connector comprises a first RJ45 connector; the second network connector comprises a second RJ45 connector.

By adopting the technical scheme, the first network connector and the second network connector both adopt RJ45 connectors, and the RJ45 connector has good anti-attenuation and anti-crosstalk capabilities and is safe and reliable in signal transmission.

Optionally, the first RJ45 connector and the second RJ45 connector are connected through a network cable.

By adopting the technical scheme, the first RJ45 connector in the transmitter and the second RJ45 connector in the receiver are connected through the network cable, and the transmission of signals between the transmitter and the receiver is realized.

Optionally, the number of the transmitters and receivers is one or more.

By adopting the technical scheme, the transmitter and the receiver can be added according to the requirement by virtue of the flexibility of the network, and one-to-one, one-to-many and many-to-many connection modes are conveniently realized.

To sum up, the application comprises the following beneficial technical effects:

1. by means of the flexibility of the network protocol, efficient transmission of video data can be achieved only by assembling a simple local area network. And a transmitter or a receiver can be added as required, so that one-to-one, one-to-many and many-to-many connection modes can be realized conveniently, various splicing and switching modes can be realized by the connection mode, and the capacity expansion is simple.

2. This application carries out data transmission through the RJ45 connector, has good anti-decay, anti crosstalk ability, safe and reliable when carrying out signal transmission.

Drawings

Fig. 1 is a schematic structural diagram of an HDMI video transmission system according to an embodiment of the present application.

Fig. 2 is a topology structure diagram of an HDMI video transmission system according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The present embodiment is only for explaining the present application, and it is not limited to the present application, and those skilled in the art can make modifications of the present embodiment without inventive contribution as needed after reading the present specification, but all of them are protected by patent law within the scope of the claims of the present application.

As shown in fig. 1, an embodiment of the present application discloses an HDMI video transmission system, including: a transmitter and a receiver.

The transmitter comprises a first HDMI connector, an HDMI decoding chip, a first central processing unit, a first Ethernet PHY chip and a first network connector. The first central processing unit comprises a video coding module, a first GPIO interface and a first MAC chip. The input end of the HDMI connector is connected with an external video signal source, and the output end of the HDMI connector is connected with the input end of the HDMI decoding chip. The output end of the HDMI decoding chip is connected with the input end of the video coding module and the input end of the first GPIO interface. The output end of the video coding module and the output end of the first GPIO interface are connected with the input end of the first MAC chip. The first MAC chip is connected with the first Ethernet HPY chip, and the first Ethernet PHY chip is connected with the first network connector.

The receiver comprises a second HDMI connector, an HDMI coding chip, a second central processing unit, a second Ethernet PHY chip and a second network connector. The second central processing unit comprises a video decoding module, a second GPIO interface and a second MAC chip. The second network connector is connected with the second Ethernet PHY chip, the second Ethernet PHY chip is connected with the second MAC chip, the output end of the second MAC chip is respectively connected with the input end of the video decoding module and the input end of the second GPIO interface, the output end of the video decoding module and the output end of the second GPIO interface are both connected to the input end of the HDMI coding chip, the output end of the HDMI coding chip is connected with the input end of the second HDMI connector, and the output end of the second HDMI connector is connected to an external device.

In this embodiment, the first network connector may be a first RJ45 connector; the second network connector may be a second RJ45 connector. RJ is an abbreviation for Registered Jack, meaning "Registered Jack". The RJ45 connector is composed of a plug and a socket, and the connector composed of these two components is connected between the wires to achieve electrical continuity of the wires. The RJ45 connector has the advantages of low cost, no signal attenuation, and convenient and reliable connection, so the RJ45 connector is selected to realize the attenuation-free and reliable transmission of data in this embodiment.

In the present embodiment, the first RJ45 connector and the second RJ45 connector are connected by a CAT5E cable or a CAT6 cable. Specifically, since the CAT5E cable and the CAT6 cable, i.e., the extra-five type cable and the six type cable, have characteristics of high signal transmission frequency and high signal transmission rate, in the present embodiment, the cable connecting the first RJ45 connector and the second RJ45 connector may specifically adopt the CAT5E cable and the CAT6 cable, so as to realize efficient data transmission between the first RJ45 connector and the second RJ45 connector through the CAT5E cable and the CAT6 cable.

In this embodiment, the first MAC chip and the second MAC chip both employ 1GbpsMAC chips. MAC is a media access control sublayer protocol, which is located below the data link layer in the OSI seven-layer protocol, and the layer protocol is that Ethernet MAC is defined by the IEEE-802.3 Ethernet standard. The 1GbpsMAC chip used in this embodiment has a high-speed data processing capability, and can repackage and encapsulate received video data and audio data into a network data frame, where the network data frame includes a target MAC address, a source MAC address, and a protocol type in the received data.

In this embodiment, the first ethernet PHY chip and the second ethernet PHY chip are both gigabit ethernet PHY chips. The PHY, i.e., the physical layer, may transmit and receive data frames from the MAC. The gigabit ethernet has the characteristics of high efficiency, high speed and high performance, and the gigabit ethernet PHY chip is adopted in this embodiment to transmit the network data frame sent by the MAC chip, so that a large amount of data can be transmitted, and the phenomenon of network congestion during transmission of a large amount of data is effectively avoided. The gigabit Ethernet PHY chip can also detect whether data is transmitted on the network, wait if the data is transmitted, wait for a random time to transmit the data once the network is detected to be idle, and wait for a random time to retransmit the data if data collision is found.

The working principle is as follows:

the external video signal source inputs signals to the HDMI decoding chip through the first HDMI connector, and the HDMI decoding chip decodes the received HDMI TMDS serial data stream into RGB/YUV parallel video data and IIS audio data. The video data and the audio data are processed separately, the RGB/YUV parallel video data are sent to a video coding module for video coding, the IIS audio data are sent to a first GPIO interface, the processed video signals and audio signals are transmitted to a first MAC chip for packaging, the packaged signals are network data frames, and then the network data frames are transmitted to a first Ethernet PHY chip for coding. The first Ethernet PHY chip receives the network data frame sent by the first MAC chip, then converts the network data frame into a serial data stream, codes the data according to the coding rule of the physical layer, and converts the data into an analog signal which is output to a receiver by the first RJ45 connector.

After a second RJ45 connector in the receiver receives data input by a first RJ45 connector through a CAT5E network cable or a CAT6 network cable, a second Ethernet PHY chip performs data decoding on analog signals according to the section rule of a physical layer, serial data are converted into parallel network data frames, the network data frames are output to a second MAC chip, the second MAC chip unpacks the network data frames, transmits video signals to a video decoding module for processing, transmits audio signals to a second GPIO interface, encodes the processed video signals and audio signals into TMDS serial data streams through an HDMI coding chip and outputs the TMDS serial data streams to a second HDMI connector, and the second HDMI connector transmits the signals to corresponding external equipment, so that transmission of the video signals is achieved.

As shown in fig. 2, in the present embodiment, one or more transmitters, one or more receivers, and at most 253 transmitters and receivers may be provided according to actual requirements. When a plurality of transmitters and a plurality of receivers are provided, signal transmission can be performed between the plurality of transmitters and the plurality of receivers through the switch connection.

When a plurality of transmitters and a plurality of receivers are arranged, the switching mode and the splicing mode of video transmission are conveniently realized through the HDMI video transmission system disclosed by the application.

When a user performs a picture switching operation at an external device end, a corresponding switching command is sent to a sender through an external device (such as a desktop computer, a notebook computer, a camera and other devices), the sender analyzes the switching command to obtain a switching target, the switching target comprises video information of a picture to be switched, then a switching target instruction is sent to a receiver of the corresponding device, and the receiver processes the received instruction to obtain a switching target picture, so that the switching operation is completed.

When a user carries out video splicing at an external device end, firstly, video information to be spliced is set on the external device, and each receiver is allocated with a display interval. The external equipment sends a corresponding splicing command to the sender, the sender analyzes the splicing command to obtain a splicing target after analysis, the splicing target comprises video information to be spliced, then the splicing target is sent to each receiver to be spliced, the receivers correspondingly analyze the network data frame after receiving the network data frame, and the video data of the corresponding display interval part is processed, output and displayed.

The above embodiments are only used to describe the technical solutions of the present application in detail, but the above embodiments are only used to help understanding the technical solutions of the present application, and the protection scope of the present application is not limited by this, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.

Claims

1. An HDMI video transmission system comprising: a transmitter and a receiver; the transmitter is characterized by comprising an HDMI decoding chip, a first central processing unit, a first Ethernet PHY chip and a first network connector; the output end of the HDMI decoding chip is connected with a first central processing unit, the first central processing unit is connected with a first Ethernet PHY chip, and the first Ethernet PHY chip is connected with a first network connector;

2. The HDMI video transmission system of claim 1, wherein the transmitter further comprises an HDMI connector, an input of the HDMI connector is connected to an external video signal source, and an output of the HDMI connector is connected to an input of the HDMI decoding chip.

3. The HDMI video transmission system of claim 1, wherein the receiver further comprises an HDMI connector, an input of the HDMI connector is connected to an output of the HDMI coding chip, and an output of the HDMI connector is connected to an external device.

4. The HDMI video transmission system of claim 1, wherein said first central processor comprises a video encoding module, a first GPIO interface, and a first MAC chip; the input end of the video coding module and the input end of the first GPIO interface are both connected with the output end of the HDMI decoding chip, the output end of the video coding module and the output end of the first GPIO interface are both connected with the input end of the first MAC chip, and the first MAC chip is connected with the first Ethernet HPY chip.

5. The HDMI video transmission system of claim 1, wherein said second central processor comprises a video decoding module, a second GPIO interface and a second MAC chip; the second MAC chip is connected with the second Ethernet HPY chip, the input end of the video decoding module and the input end of the second GPIO interface are both connected with the output end of the second MAC chip, and the output end of the video decoding module and the output end of the second GPIO interface are both connected with the input end of the HDMI coding chip.

6. The HDMI video transmission system of claim 1, wherein said first network connector comprises a first RJ45 connector; the second network connector comprises a second RJ45 connector.

7. The HDMI video transmission system of claim 6, wherein the first RJ45 connector and the second RJ45 connector are connected by a cable.

8. The HDMI video transmission system of claim 1, wherein said number of transmitters and receivers is one or more.