CN114339070B - MPSoC-based multipath image processing display interaction system - Google Patents
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Abstract
The application provides a MPSoC-based multipath image processing display interaction system, which comprises a video acquisition module, wherein different video sources are respectively converted into a unified video data format by adopting corresponding processing modes to obtain first video data; the video scaling and splicing module is connected with the video acquisition module and used for scaling and splicing the first video data to obtain second video data; the display interaction module is connected with the video scaling splicing module, and is used for displaying the second video data and controlling each module; the video processing module is connected with the video acquisition module and the display interaction module, and compresses and encapsulates the first video data according to the control of the display interaction module to obtain third video data; the video output module is connected with the video processing module and the display interaction module, and outputs third video data according to the control of the display interaction module. By the processing scheme, real-time display, coding storage and transmission of multiple paths of different video input sources are realized.
Description
Technical Field
The application relates to the technical field of image processing display, in particular to a MPSoC-based multipath image processing display interaction system.
Background
With the development of video applications, a plurality of video input sources acquire application scenes of coding output. In some important fields, such as the on-board display field, there is often a diversified requirement for real-time display, code storage, and transmission of multiple different video input sources.
At present, common solutions include an FPGA+Hai Si 3559 scheme, an FPGA+DSP scheme and the like, wherein the FPGA+Hai Si 3559 scheme has weaker GPU performance of Hai Si 3559 and large desktop system transplanting difficulty; the FPGA+DSP scheme does not have an interactive system and has great development difficulty, so that more problems still exist on how to meet the requirements of real-time display, coding storage, transmission and the like of multiple different video input sources in the relevant fields of airborne display and the like.
Disclosure of Invention
In view of this, the embodiment of the application provides a MPSoC-based multi-channel image processing display interaction system, which is used for meeting the requirements of real-time display, coding storage, transmission and the like of multiple different video input sources in the related fields of airborne display and the like.
The embodiment of the application provides a MPSoC-based multipath image processing display interaction system, which comprises:
the video acquisition module is connected with the video sources and is used for converting different video sources into a unified video data format by adopting corresponding processing modes respectively to obtain first video data;
the input end of the video scaling and splicing module is connected with the video acquisition module and is used for scaling and splicing the first video data to obtain second video data;
the input end of the display interaction module is connected with the output end of the video scaling splicing module and is used for displaying the second video data and controlling each module connected with the display interaction module;
the input end of the video processing module is respectively connected with the output end of the video acquisition module and the output end of the display interaction module, and is used for compressing and packaging the first video data according to the control of the display interaction module to obtain third video data;
and the input end of the video output module is respectively connected with the output end of the video processing module and the output end of the display interaction module, and is used for outputting the third video data according to the control of the display interaction module.
According to a specific implementation of an embodiment of the present application, the video acquisition module comprises a combination of one or more of a BT1120 decoding module, an HDMI decoding module, a Mipi decoding module, a BT656 decoding module, an SDI decoding module and a network stream decoding module,
the BT1120 decoding module is used for decoding the input BT1120 video signals and separating lines, fields and enabling signals required by the video in the internal transmission process of the FPGA;
the HDMI decoding module is used for realizing the analysis of HDMI video protocol;
the MIpi decoding module is used for realizing the analysis of MIPI video;
the BT656 decoding module is used for decoding the input BT656 video signals and separating lines, fields and enabling signals required by the video in the internal transmission process of the FPGA;
the SDI decoding module is used for decoding an input SDI video signal;
the network stream decoding module is used for decoding the input network stream video signal.
According to a specific implementation manner of the embodiment of the application, the BT656 decoding module uses a TW9984 chip to implement PAL decoding, and generates a BT656 video signal.
According to a specific implementation manner of the embodiment of the present application, an output end of the BT656 decoding module is connected to a deinterace module, where the deinterace module is used for a de-interlacing function of PAL video, so as to implement conversion from interlaced video to progressive video.
According to a specific implementation manner of the embodiment of the application, the system is further provided with a VPSS module, the VPSS module is connected to the output end of the video acquisition module, and the VPSS module is used for preprocessing an input image, wherein the preprocessing comprises image mosaic resolution, gamma calibration and white balance.
According to a specific implementation manner of the embodiment of the application, the Display interaction module is provided with three output modes, including a Display mode, a Record mode and a Stream mode,
the Display mode is used for selecting the displayed video and the Display arrangement mode;
the Record mode is used for setting compression parameters, packaging modes and storage parameters;
the Stream mode is used for setting the compression parameter, the packaging mode and the streaming media parameter.
According to a specific implementation manner of the embodiment of the application, the compression parameters include a coding manner, a code rate control manner, an output code rate, the number of B frames and the GOP length; the packaging mode comprises ts, mkv and mp4; the storage parameters include selection of storage medium, storage duration, selection of storage medium file system, and formatting operations.
According to a specific implementation manner of the embodiment of the application, each output mode displays the current video source, resolution, original data format, compression code rate, compression mode, IP information, port number and utilization condition of system resources when running.
According to a specific implementation manner of the embodiment of the application, the video processing module includes an encoding module, an encapsulation module and a storage module, the encoding module is used for encoding and compressing the first video data, the encapsulation module is used for encapsulating the compressed first video data, and the storage module is used for caching the video data.
According to a specific implementation manner of the embodiment of the application, the video output module includes a video signal transmission module, a PCIE module, a Uart module and a DP module, where the video signal transmission module is used for transmission of the third video data, the PCIE module is used for connecting a solid state disk SSD of the Nvme interface, the Uart module is used for debugging a whole system, and the DP module is used for displaying video signals.
Advantageous effects
According to the MPSoC-based multi-channel image processing display interaction system, multi-channel image processing display and interaction functions are realized based on the MPSoC chip, the GPU display interaction function and the PL end scaling and splicing function are adopted, and switching of modes such as an output mode, an input source and a display mode can be realized, so that the requirements of real-time display, coding storage and transmission of multi-channel different video input sources in relevant fields such as airborne display are met.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an MPSoC-based multi-path image processing display interaction system according to an embodiment of the present invention;
FIG. 2 is a hardware block diagram of a MPSoC-based multi-path image processing display interaction system according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a display mode of a MPSoC-based multi-path image processing display interactive system according to an embodiment of the invention.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
The embodiment of the application provides a MPSoC-based multi-path image processing display interaction system, which is designed based on an MPSoC chip, and each module in the system is described in detail below with reference to fig. 1 to 3.
Referring to fig. 1, the MPSoC-based multi-path image processing display interactive system specifically includes the following modules: the system comprises a video acquisition module, a video scaling and splicing module, a display interaction module, a video processing module and a video output module.
The input end of the video acquisition module is connected with the video source, the output end of the video acquisition module is connected with the input end of the video scaling and splicing module, and the video acquisition module is used for respectively converting different video sources into a unified video data format by adopting corresponding processing modes to obtain first video data, wherein the universal video data format comprises NV16 or NV12 and the like.
The input end of the video scaling and splicing module is connected with the video acquisition module and is used for scaling and splicing the first video data to obtain second video data, and the second video data is transmitted to the display interaction module for output.
The input end of the display interaction module is connected with the output end of the video scaling and splicing module and is used for receiving and displaying the second video data, and controlling each module connected with the second video data and the total control console used for video acquisition, scaling, splicing, compression, encapsulation, storage and network transmission.
The display interaction module is realized based on the GPU, and because the resolution of the video displayed by the GPU is fixed (1080P is taken as an example), if multiple paths of 1080P or 720 x 576 videos are needed to be spliced and displayed in the same display, the videos are needed to be correspondingly scaled and spliced. As shown in FIG. 3, there are four display modes of 2x1, 2x2, 3x2, and 4x 2. In the different display modes, the resolution of each video filling area is determined, and the video scaling splicing module needs to scale the selected video to the resolution of the target area and splice the selected video into one video according to the display mode.
The input end of the video processing module is respectively connected with the output end of the video acquisition module and the output end of the display interaction module, and is used for receiving the control of the display interaction module, compressing and packaging the first video data according to the compression parameters and the packaging mode configured by the display interaction module, obtaining third video data, and transmitting the third video data to the video output module.
The input end of the video output module is respectively connected with the output end of the video processing module and the output end of the display interaction module, and is used for receiving the control of the display interaction module and outputting third video data according to the output parameters configured by the display interaction module.
In one embodiment, the video acquisition module includes a combination of one or more of a TPG decoding module, a BT1120 decoding module, an HDMI decoding module, a Mipi decoding module, a BT656 decoding module, an SDI decoding module, and a network stream decoding module.
The TPG decoding module is used for decoding the input color bar video signals; the BT1120 decoding module is used for decoding the input BT1120 video signals and separating lines, fields and enabling signals required by the video in the internal transmission process of the FPGA; the HDMI decoding module is used for realizing the analysis of the HDMI video protocol; the Mipi decoding module is used for realizing the analysis of the MIPI video; the BT656 decoding module is used for decoding the input BT656 video signals and separating the row, the field and the enabling signals required by the video in the internal transmission process of the FPGA; the SDI decoding module is used for decoding the input SDI video signal; the network stream decoding module is used for decoding the input network stream video signal.
Furthermore, the BT656 decoding module adopts TW9984 chip to realize PAL decoding, and generates BT656 video signal, the output end of the BT656 decoding module is connected with a Deinter module, and the Deinter module is used for the de-interlacing function of PAL video, and realizes the conversion from interlaced video to progressive video.
Preferably, the system is further provided with a VPSS module, the VPSS module is connected to the output end of the video acquisition module, and the VPSS module is used for preprocessing an input image, wherein the preprocessing comprises image mosaic resolution, gamma calibration and white balance.
In one embodiment, the Display interaction module is provided with three output modes, including a Display mode, a Record mode and a Stream mode, and each mode displays the current video source, resolution, original data format, compression code rate, compression mode, IP information and port number and the utilization condition of system resources when running. The Display mode is used for selecting the displayed video and displaying the arrangement mode. The Record mode is used for setting compression parameters, packaging modes and storage parameters, wherein the compression parameters comprise a coding mode (H264 and H265), a code rate control mode (CBR, VBR and low delay mode), an output code rate, the number of B frames and the GOP length; the packaging modes comprise ts, mkv, mp4 and other common packaging modes; storage parameters include selection of storage medium, storage duration, selection of storage medium file system, formatting operations, and the like. The Stream mode is used for setting compression parameters, a packaging mode and Stream media parameters, the compression parameters and the packaging mode are the same as those of the Record mode, and the Stream media parameters comprise a board card IP, a server IP and a port number.
In one embodiment, the video processing module includes an encoding module, a packaging module, and a storage module, where the encoding module is configured to encode the first video data, the packaging module is configured to package the encoded first video data, and the storage module is configured to cache the video data.
In one embodiment, the video output module includes a video signal transmission module, a PCIE module, a Uart module and a DP module, where the video signal transmission module is used for transmitting third video data, the PCIE module is used for connecting to a solid state disk SSD of the Nvme interface, the Uart module is used for debugging a whole system, and the DP module is used for displaying video signals.
Preferably, the video signal transmission module comprises a network port module and a USB module.
To facilitate an understanding of the MPSoC-based multi-path image processing display interaction system, the hardware architecture is described below with reference to FIG. 2 by way of one embodiment.
The hardware part comprises a PL part and a PS part based on a MPSoC chip, the PL part comprises a BT1120 decoding module, an HDMI decoding module, a Mipi decoding module, a VPSS module, a BT656 decoding module, a Deinterace module, a Scaler scaling module, a DMA module, a VCU module, a USB module of the PS part, a PCIE module, a network port module, a Uart module and a DP module, and the modules at the PL end and the PS end are interconnected through an AXI bus.
The BT1120 decoding module, the HDMI decoding module, the Mipi decoding module, the VPSS module, the BT656 decoding module and the Deinterace module are all used for converting an input video into a universal video data format to obtain first video data. The BT1120 decoding module implements decoding of SDI by GV7704 chip of Semtech company, generating a video signal of BT 1120. The HDMI decoding module is used for realizing the analysis of the HDMI video protocol, and the analyzed video data is cached into a certain block address space of the DDR by the DMA module. The Mipi decoding module is used for realizing the analysis of MIPI video, and the analyzed video data is cached into a certain block address space of the DDR through the VPSS module and the DMA module. The VPSS module is used for processing the basic image output by the Mipi decoding module, and comprises algorithms such as image demosaicing, gamma calibration, white balance and the like. The BT656 decoding module realizes PAL decoding by TW9984 chip of Intersil company, and generates BT656 video signal. The deinterace module is used for the de-interlacing function of the PAL video and converting interlaced video into progressive video.
The Scaler scaling module is used for realizing the scaling function in the video scaling splicing module, and is respectively connected with the BT1120 decoding module, the HDMI decoding module and the Deinterace module, so as to realize the scaling function of the first video data on the link, and the scaling parameters are configured by the PS end through the AXI Lite bus to form the second video data.
The DMA module is used for caching second video data, is connected to the output ends of the Scaler scaling module and the VPSS module, converts video signals into AXI bus signals, transmits the AXI bus signals to the PS end, and interacts with the DDR through an internal bus of the PS end to realize video caching. The DMA module can be configured with a buffer area by the PS side through the axilite bus.
The VCU module is used for encoding and compressing the second video data through the AXI bus to form third video data.
The network port module and the USB module at the PS end are used for realizing the transmission of coded video signals, the DP module is used for displaying the video signals, the PCIE module is used for connecting the SSD of the Nvme interface, and the Uart module is used for debugging the whole system.
In another embodiment, taking 8 paths of videos (2 paths of SDI, 2 paths of PAL, 1 path of TPG, 1 path of network video stream, one path of MIPI, one path of HDMI) as an example, a use method of the MPSoC-based multi-path image processing display interaction system is introduced.
The flow of the MPSoC display interaction system is as follows:
(1) And selecting a Display option on an interface of the Display interaction module, and selecting a certain path of video or a plurality of paths of video from the 8 paths of video sources to output and Display. And the PL terminal of the MPSoC performs scaling and splicing on the corresponding video sources according to the control information of the interactive interface, outputs the spliced video to a display terminal for display, and simultaneously displays information such as the source, resolution, format and the like of the corresponding video.
(2) Selecting a Record option on the interactive interface, wherein MPSoC can collect 8 paths of video, send the collected video to a VCU module of the PL terminal through Frame buffer write for compression coding, and finally encapsulate and store the video in the SD card through the PS terminal.
(3) And selecting a Stream option on the interactive interface, wherein MPSoC can collect 8 paths of video, send the collected video to a VCU module compression coding of a PL terminal through Frame buffer Write (Fb Write), and finally send the video to a client through RTSP after packaging the video by a PS terminal.
In the embodiment of the invention, as the Zynq UltraScale+MPSoC EV compression platform supports various common video input interfaces such as a PAL interface, an SDI interface, an MIPI interface, a network interface and the like, the splicing display, compression coding, storage and network plug flow of the video can be configured through a desktop interaction system displayed by the GPU, and the system has strong operability and interactivity. Therefore, the Zynq UltraScale+MPSoC EV series chip is selected to realize the functions of multi-channel image processing display and interaction, and the GPU display interaction function and the PL end scaling and splicing function are adopted, so that the switching of modes such as an output mode, an input source, a display mode and the like can be realized, and the requirements of real-time display, coding storage, transmission and the like of multi-channel different video input sources in the relevant fields such as airborne display and the like are met.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. The MPSoC-based multi-path image processing display interaction system is characterized in that the system is designed based on an MPSoC chip and comprises:
the video acquisition module is connected with the video sources and is used for converting different video sources into a unified video data format by adopting corresponding processing modes respectively to obtain first video data;
the input end of the video scaling and splicing module is connected with the video acquisition module and is used for scaling and splicing the first video data to obtain second video data;
the input end of the display interaction module is connected with the output end of the video scaling splicing module and is used for displaying the second video data and controlling each module connected with the display interaction module; the display interaction module is realized based on a GPU, and in different display modes, the video scaling splicing module is used for scaling the selected first video data into the resolution of a target display area and splicing the first video data into the second video data according to the display modes; the Display interaction module is provided with three output modes, including a Display mode, a Record mode and a Stream mode, wherein the Display mode is used for selecting a displayed video and a Display arrangement mode, the Record mode is used for setting compression parameters, a packaging mode and storage parameters, and the Stream mode is used for setting the compression parameters, the packaging mode and Stream media parameters;
the input end of the video processing module is respectively connected with the output end of the video acquisition module and the output end of the display interaction module, and is used for compressing and packaging the first video data according to the control of the display interaction module to obtain third video data;
and the input end of the video output module is respectively connected with the output end of the video processing module and the output end of the display interaction module, and is used for outputting the third video data according to the control of the display interaction module.
2. The MPSoC-based multi-path image processing display interaction system of claim 1, wherein the video capture module comprises a combination of one or more of a BT1120 decode module, an HDMI decode module, a Mipi decode module, a BT656 decode module, an SDI decode module, and a network stream decode module,
the BT1120 decoding module is used for decoding the input BT1120 video signals and separating lines, fields and enabling signals required by the video in the internal transmission process of the FPGA;
the HDMI decoding module is used for realizing the analysis of HDMI video protocol;
the MIpi decoding module is used for realizing the analysis of MIPI video;
the BT656 decoding module is used for decoding the input BT656 video signals and separating lines, fields and enabling signals required by the video in the internal transmission process of the FPGA;
the SDI decoding module is used for decoding an input SDI video signal;
the network stream decoding module is used for decoding the input network stream video signal.
3. The MPSoC-based multi-path image processing display interaction system of claim 2, wherein the BT656 decoding module employs a TW9984 chip to implement PAL decoding to generate the BT656 video signal.
4. The MPSoC-based multi-path image processing display interactive system of claim 3, wherein the output end of the BT656 decoding module is connected with a deinterace module, and the deinterace module is used for the de-interlacing function of PAL video to convert interlaced video into progressive video.
5. The MPSoC-based multi-path image processing display interactive system of claim 1, further comprising a VPSS module connected to the output of the video acquisition module, wherein the VPSS module is configured to pre-process the input image, and wherein the pre-processing comprises image mosaic resolution, gamma calibration and white balance.
6. The MPSoC-based multi-path image processing display interactive system of claim 1, wherein the compression parameters comprise coding mode, rate control mode, output rate, B-frame number and GOP length; the packaging mode comprises ts, mkv and mp4; the storage parameters include selection of storage medium, storage duration, selection of storage medium file system, and formatting operations.
7. The MPSoC-based multi-path image processing display interactive system of claim 1, wherein each of said output modes is operable to display a current video source, resolution, original data format, compression rate, compression mode, IP information, port number and utilization of system resources.
8. The MPSoC-based multi-path image processing display interactive system of claim 1, wherein the video processing module comprises an encoding module, a packaging module and a storage module, the encoding module is configured to encode and compress the first video data, the packaging module is configured to package the compressed first video data, and the storage module is configured to buffer the video data.
9. The MPSoC-based multi-path image processing display interaction system of claim 1, wherein the video output module comprises a video signal transmission module, a PCIE module, a Uart module and a DP module, the video signal transmission module is used for transmitting the third video data, the PCIE module is used for connecting with a solid state disk SSD of the Nvme interface, the Uart module is used for debugging a whole system, and the DP module is used for displaying video signals.
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| CN112367537A (en) * | 2020-11-02 | 2021-02-12 | 上海无线电设备研究所 | Video acquisition-splicing-display system based on ZYNQ |
| CN214014396U (en) * | 2020-12-25 | 2021-08-20 | 北京中科戎大科技股份有限公司 | Multi-channel video image processing device |
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