CN115988155B - Spliced display method and display system - Google Patents
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Abstract
The embodiment of the application relates to the technical field of video processing, and discloses a spliced display method and a display system, wherein the method comprises the following steps: after the multipath video signals are input to the video coding access terminal, controlling the video coding access terminal to perform compression coding on the multipath video signals and encapsulating the multipath video signals into Ethernet data packets; the Ethernet data packet is sent to the Ethernet chip, and the Ethernet chip is controlled to convert the Ethernet data packet into a Serdes signal; controlling the Serdes signal to enter the optical module so as to enable the Serdes signal to be sent to the optical fiber exchange host; the communication data output by the optical fiber exchange host is sent to any video decoding splicing terminal; controlling a video decoding splicing terminal to extract communication data so as to obtain a plurality of paths of target video signals; and outputting the multipath target video signals to a video interface after video processing according to the configuration parameters of the spliced display. By implementing the application, the coding and decoding delay can be effectively reduced, and the transmission of the video signal low-delay networking can be realized.
Description
Technical Field
The application relates to the technical field of video processing, in particular to a spliced display method and a display system.
Background
At present, the encoding and decoding scheme of H.264/H.265 and the transmission mode of the standard Ethernet are mostly adopted in the market to realize large-screen splicing, and the technology has the advantages of high compression ratio, small occupied bandwidth and flexible large-scale networking, but in practice, the technology has the defects of long delay and low image quality.
While other lossless compression schemes adopted in the industry need to occupy extremely high bandwidth, if not compressed, 1 way 1080P60 video transmission needs transmission rate above 3Gbps, and 1 way 4K30 video needs transmission rate of 6 Gbps. The method is mostly limited by transmission bandwidth and networking scale, and general FPGA lossless video transmission can only realize the seat function, so that the method cannot be applied to large-screen display splicing of multi-path videos.
Disclosure of Invention
The embodiment of the application discloses a splicing display method and a display system, which can effectively reduce coding and decoding delay and realize the transmission of video signal low-delay networking.
The first aspect of the embodiment of the application discloses a tiled display method, which comprises the following steps:
after the multipath video signals are input to a video coding access terminal, controlling the video coding access terminal to perform compression coding on the multipath video signals and encapsulating the multipath video signals into Ethernet data packets;
the Ethernet data packet is sent to an Ethernet chip, and the Ethernet chip is controlled to convert the Ethernet data packet into a Serdes signal;
controlling the Serdes signal to enter an optical module so as to enable the Serdes signal to be sent to an optical fiber exchange host;
the communication data output by the optical fiber exchange host is sent to any video decoding splicing terminal;
controlling the video decoding splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals;
and controlling the video decoding splicing terminal to perform video processing on the multipath target video signals according to the configuration parameters of the splicing display, and outputting the processed target video data to a video interface.
As another optional implementation manner, in the first aspect of the embodiment of the present application, after the multiple video signals are input to the video coding access terminal, the operation of controlling the video coding access terminal to perform compression coding on the multiple video signals and encapsulate the multiple video signals into ethernet packets includes:
inputting the multiple paths of video signals to a video encoder so as to convert the multiple paths of video signals into RGB digital signals;
storing the RGB digital signals into a first storage space;
after receiving a video coding control instruction, reading out the RGB digital signals from the first storage space;
and performing compression coding encapsulation on the RGB digital signals by adopting a run-length coding mode to obtain the Ethernet data packet.
As another optional implementation manner, in the first aspect of the embodiment of the present application, the sending the ethernet packet to an ethernet chip and controlling the ethernet chip to convert the ethernet packet into a Serdes signal include:
and sending the Ethernet data packet to the Ethernet chip in the RGMII protocol format, so that the Ethernet chip converts the Ethernet data packet into the Serdes signal.
As another optional implementation manner, in the first aspect of the embodiment of the present application, the controlling the video decoding splicing terminal to perform an extraction operation on the communication data to obtain a multi-path target video signal includes:
after the video decoding splicing terminal receives the communication data, decoding the communication data to extract an initial video signal and a control signal; wherein the control signal comprises the configuration parameters;
decoding the initial video signal in a run-length decoding mode to obtain the multipath target video signal;
storing the multipath target video signals into a second storage space;
and after receiving control instructions of display time sequence and scaling process, reading the multipath target video signals from the second storage space.
In another optional implementation manner, in a first aspect of the embodiment of the present application, the controlling, according to a configuration parameter of the tiled display, the video decoding and stitching terminal to perform video processing on the multiple paths of target video signals, and outputting the processed target video data to a video interface includes:
clipping and scaling the multipath target video signals;
performing layer superposition and OSD superposition processing on the multi-path target video signals subjected to clipping and scaling processing according to the configuration parameters so as to obtain the target video data;
and sending the target video data to a DVI interface driving module to be output to a DVI decoder chip for display output.
As another optional implementation manner, in the first aspect of the embodiment of the present application, the method further includes:
the video coding access terminals realize the transmission synchronization of data in a mode of synchronizing signals connected in series;
and the display synchronization of the pictures is realized by a mode that the synchronous signals are connected in series among the video decoding splicing terminals.
In another optional implementation manner, in the first aspect of the embodiment of the present application, the sending the communication data output by the optical fiber switching host to any video decoding splicing terminal includes:
acquiring the configuration parameters sent by user configuration software;
transmitting the configuration parameters to the optical fiber switching host;
and after the optical fiber exchange host integrates the configuration parameters and the Serdes signals into the communication data, the communication data is sent to any video decoding splicing terminal.
A second aspect of an embodiment of the present application discloses a display system, including:
the first control unit is used for controlling the video coding access terminal to perform compression coding on the multiple paths of video signals and packaging the multiple paths of video signals into an Ethernet data packet after the multiple paths of video signals are input to the video coding access terminal;
the sending and controlling unit is used for sending the Ethernet data packet to an Ethernet chip and controlling the Ethernet chip to convert the Ethernet data packet into a Serdes signal;
the second control unit is used for controlling the Serdes signal to enter the optical module so as to enable the Serdes signal to be sent to the optical fiber exchange host;
the sending unit is used for sending the communication data output by the optical fiber exchange host to any video decoding splicing terminal;
the third control unit is used for controlling the video decoding splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals;
and the fourth control unit is used for controlling the video decoding splicing terminal to carry out video processing on the multipath target video signals according to the configuration parameters of the splicing display, and outputting the processed target video data to a video interface.
As another optional implementation manner, in a second aspect of the embodiment of the present application, the first control unit includes:
an input subunit, configured to input the multiple video signals to a video encoder, so that the multiple video signals are converted into RGB digital signals;
a first storage subunit, configured to store the RGB digital signals into a first storage space;
a first reading subunit, configured to read the RGB digital signals from the first storage space after receiving a video encoding control instruction;
and the encoding subunit is used for carrying out compression encoding encapsulation on the RGB digital signals in a run-length encoding mode so as to obtain the Ethernet data packet.
A third aspect of an embodiment of the present application discloses a display system, including:
a memory storing executable program code;
a processor coupled to the memory;
the processor invokes the executable program code stored in the memory to execute the tiled display method disclosed in the first aspect of the embodiment of the present application.
A fourth aspect of the embodiment of the present application discloses a computer-readable storage medium storing a computer program, where the computer program causes a computer to execute a tiled display method disclosed in the first aspect of the embodiment of the present application.
A fifth aspect of the embodiments of the present application discloses a computer program product which, when run on a computer, causes the computer to perform part or all of the steps of any one of the tiled display methods of the first aspect.
A sixth aspect of the embodiments of the present application discloses an application publishing platform for publishing a computer program product, wherein the computer program product, when run on a computer, causes the computer to perform part or all of the steps of any one of the tiled display methods of the first aspect.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
in the embodiment of the application, after a plurality of paths of video signals are input to a video coding access terminal, the video coding access terminal is controlled to perform compression coding on the plurality of paths of video signals and package the video signals into an Ethernet data packet; the Ethernet data packet is sent to an Ethernet chip, and the Ethernet chip is controlled to convert the Ethernet data packet into a Serdes signal; controlling the Serdes signal to enter an optical module so as to enable the Serdes signal to be sent to an optical fiber exchange host; the communication data output by the optical fiber exchange host is sent to any video decoding splicing terminal; controlling the video decoding splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals; and controlling the video decoding splicing terminal to perform video processing on the multipath target video signals according to the configuration parameters of the splicing display, and outputting the processed target video data to a video interface. Therefore, the embodiment of the application can effectively reduce the encoding and decoding delay and realize the transmission of the video signal low-delay networking.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a tiled display method according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of another exemplary embodiment of a tiled display method;
FIG. 3 is a schematic diagram of a display system according to an embodiment of the present application;
FIG. 4 is a schematic diagram of another display system according to an embodiment of the present application;
FIG. 5 is a schematic diagram of another display system according to an embodiment of the present application;
FIG. 6 is a schematic diagram of the overall structure of a display system according to an embodiment of the present application;
fig. 7 is an internal block diagram of a video coding access terminal according to an embodiment of the present application;
FIG. 8 is a diagram illustrating an internal architecture of a fiber optic switching host according to an embodiment of the present application;
fig. 9 is an internal structural diagram of a video decoding splicing terminal according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that the terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the application discloses a splicing display method and a display system, which can effectively reduce coding and decoding delay and realize the transmission of video signal low-delay networking.
The following detailed description refers to the accompanying drawings.
Example 1
Referring to fig. 1, fig. 1 is a schematic flow chart of a tiled display method according to an embodiment of the application. As shown in fig. 1, the tiled display method may include the following steps.
101. After the multiple video signals are input to the video coding access terminal, the display system controls the operation of the video coding access terminal to compress and encode the multiple video signals and encapsulate the multiple video signals into Ethernet data packets.
As an alternative implementation manner, in an embodiment of the present application, please refer to fig. 6, fig. 6 is a schematic diagram of a general scheme of a display system according to the present application, which is composed of a video encoding access terminal, an optical fiber exchange host, and a video decoding splice terminal. The figure comprises 8 video coding access terminals, 1 optical fiber exchange host, 2 video decoding splicing terminals, and the number of the devices can be increased or decreased according to the needs when an actual system is built.
As an alternative implementation manner, in an embodiment of the present application, after the multiple video signals are input to the video coding access terminal, the video coding access terminal may perform compression coding on the multiple video signals, encapsulate the multiple video signals into ethernet data packets (non-IP data format that complies with ethernet protocol), send the ethernet packets into the optical module after converting the ethernet packets into the Serdes signals, and then send the signals to the optical fiber exchange host.
102. The display system sends the Ethernet data packet to the Ethernet chip and controls the Ethernet chip to convert the Ethernet data packet into a Serdes signal.
103. The display system controls the Serdes signal to enter the optical module so that the Serdes signal is sent to the optical fiber switching host.
104. And the display system sends the communication data output by the optical fiber exchange host to any video decoding splicing terminal.
In an embodiment of the present application, the optical fiber switching host may be used to perform data interleaving and control on serdes links, and then the system may send the communication data output by the optical fiber switching host to any video decoding splicing terminal, so as to finally implement multi-terminal networking.
105. And the display system controls the video decoding splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals.
106. And the display system controls the video decoding splicing terminal to carry out video processing on the multipath target video signals according to the configuration parameters of the splicing display, and outputs the processed target video data to the video interface.
In an embodiment of the present application, the configuration parameters of the splice display may be sent by the user configuration software to the optical fiber switching host and then sent to the video encoding access terminal and the video decoding splice terminal.
As an alternative implementation manner, in an embodiment of the present application, after receiving communication data from the optical fiber switching host, the video decoding splice terminal may extract and recover video signals from the communication data, where each path of 1Gbps signal includes 1 path of video signal. Then, operations such as clipping, scaling, layer overlapping, subtitle overlapping and the like can be performed on up to 8 paths of video signals according to configuration parameters of the spliced display, and finally the video signals are output to a DVI video interface.
As an optional implementation manner, in the embodiment of the application, a display system can be provided with a plurality of video coding access terminals, an optical fiber exchange host and a video decoding splicing terminal, so that the splicing display of the ultra-large screen is realized.
In the embodiment of the application, the data transmission synchronization can be realized by the mode of synchronizing signals connected in series among the video coding access terminals, and the display synchronization of the pictures can be realized by the mode of synchronizing signals connected in series among the video decoding splicing terminals, so that the synchronous output of the display pictures of all the spliced screens can be ensured finally.
In the tiled display method of fig. 1, a display system is described as an example of an execution subject. It should be noted that, the execution subject of the tiled display method of fig. 1 may also be a stand-alone device associated with the display system, which is not limited by the embodiments of the present application.
Therefore, implementing the display method of fig. 1 can effectively reduce the delay of encoding and decoding, and realize the transmission of video signal low-delay networking.
In addition, implementing a tiled display method as described in fig. 1 can ensure synchronous output of the display pictures of each tiled screen finally.
Example two
Referring to fig. 2, fig. 2 is a flow chart of another embodiment of a tiled display method according to the present application. As shown in fig. 2, the tiled display method may include the steps of:
201. the display system inputs the multiple video signals to the video encoder to convert the multiple video signals into RGB digital signals.
202. The display system stores the RGB digital signals into the first storage space.
203. After receiving the video coding control instruction, the display system reads out the RGB digital signals from the first storage space.
204. The display system adopts a run-length coding mode to carry out compression coding encapsulation on the RGB digital signals so as to obtain an Ethernet data packet.
205. The display system sends the Ethernet data packet to the Ethernet chip in the RGMII protocol format, so that the Ethernet chip converts the Ethernet data packet into a Serdes signal.
As an alternative implementation manner, in the embodiment of the present application, please refer to fig. 7, fig. 7 is an internal structure diagram of a video coding access terminal disclosed in the embodiment of the present application, as shown in the figure, an FPGA chip of the video coding access terminal is an FPGA chip of the INTEL company cycloev series, and 2 DDR slices are connected to the external part of the FPGA chip as a buffer space for video frame data. The HDMI video encoder may implement conversion of a video signal of 4K30 into an RGB digital signal.
As an alternative implementation manner, in the embodiment of the present application, the system may write the RGB digital signals that pass through the line buffer and the DDR controller into the external DDR temporary storage, and then may read out the video signals according to the video encoding control command, and perform video compression encoding. The video compression coding in the application adopts run length coding (also called run length coding), and the common computer desktop signal can be compressed to more than 6 times through the run length coding, namely, the 4K30 signal which originally needs 6Gbps bandwidth to be transmitted can be transmitted only by 1Gbps through the run length coding. The compressed and encoded data is sent to the Ethernet PHY chip for transmission in the format of RGMII protocol. And the Ethernet PHY chip converts RGMII data into a serdes signal and finally transmits the serdes signal through the optical module.
206. The display system controls the Serdes signal to enter the optical module so that the Serdes signal is sent to the optical fiber switching host.
207. The display system acquires configuration parameters sent by user configuration software.
208. The display system sends the configuration parameters to the optical fiber switching host.
209. After the optical fiber switching host integrates the configuration parameters and the Serdes signals into communication data, the display system sends the communication data to any video decoding splicing terminal.
As an optional implementation manner, in the embodiment of the present application, referring to fig. 8, fig. 8 is an internal structure diagram of an optical fiber switching host disclosed in the embodiment of the present application, as shown in the drawing, the optical fiber switching host may use multiple FPGAs as a data switching chip, where one back panel FPGA implements backbone data switching; the multi-chip interface board FPGA realizes interface branch data exchange; in addition, a piece of CycloneV chip of the main control board is used as the main control chip of the optical fiber exchange host.
As an optional implementation manner, in the embodiment of the present application, the functions mainly implemented by the optical fiber switching host in the present application include rate configuration of optical fiber channels, signal routing of each channel, and interface status monitoring. The highest speed of the high-speed transceiver of the back plate and the interface board FPGA exceeds 12Gbps, the scheme uses a 1Gbps speed standard at the interface, and the data exchange between the back plate and the interface board uses a 10Gbps speed standard. And the SOC system of the main control board is used as a configuration CPU and is connected with a user configuration computer through a standard Ethernet. The visual interface configuration software installed on the configuration computer is used for controlling the large screen display and signal allocation, the control signals are sent to the optical fiber exchange host through the Ethernet, and the SOC of the optical fiber exchange host sends configuration information to each FPGA chip to perform data exchange configuration of the optical fiber Serdes channels.
210. After the video decoding splicing terminal receives the communication data, the display system decodes the communication data to extract an initial video signal and a control signal; wherein, the control signal comprises configuration parameters.
211. The display system decodes the initial video signal in a run-length decoding manner to obtain multiple target video signals.
212. The display system stores the multiple target video signals in the second storage space.
213. After receiving control instructions of display time sequence and zooming process, the display system reads out multiple paths of target video signals from the second storage space.
214. The display system performs clipping and scaling on the multiple target video signals.
215. And the display system performs layer superposition and OSD superposition processing on the multi-path target video signals subjected to clipping and scaling processing according to the configuration parameters so as to obtain target video data.
216. And the display system sends the target video data to the DVI interface driving module to be output to the DVI decoder chip for display output.
As an alternative implementation manner, in an embodiment of the present application, referring to fig. 9, fig. 9 is an internal structure diagram of a video decoding splicing terminal disclosed in the embodiment of the present application, as shown in the drawing, the video decoding splicing terminal may use an FPGA of Xilinx company as a video data processing chip, and may use 41 Gbit DDR as a video frame data buffer space and a DVI decoder as a video decoding chip.
As an optional implementation manner, in the embodiment of the present application, when each optical module signal enters an IP core 1G/2.5G Ethernet PCS/PMA orSGMII (IP core from which serdes of XILINX FPGA is converted into RGMII) of the FPGA, the video decoding and splicing terminal receives data sent by the optical fiber exchange host through the optical fiber channel, and then the system may control the video decoding and splicing terminal to decode the data, and extract the video signal and the control signal. The control signals are used to configure display parameters such as display resolution, layer size, display coordinates, OSD superimposition parameters, etc. The video signal is required to be run-length decoded (i.e. reverse decoded of run-length encoding) to obtain real video data, and the real video data is stored in the DDR through the line buffer and the DDR controller. The system can read out the video content to be cut, scaled and displayed from the DDR controller according to the display time sequence and the scaling process control, cut and scale, then the system can combine the processed video data signals to carry out graph stacking and OSD stacking according to the control parameters, finally the video RGB data can be sent to the DVI interface driving module, and finally the video RGB data is output to the DVI decoder chip for display output.
As an optional implementation manner, in the embodiment of the application, an FPGA chip can be used as a carrier for video encoding, decoding and transmission, the video transmission bandwidth utilization rate is improved by using run-length encoding, 1 path of 4K30 video or 1 path of 1080P60 video can be transmitted by using 1Gbps bandwidth, the characteristics of low delay and flexible programming of the FPGA chip are fully utilized, and low-delay networking transmission of video signals and large-screen splicing with high image quality, flexible configuration and high confidentiality are realized.
Therefore, implementing another splicing display method described in fig. 2 can effectively reduce the encoding and decoding delay, and realize the transmission of video signal low-delay networking.
In addition, by implementing another tiled display method described in fig. 2, confusion of the tiled pattern due to delay of video transmission can be avoided.
Example III
Referring to fig. 3, fig. 3 is a schematic structural diagram of a display system according to an embodiment of the application. As shown in fig. 3, the display system 300 may include a first control unit 301, a transmitting and controlling unit 302, a second control unit 303, a transmitting unit 304, a third control unit 305, and a fourth control unit 306, wherein:
the first control unit 301 is configured to control an operation of the video coding access terminal to compression-encode the multiple video signals and encapsulate the multiple video signals into ethernet packets after the multiple video signals are input to the video coding access terminal.
The sending and controlling unit 302 is configured to send the ethernet packet to the ethernet chip, and control the ethernet chip to convert the ethernet packet into a Serdes signal.
The second control unit 303 is configured to control the Serdes signal to enter the optical module, so that the Serdes signal is sent to the optical fiber switching host.
And the sending unit 304 is configured to send the communication data output by the optical fiber switching host to any video decoding splicing terminal.
And the third control unit 305 is configured to control the video decoding splicing terminal to perform an extraction operation on the communication data, so as to obtain a multi-path target video signal.
And the fourth control unit 306 is configured to control the video decoding splicing terminal to perform video processing on the multiple paths of target video signals according to the configuration parameters of the splicing display, and output the processed target video data to the video interface.
As can be seen, implementing the display system depicted in fig. 3,
in addition, implementing the display system depicted in FIG. 3,
example IV
Referring to fig. 4, fig. 4 is a schematic structural diagram of another display system according to an embodiment of the application. Wherein the display system of fig. 4 is optimized from the display system of fig. 3. In comparison with the display system of fig. 3, the first control unit 301 of fig. 4 includes:
an input subunit 3011 is configured to input the multiple video signals to a video encoder, so as to convert the multiple video signals into RGB digital signals.
A first storage subunit 3012, configured to store RGB digital signals into the first storage space.
The first reading subunit 3013 is configured to read the RGB digital signals from the first storage space after receiving the video encoding control instruction.
And the encoding subunit 3014 is configured to perform compression encoding encapsulation on the RGB digital signal by using a run-length encoding manner, so as to obtain an ethernet packet.
In comparison to the display system of fig. 3, the transmission and control unit 302 of fig. 4 includes:
the first transmitting subunit 3021 is configured to transmit the ethernet packet to the ethernet chip in the format of the RGMII protocol, so that the ethernet chip converts the ethernet packet into a Serdes signal.
In comparison with the display system of fig. 3, the third control unit 305 of fig. 4 includes:
the decoding subunit 3051 is configured to decode the communication data after the video decoding splicing terminal receives the communication data, so as to extract an initial video signal and a control signal; wherein, the control signal comprises configuration parameters.
As an alternative implementation, in the embodiment of the present application, the decoding subunit 3051 is further configured to decode the initial video signal by using a run-length decoding manner, so as to obtain multiple target video signals.
A second storage subunit 3052, configured to store the multiple target video signals into the second storage space.
The second reading subunit 3053 is configured to read the multi-path target video signal from the second storage space after receiving the control instruction of the display timing and the scaling process.
In comparison with the display system of fig. 3, the fourth control unit 306 of fig. 4 includes:
the processing subunit 3061 is configured to perform clipping and scaling processing on the multiple target video signals.
As an optional implementation manner, in an embodiment of the present application, the processing subunit 3061 is further configured to perform, according to the configuration parameter, processing of layer superimposition and OSD superimposition on the multiple paths of target video signals subjected to clipping and scaling processing, so as to obtain target video data.
The second transmitting subunit 3062 is configured to transmit the target video data to the DVI interface driver module, so as to output the target video data to the DVI decoder chip for display output.
In comparison with the display system of fig. 3, the transmission unit 304 of fig. 4 includes:
an obtaining subunit 3041, configured to obtain the configuration parameters sent by the user configuration software.
A third transmitting subunit 3042, configured to transmit the configuration parameters to the optical fiber switching host.
And a fourth transmitting subunit 3043, configured to transmit the communication data to any video decoding splicing terminal after the optical fiber switching host assembles the configuration parameters and the Serdes signals into the communication data.
It will be seen that implementing another display system as described in fig. 4 is capable of supporting a plurality of different rates of switching modes.
In addition, the implementation of the alternative display system described in fig. 4 can effectively solve the problem that the exchange scale is difficult to expand.
Example five
Referring to fig. 7, fig. 7 is a schematic structural diagram of another display system according to an embodiment of the application. As shown in fig. 7, the display system may include:
a memory 501 in which executable program codes are stored;
a processor 502 coupled to the memory 501;
the processor 502 invokes executable program codes stored in the memory 501 to execute any one of the tiled display methods of fig. 1-2.
The embodiment of the application discloses a computer readable storage medium which stores a computer program, wherein the computer program enables a computer to execute any one of the spliced display methods shown in fig. 1-2.
The embodiments of the present application also disclose a computer program product, wherein the computer program product, when run on a computer, causes the computer to perform some or all of the steps of the method as in the method embodiments above.
Those of ordinary skill in the art will appreciate that all or part of the steps of the various methods of the above embodiments may be implemented by hardware associated with a program that may be stored in a computer-readable storage medium, including Read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), programmable Read-Only Memory (Programmable Read-Only Memory, PROM), erasable programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), one-time programmable Read-Only Memory (OTPROM), electrically erasable programmable Read-Only Memory (EEPROM), compact disc Read-Only Memory (Compact Disc Read-Only Memory, CD-ROM), or other optical disk Memory, magnetic disk Memory, tape Memory, or any other medium that can be used to carry or store data that is readable by a computer.
The above describes in detail a display method and a display system for splicing disclosed in the embodiments of the present application, and specific examples are applied to describe the principles and embodiments of the present application, where the description of the above embodiments is only for helping to understand the method and core ideas of the present application; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the idea of the present application, the present disclosure should not be construed as limiting the present application in summary.
Claims (10)
1. A tiled display method, comprising:
after the multipath video signals are input to a video coding access terminal, controlling the video coding access terminal to perform compression coding on the multipath video signals and encapsulating the multipath video signals into Ethernet data packets;
the Ethernet data packet is sent to an Ethernet chip, and the Ethernet chip is controlled to convert the Ethernet data packet into a Serdes signal;
controlling the Serdes signal to enter an optical module so as to enable the Serdes signal to be sent to an optical fiber exchange host;
the communication data output by the optical fiber exchange host is sent to any video decoding splicing terminal;
controlling the video decoding splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals;
and controlling the video decoding splicing terminal to perform video processing on the multipath target video signals according to the configuration parameters of the splicing display, and outputting the processed target video data to a video interface.
2. The method of claim 1, wherein said controlling the video coding access terminal to compression encode and encapsulate the multiplexed video signal into ethernet packets after the multiplexed video signal is input to the video coding access terminal comprises:
inputting the multiple paths of video signals to a video encoder so as to convert the multiple paths of video signals into RGB digital signals;
storing the RGB digital signals into a first storage space;
after receiving a video coding control instruction, reading out the RGB digital signals from the first storage space;
and performing compression coding encapsulation on the RGB digital signals by adopting a run-length coding mode to obtain the Ethernet data packet.
3. The method of claim 2, wherein said sending the ethernet packet into an ethernet chip and controlling the ethernet chip to convert the ethernet packet into a Serdes signal comprises:
and sending the Ethernet data packet to the Ethernet chip in the RGMII protocol format, so that the Ethernet chip converts the Ethernet data packet into the Serdes signal.
4. The method of claim 3, wherein said controlling the video decoding splice terminal to extract the communication data to obtain a multi-path target video signal comprises:
after the video decoding splicing terminal receives the communication data, decoding the communication data to extract an initial video signal and a control signal; wherein the control signal comprises the configuration parameters;
decoding the initial video signal in a run-length decoding mode to obtain the multipath target video signal;
storing the multipath target video signals into a second storage space;
and after receiving control instructions of display time sequence and scaling process, reading the multipath target video signals from the second storage space.
5. The method according to claim 4, wherein controlling the video decoding splicing terminal to perform video processing on the multiple paths of target video signals according to the configuration parameters of the splicing display, and outputting the processed target video data to a video interface, includes:
clipping and scaling the multipath target video signals;
performing layer superposition and OSD superposition processing on the multi-path target video signals subjected to clipping and scaling processing according to the configuration parameters so as to obtain the target video data;
and sending the target video data to a DVI interface driving module to be output to a DVI decoder chip for display output.
6. The method according to any one of claims 1-5, further comprising:
the video coding access terminals realize the transmission synchronization of data in a mode of synchronizing signals connected in series;
and the display synchronization of the pictures is realized by a mode that the synchronous signals are connected in series among the video decoding splicing terminals.
7. The method of claim 1, wherein the sending the communication data output by the optical fiber switching host to any video decoding splice terminal comprises:
acquiring the configuration parameters sent by user configuration software;
transmitting the configuration parameters to the optical fiber switching host;
and after the optical fiber exchange host integrates the configuration parameters and the Serdes signals into the communication data, the communication data is sent to any video decoding splicing terminal.
8. A display system, the display system comprising:
the first control unit is used for controlling the video coding access terminal to perform compression coding on the multiple paths of video signals and packaging the multiple paths of video signals into an Ethernet data packet after the multiple paths of video signals are input to the video coding access terminal;
the sending and controlling unit is used for sending the Ethernet data packet to an Ethernet chip and controlling the Ethernet chip to convert the Ethernet data packet into a Serdes signal;
the second control unit is used for controlling the Serdes signal to enter the optical module so as to enable the Serdes signal to be sent to the optical fiber exchange host;
the sending unit is used for sending the communication data output by the optical fiber exchange host to any video decoding splicing terminal;
the third control unit is used for controlling the video decoding splicing terminal to extract the communication data so as to obtain a plurality of paths of target video signals;
and the fourth control unit is used for controlling the video decoding splicing terminal to carry out video processing on the multipath target video signals according to the configuration parameters of the splicing display, and outputting the processed target video data to a video interface.
9. The display system according to claim 8, wherein the first control unit includes:
an input subunit, configured to input the multiple video signals to a video encoder, so that the multiple video signals are converted into RGB digital signals;
a first storage subunit, configured to store the RGB digital signals into a first storage space;
a first reading subunit, configured to read the RGB digital signals from the first storage space after receiving a video encoding control instruction;
and the encoding subunit is used for carrying out compression encoding encapsulation on the RGB digital signals in a run-length encoding mode so as to obtain the Ethernet data packet.
10. A display system, the display system comprising:
a memory storing executable program code;
a processor coupled to the memory;
the processor invokes the executable program code stored in the memory to perform the tiled display method of any of claims 1-7.
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| CN111010616A (en) * | 2019-12-23 | 2020-04-14 | 威创集团股份有限公司 | Audio and video transmission method and system based on IP network |
| CN112019863A (en) * | 2020-09-04 | 2020-12-01 | 威创集团股份有限公司 | Control system for video display |
| CN217445454U (en) * | 2021-12-24 | 2022-09-16 | 广州市保伦电子有限公司 | Recording and broadcasting KVM (keyboard video mouse) seat system with optical network hot standby function |
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| CN111010616A (en) * | 2019-12-23 | 2020-04-14 | 威创集团股份有限公司 | Audio and video transmission method and system based on IP network |
| CN112019863A (en) * | 2020-09-04 | 2020-12-01 | 威创集团股份有限公司 | Control system for video display |
| CN217445454U (en) * | 2021-12-24 | 2022-09-16 | 广州市保伦电子有限公司 | Recording and broadcasting KVM (keyboard video mouse) seat system with optical network hot standby function |
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