CN112019863A - Control system for video display - Google Patents
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- CN112019863A CN112019863A CN202010920856.6A CN202010920856A CN112019863A CN 112019863 A CN112019863 A CN 112019863A CN 202010920856 A CN202010920856 A CN 202010920856A CN 112019863 A CN112019863 A CN 112019863A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformations in the plane of the image
- G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
- G06T3/4038—Image mosaicing, e.g. composing plane images from plane sub-images
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
- H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
- H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394
- H04N21/43635—HDMI
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Abstract
The application discloses a control system for video display, the system comprising: the system comprises a network switching module, an IP decoder, an LED screen driving module, an HDMI receiver and an FPGA module; the network switching module is used for receiving the 4K signal to be displayed and sending the 4K signal to be displayed to the IP decoder; the IP decoder is used for decoding the 4K signal to be displayed into an HDMI video signal and sending the HDMI video signal to the HDMI receiver; the HDMI receiver is used for decoding the HDMI video signals into RGB video signals and sending the RGB video signals to the FPGA module; the FPGA module is used for grouping the RGB video signals according to the configuration of the switching chip in the LED screen driving module to obtain a plurality of paths of output signals; the LED screen driving module is used for outputting a plurality of output signals to the display equipment based on the configuration of the exchange chip, and the technical problem that the splicing display of 4K signals is difficult to realize in the existing video display control system is solved.
Description
Technical Field
The present application relates to the field of video processing technologies, and in particular, to a control system for video display.
Background
With the continuous development of the video industry technology and the maturity of the IP encoding and decoding technology, the cost of the low-latency encoding and decoding technology is gradually reduced, and the IP encoding and decoding technology is widely applied to the related field of video processing.
In the prior art, an IP decoder and an LED screen driving module form a video display control system, however, the IP decoder in the control system does not have a function of driving a high definition LED screen, and the LED screen driving module does not have an IP video input interface and a decoding function, and the number of high definition LED screens that can be driven is small. In this way, if the control system is used to realize the splicing display of the 4K signals, the defects are difficult to realize.
Disclosure of Invention
The application provides a control system for video display, has solved current video display's control system, is difficult to realize the technical problem that the concatenation of 4K signal shows.
In view of the above, the present application provides a control system for video display, comprising: the system comprises a network switching module, an IP decoder, an LED screen driving module, an HDMI receiver and an FPGA module;
the network switching module is used for receiving a 4K signal to be displayed and sending the 4K signal to be displayed to the IP decoder;
the IP decoder is used for decoding the 4K signal to be displayed into an HDMI video signal and sending the HDMI video signal to the HDMI receiver;
the HDMI receiver is used for decoding the HDMI video signals into RGB video signals and sending the RGB video signals to the FPGA module;
the FPGA module is used for grouping the RGB video signals according to the configuration of a switching chip in the LED screen driving module to obtain a plurality of paths of output signals;
and the LED screen driving module is used for outputting a plurality of output signals to display equipment based on the configuration of the exchange chip.
Alternatively,
the output signal includes: a sub video signal and a signal identifier corresponding to the sub video signal;
the configuration of the switching chip comprises: exchanging the number of chips, the number of channels of signal transmission channels and channel identifications corresponding to the signal transmission channels;
the signal identification corresponds to the channel identification;
the LED screen driving module is specifically configured to send the output signal to the display device based on the number of switching chips, the number of channels, and the channel identifier.
Alternatively,
the number of the output signals is 16;
the number of the switching chips is two, and the number of the signal transmission channels is 16.
Alternatively,
the control system further comprises: the HDMI connector comprises a signal conversion module and an HDMI connector;
the signal conversion module is used for copying the HDMI video signals output by the IP decoder to obtain two paths of HDMI video signals and respectively sending the two paths of HDMI video signals to the HDMI receiver and the HDMI connector;
the HDMI connector is used for displaying back in the display control process of the 4K signal to be displayed.
Alternatively,
the network switching module includes: a network switching chip and an input interface;
the input interface is used for receiving the 4K signal to be displayed;
and the network switching chip is used for sending the 4K signal to be displayed to the IP decoder.
Alternatively,
the input interface includes: an optical module interface and/or an ethernet interface.
Alternatively,
when the input interface includes an ethernet interface, the ethernet interface specifically includes: PoE network interface type interface.
Alternatively,
the power module of the control system includes: the device comprises an AC-DC module and a PoE direct current conversion module;
the AC-DC module is used for converting an external power supply into preset voltage and inputting the preset voltage into the control system;
and the PoE direct current conversion module is used for carrying out power supply handshake negotiation with an external PSE switch, and inputting the preset voltage into the control system after adjusting the power supply separated by the Ethernet interface to the preset voltage.
Alternatively,
the control system further comprises: a USB interface module;
the USB interface module is connected with the IP decoder.
Alternatively,
the control system further comprises: a storage module;
the storage module is connected with the IP decoder.
According to the technical scheme, the embodiment of the application has the following advantages:
the control system for video display in the present application includes: the system comprises a network switching module, an IP decoder, an LED screen driving module, an HDMI receiver and an FPGA module; the network switching module is used for receiving the 4K signal to be displayed and sending the 4K signal to be displayed to the IP decoder; the IP decoder is used for decoding the 4K signal to be displayed into an HDMI video signal and sending the HDMI video signal to the HDMI receiver; the HDMI receiver is used for decoding the HDMI video signals into RGB video signals and sending the RGB video signals to the FPGA module; the FPGA module is used for grouping the RGB video signals according to the configuration of the switching chip in the LED screen driving module to obtain a plurality of paths of output signals; and the LED screen driving module is used for outputting a plurality of output signals to the display equipment based on the configuration of the switching chip.
In the application, after the IP decoder acquires the signals to be displayed 4, firstly, the signals to be displayed 4K are decoded into HDMI video signals, then the HDMI video signals are sent to the HDMI receiver, the HDMI receiver decodes the HDMI video signals into RGB video signals, the RGB video signals are sent to the FPGA module, the FPGA module groups the RGB video signals according to the configuration of a switching chip in the LED screen driving module to obtain a plurality of paths of output signals, finally, the LED screen driving module outputs the output signals to the display equipment based on the configuration of the switching chip, in the whole display process, the IP decoder and the LED screen driving module are used for splicing and displaying the signals to be displayed 4K by means of the HDMI receiver and the FPGA module, and therefore the technical problem that the splicing and displaying of the signals to be displayed 4K are difficult to achieve is solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of an embodiment of a control system for video display according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a network switching module in an embodiment of the present application;
fig. 3 is a schematic structural diagram of an LED screen driving module in an embodiment of the present application;
FIG. 4 is a schematic structural diagram of a USB interface module according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an application example of a control system for video display according to an embodiment of the present application.
Detailed Description
The embodiment of the application provides a control system for video display, and solves the technical problem that the splicing display of 4K signals is difficult to realize in the existing control system for video display.
In order to make the technical solutions of the present application better understood, the technical solutions of the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of a control system for video display according to an embodiment of the present disclosure.
The control system for video display in the embodiment comprises a network switching module 2, an IP decoder 1, an LED screen driving module 7, an HDMI receiver 5 and an FPGA module 6; the network switching module 2 is used for receiving the 4K signal to be displayed and sending the 4K signal to be displayed to the IP decoder 1; the IP decoder 1 is used for decoding the 4K signal to be displayed into an HDMI video signal and sending the HDMI video signal to the HDMI receiver 5; the HDMI receiver 5 is used for decoding the HDMI video signals into RGB video signals and sending the RGB video signals to the FPGA module 6; the FPGA module 6 is used for grouping the RGB video signals according to the configuration of the switching chip in the LED screen driving module 7 to obtain a plurality of paths of output signals; and the LED screen driving module 7 is used for outputting a plurality of output signals to the display equipment based on the configuration of the switching chip.
It can be understood that the IP decoder 1 has the decoding functions of h.264 and h.265. The IP video encoding and decoding processor is provided with an RGMII interface, a USB2.0 interface, a USB3.0 interface, an eMMC4.5 interface, an HDMI2.0 interface and the like. The RGMII interface is used for receiving a 4K signal to be displayed sent by the network switching module 2 and decoding the signal into an HDMI video signal; USB2.0 is used for receiving keyboard and mouse data; USB3.0 for reading and writing external (USB disk) data; the eMMC4.5 interface is used for reading and writing of the large-capacity storage chip; the HDMI2.0 interface is used for outputting HDMI video signals.
In this embodiment, after the IP decoder 1 obtains the to-be-displayed 4-view signal through the network switch module 2, it first decodes the to-be-displayed 4K signal into an HDMI video signal, then, the HDMI video signal is transmitted to the HDMI receiver 5, and after the HDMI receiver 5 decodes the HDMI video signal into RGB video signals, the RGB video signals are sent to an FPGA module 6, the FPGA module 6 groups the RGB video signals according to the configuration of a switching chip in an LED screen driving module 7 to obtain a plurality of output signals, finally, the LED screen driving module 7 outputs the output signals to a display device based on the configuration of the switching chip, in the whole display process, the 4K signals to be displayed are spliced and displayed through the IP decoder 1 and the LED screen driving module 7 by means of the HDMI receiver 5 and the FPGA module 6, therefore, the technical problem that the splicing display of the 4K signal is difficult to realize in the existing video display control system is solved.
The above is a description of a first embodiment of a control system for video display provided in an embodiment of the present application, and the above is a description of an embodiment of a control system for video display provided in an embodiment of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a second embodiment of a control system for video display according to the present disclosure.
The control system for video display in the embodiment comprises a network switching module 2, an IP decoder 1, an LED screen driving module 7, an HDMI receiver 5 and an FPGA module 6; the network switching module 2 is used for receiving the 4K signal to be displayed and sending the 4K signal to be displayed to the IP decoder 1; the IP decoder 1 is used for decoding the 4K signal to be displayed into an HDMI video signal and sending the HDMI video signal to the HDMI receiver 5; the HDMI receiver 5 is used for decoding the HDMI video signals into RGB video signals and sending the RGB video signals to the FPGA module 6; the FPGA module 6 is used for grouping the RGB video signals according to the configuration of the switching chip in the LED screen driving module 7 to obtain a plurality of paths of output signals; and the LED screen driving module 7 is used for outputting a plurality of output signals to the display equipment based on the configuration of the switching chip.
It can be understood that, in order to ensure correct output of the 4K signal, and no picture disorder or the like, the output signals in the embodiment include: a sub video signal and a signal identifier corresponding to the sub video signal; the configuration of the exchange chip comprises: exchanging the number of chips, the number of channels of the signal transmission channels and the channel identification corresponding to each signal transmission channel; the signal identification corresponds to the channel identification; the LED screen driving module 7 is specifically configured to send an output signal to the display device based on the number of switching chips, the number of channels, and the channel identifier.
Specifically, the number of output signals is 16; the number of the switching chips is two, and the number of the signal transmission channels is 16.
Namely, the FPGA module 6 is provided with 8 paths of 12.5Gb/s high-speed transceiver interfaces and is used for sending two groups of QSGMII data to the LED screen driving module 7. Each set QSGMII contains 8 output signals, each corresponding to 960 x 540 image data. The FPGA module 6 divides the received RGB video signals into 16 paths of output signals and sends the output signals to the LED screen driving module 7 through two groups of QSGMII lines.
The specific picture is divided into: a 4K (3840 × 2160) picture is divided into 4 rows × 4 columns, and may be divided into 16 blocks 960 × 540 of pictures, each block 960 × 540 having 518400 pixels. The pictures of the 16 small blocks are sequentially ordered from top to bottom and from left to right into numbers 1-16, and each block is sent corresponding to one signal transmission channel. Therefore, the FPGA module 6 needs to perform VLAN configuration on the network switching chips in the LED panel driving module 7 through the MDIO bus, and the two network switching chips can output 16 output signals at the same time. The configuration content of the network switching chip comprises:
1) the input mode is configured as QSGMII;
2) and dividing 8 groups of VLANs corresponding to the 8 paths of output network ports, and determining a signal transmission channel and a corresponding channel identifier of each group of VLANs.
After configuration is completed, the FPGA module 6 packs the image data of the No. 1-16 pictures, adds a signal identifier and sends the image data to the QSGMII interface.
Further, the control system in this embodiment further includes: the signal conversion module 3 and the HDMI connector 4; the signal conversion module 3 is configured to copy the HDMI video signals output by the IP decoder 1 to obtain two paths of HDMI video signals, and send the two paths of HDMI video signals to the HDMI receiver 5 and the HDMI connector 4, respectively; and the HDMI connector 4 is used for displaying back in the display control process of the 4K signal to be displayed.
It can be understood that the signal conversion module 3 is an HDMI2.0 one-in two-out chip, and can receive one HDMI2.0b signal and send the signal to the next stage after being duplicated into 2 HDMI2.0b signals. The chip is internally provided with an EDID storage space, the EDID reading and writing functions of a receiving end and a sending end are met, and an external storage device is not needed. Use of the chip requires obtaining keys authorized by the HDCP association. In the embodiment, one path of HDMI video signal obtained after copying is output to an HDMI receiver 5, converted into an RGB video signal and enters an FPGA; the other path of the direct output HDMI connector 4 is used for equipment cascade connection and debugging or for back display in the display control process of the 4K signal to be displayed.
As shown in fig. 2, the network switching module 2 in this embodiment includes: a network switching chip 201 and an input interface; the input interface is used for receiving a 4K signal to be displayed; and the network switching chip is used for sending the 4K signal to be displayed to the IP decoder 1.
Specifically, the network switch module 2 is composed of a network switch chip 201, SFP optical module interfaces 202 and 203, and ethernet interfaces 204 and 205. The network switch chip 201 has a 1-way RGMII interface, a 2-way 1Gbps SERDES interface, and a 3-way 10/100/1000BaseT interface, and in this embodiment, the 1-way RGMII interface, the 2-way 1Gbps SERDES interface, and the 2-way 10/100/1000BaseT interface are used. The 4K signal to be displayed can be input to the network switch chip 201 from the SFP optical module interface 202, 203 or the ethernet interface 204, 205, and sent to the IP decoder 1 through the RGMII interface. The ethernet interfaces 204 and 205 are PoE network port type interfaces, and are provided with a network transformer inside, which can separate 48V PoE power supply from network signals, the 48V power supply is output to the PoE dc conversion module 10, and the network signals are input to the network switch chip 201.
Specifically, the power supply module of the control system in this embodiment includes: an AC-DC module 9 and a PoE direct current conversion module 10; the AC-DC module 9 is used for converting an external power supply into preset voltage and inputting the preset voltage into the control system; the PoE dc conversion module 10 is configured to perform power supply handshake negotiation with an external PSE switch, adjust a power supply separated through the ethernet interfaces 204 and 205 to a preset voltage, and input the preset voltage to the control system. Therefore, the PoE direct current conversion module 10 and the AC-DC module 9 form redundant power supply, and any power supply can enable the control system to work normally.
As shown in fig. 3, the LED panel driving module 7 in this embodiment is composed of two network switch chips 701 and 702 with QSGMII interface and 8 gigabit ports, and two 8-way RJ45 network ports 703 and 704. Two sets of 8 kilomega ports are external interfaces and are connected to the input end of the LED display equipment, and the LED display equipment resolves the video content into the adaptive resolution ratio for displaying.
It is to be understood that, as shown in fig. 1 and 4, the control system in the present embodiment further includes: a USB interface module 8; the USB interface module 8 is connected to the IP decoder 1.
Specifically, the USB interface module 8 is composed of a USB HUB chip 801, a mouse USB interface 802, a keyboard USB interface 803, and a USB3.0 interface 804. The mouse USB interface 802 and the keyboard USB interface 803 are used to input a keyboard signal and a mouse signal, respectively, and send data of the keyboard and the mouse to the IP decoder 1 through the HUB chip, and in a typical application (as shown in fig. 5), the keyboard and the mouse are sent to the IP decoder 1 through a network for analysis, so that the IP decoder 1 remotely controls the desktop operation of the PC host. The USB3.0 interface 804 is used for reading the video or picture content of the USB disk, storing the content in the storage module 11, and the processor may decode the stored content video and output the decoded content video through the HDMI interface.
It is understood that the control system in this embodiment further includes: a storage module 11; the memory module 11 is connected to the IP decoder 1.
The storage module 11 may be a 16GByte large-capacity memory chip, which is used for the IP decoder 1 to read and write large-capacity data, and may also be used as a storage space for a processor boot program (firmware). The interface of the processor is an eMMC4.5 parallel data interface, the highest writing speed reaches 150MByte/s, and the reading speed reaches 300 MByte/s.
It can be understood from fig. 5 that, the control system in this embodiment may obtain data in the video coding node, the video conference server, and the IP camera through the switch and the PSE switch, and after coding is completed in the control system, the data may be input into the LED tiled display wall and the HDMI display device for display. The control system integrates an IP decoder 1, an LED screen driving module 7, two SFP optical ports and two Ethernet ports, and is provided with one path of alternating current power supply and two paths of PoE power supply interfaces to realize redundant backup power supply of three interfaces; the IP video code stream input with the highest 4K60 resolution can be received from a LAN or WAN network, and the echoing or HDMI equipment cascade connection is realized; one control system can drive 16 paths of LED display screens, and spliced pixels reach ultra-high definition 4K 60; the USB flash disk has the functions of keyboard and mouse output and a USB3.0 read-write interface, and can store user contents into a storage space of 16GByte through a high-speed parallel data protocol or read the user contents for display. The invention has the advantages of high integration level, small volume, flexible interface, convenient operation and the like, can conveniently realize the multi-path LED screen display and content storage of users, and ensures that the product has higher market competitiveness.
In this embodiment, after the IP decoder 1 obtains the to-be-displayed 4-view signal through the network switch module 2, it first decodes the to-be-displayed 4K signal into an HDMI video signal, then, the HDMI video signal is transmitted to the HDMI receiver 5, and after the HDMI receiver 5 decodes the HDMI video signal into RGB video signals, the RGB video signals are sent to an FPGA module 6, the FPGA module 6 groups the RGB video signals according to the configuration of a switching chip in an LED screen driving module 7 to obtain a plurality of output signals, finally, the LED screen driving module 7 outputs the output signals to a display device based on the configuration of the switching chip, in the whole display process, the 4K signals to be displayed are spliced and displayed through the IP decoder 1 and the LED screen driving module 7 by means of the HDMI receiver 5 and the FPGA module 6, therefore, the technical problem that the splicing display of the 4K signal is difficult to realize in the existing video display control system is solved.
The terms "first," "second," "third," "fourth," and the like in the description of the application and the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present application, or a part or all or part of the technical solution that contributes to the prior art, may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. A control system for video display, comprising: the system comprises a network switching module, an IP decoder, an LED screen driving module, an HDMI receiver and an FPGA module;
the network switching module is used for receiving a 4K signal to be displayed and sending the 4K signal to be displayed to the IP decoder;
the IP decoder is used for decoding the 4K signal to be displayed into an HDMI video signal and sending the HDMI video signal to the HDMI receiver;
the HDMI receiver is used for decoding the HDMI video signals into RGB video signals and sending the RGB video signals to the FPGA module;
the FPGA module is used for grouping the RGB video signals according to the configuration of a switching chip in the LED screen driving module to obtain a plurality of paths of output signals;
and the LED screen driving module is used for outputting a plurality of output signals to display equipment based on the configuration of the exchange chip.
2. The control system for video display according to claim 1, wherein the output signal comprises: a sub video signal and a signal identifier corresponding to the sub video signal;
the configuration of the switching chip comprises: exchanging the number of chips, the number of channels of signal transmission channels and channel identifications corresponding to the signal transmission channels;
the signal identification corresponds to the channel identification;
the LED screen driving module is specifically configured to send the output signal to the display device based on the number of switching chips, the number of channels, and the channel identifier.
3. The control system for video display according to claim 2, wherein the number of said output signals is 16;
the number of the switching chips is two, and the number of the signal transmission channels is 16.
4. The control system for video display according to claim 1, further comprising: the HDMI connector comprises a signal conversion module and an HDMI connector;
the signal conversion module is used for copying the HDMI video signals output by the IP decoder to obtain two paths of HDMI video signals and respectively sending the two paths of HDMI video signals to the HDMI receiver and the HDMI connector;
the HDMI connector is used for displaying back in the display control process of the 4K signal to be displayed.
5. The control system for video display according to claim 1, wherein the network switching module comprises: a network switching chip and an input interface;
the input interface is used for receiving the 4K signal to be displayed;
and the network switching chip is used for sending the 4K signal to be displayed to the IP decoder.
6. The control system for video display according to claim 5, wherein said input interface comprises: an optical module interface and/or an ethernet interface.
7. The control system for video display according to claim 6, wherein when the input interface includes an ethernet interface, the ethernet interface is specifically: PoE network interface type interface.
8. The control system for video display according to claim 7, wherein the power module of the control system comprises: the device comprises an AC-DC module and a PoE direct current conversion module;
the AC-DC module is used for converting an external power supply into preset voltage and inputting the preset voltage into the control system;
and the PoE direct current conversion module is used for carrying out power supply handshake negotiation with an external PSE switch, and inputting the preset voltage into the control system after adjusting the power supply separated by the Ethernet interface to the preset voltage.
9. The control system for video display according to claim 1, further comprising: a USB interface module;
the USB interface module is connected with the IP decoder.
10. The control system for video display according to claim 1, further comprising: a storage module;
the storage module is connected with the IP decoder.
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| CN202010920856.6A CN112019863A (en) | 2020-09-04 | 2020-09-04 | Control system for video display |
| PCT/CN2020/141572 WO2022048089A1 (en) | 2020-09-04 | 2020-12-30 | Control system for video display |
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| CN202010920856.6A CN112019863A (en) | 2020-09-04 | 2020-09-04 | Control system for video display |
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| CN112788429A (en) * | 2021-02-25 | 2021-05-11 | 中国电子科技集团公司第五十二研究所 | Screen sharing system based on network |
| CN113676463A (en) * | 2021-04-23 | 2021-11-19 | 音王电声股份有限公司 | LED management control system and LED platform based on AIoT |
| WO2022048089A1 (en) * | 2020-09-04 | 2022-03-10 | 威创集团股份有限公司 | Control system for video display |
| CN115988155A (en) * | 2023-03-20 | 2023-04-18 | 广州美凯信息技术股份有限公司 | Splicing display method and display system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117156090A (en) * | 2023-10-30 | 2023-12-01 | 浙江禾川科技股份有限公司 | Remote display device, system and method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254513A (en) * | 2011-07-14 | 2011-11-23 | 康佳集团股份有限公司 | Multifunctional control system for light-emitting diode (LED) display screen |
| US20130162754A1 (en) * | 2003-03-10 | 2013-06-27 | Meetrix Communication, Inc. | Audio-video multi-participant conference systems using pstn and internet networks |
| CN104091558A (en) * | 2013-04-01 | 2014-10-08 | 香港理工大学 | LED display panel driving method and system |
| CN205212951U (en) * | 2015-11-30 | 2016-05-04 | 华东师范大学 | 4K display screen devices that show more |
| CN105744181A (en) * | 2016-03-30 | 2016-07-06 | 金三立视频科技（深圳）有限公司 | Video conversion display method and system based on CPLD |
| CN205657809U (en) * | 2016-05-09 | 2016-10-19 | 华东师范大学 | Wireless synchronization display device of high -speed video under multiple source multi -mode |
| CN106572283A (en) * | 2016-02-02 | 2017-04-19 | 合肥爱维信息科技有限公司 | We-media portable ultra-high-definition integrated machine |
| CN208768178U (en) * | 2018-09-27 | 2019-04-19 | 深圳京视科技有限公司 | A kind of LED-4K screen data processing system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2647664C1 (en) * | 2017-03-31 | 2018-03-16 | Общество С Ограниченной Ответственностью "Заботливый Город" | Method of processing video signal |
| CN207752739U (en) * | 2018-01-31 | 2018-08-21 | 国春鹏 | display device with splicing function |
| CN112019863A (en) * | 2020-09-04 | 2020-12-01 | 威创集团股份有限公司 | Control system for video display |
-
2020
- 2020-09-04 CN CN202010920856.6A patent/CN112019863A/en active Pending
- 2020-12-30 WO PCT/CN2020/141572 patent/WO2022048089A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130162754A1 (en) * | 2003-03-10 | 2013-06-27 | Meetrix Communication, Inc. | Audio-video multi-participant conference systems using pstn and internet networks |
| CN102254513A (en) * | 2011-07-14 | 2011-11-23 | 康佳集团股份有限公司 | Multifunctional control system for light-emitting diode (LED) display screen |
| CN104091558A (en) * | 2013-04-01 | 2014-10-08 | 香港理工大学 | LED display panel driving method and system |
| CN205212951U (en) * | 2015-11-30 | 2016-05-04 | 华东师范大学 | 4K display screen devices that show more |
| CN106572283A (en) * | 2016-02-02 | 2017-04-19 | 合肥爱维信息科技有限公司 | We-media portable ultra-high-definition integrated machine |
| CN105744181A (en) * | 2016-03-30 | 2016-07-06 | 金三立视频科技（深圳）有限公司 | Video conversion display method and system based on CPLD |
| CN205657809U (en) * | 2016-05-09 | 2016-10-19 | 华东师范大学 | Wireless synchronization display device of high -speed video under multiple source multi -mode |
| CN208768178U (en) * | 2018-09-27 | 2019-04-19 | 深圳京视科技有限公司 | A kind of LED-4K screen data processing system |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022048089A1 (en) * | 2020-09-04 | 2022-03-10 | 威创集团股份有限公司 | Control system for video display |
| CN112788429A (en) * | 2021-02-25 | 2021-05-11 | 中国电子科技集团公司第五十二研究所 | Screen sharing system based on network |
| CN112788429B (en) * | 2021-02-25 | 2024-05-14 | 中国电子科技集团公司第五十二研究所 | Screen sharing system based on network |
| CN113676463A (en) * | 2021-04-23 | 2021-11-19 | 音王电声股份有限公司 | LED management control system and LED platform based on AIoT |
| CN115988155A (en) * | 2023-03-20 | 2023-04-18 | 广州美凯信息技术股份有限公司 | Splicing display method and display system |
| CN115988155B (en) * | 2023-03-20 | 2023-08-18 | 广州美凯信息技术股份有限公司 | Spliced display method and display system |
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