CN201499263U - Single-fiber single-wavelength 1080P VOOP - Google Patents
Single-fiber single-wavelength 1080P VOOP Download PDFInfo
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- CN201499263U CN201499263U CN2009203104721U CN200920310472U CN201499263U CN 201499263 U CN201499263 U CN 201499263U CN 2009203104721 U CN2009203104721 U CN 2009203104721U CN 200920310472 U CN200920310472 U CN 200920310472U CN 201499263 U CN201499263 U CN 201499263U
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Abstract
The utility model discloses a single-fiber single-wavelength 1080P VOOP (video optical multiplexer), which includes an FPGA chip with a built-in hard IP core; an input terminal video DAC (digital-to-analogue conversion) part and an output terminal video DAC part connected with the chip; an audio DAC part connected with the chip; a DDR2 memorizer connected with the chip; and an MCU singlechip connected with the chip, the input terminal video DAC part and the output terminal video DAC part. External interfaces of the input terminal video DAC part and the output terminal video DAC part includes RGB, YUV, DVI and HDMI interfaces, so that the VOOP conveniently meets the present use requirement of a user, and gives consideration to technical improvements on rapid changed terminal product ports; and when a customer uses a new terminal device, the expensive fiber transmission equipment is not required to be changed, the customer resource is protected, and the 1080P high-definition image transmission on single-fiber single-wavelength is realized creatively.
Description
Technical field
The utility model relates to video image transmission equipment field, especially a kind of single fiber list wavelength 1080P video optical multiplexer.
Background technology
Current, the high definition that has all begun image in radio and television, advertising and video frequency graphic monitoring system is used, and in use usually faces high-definition image to be sent to by optical fiber to reach tens of kilometers far-end.The end product port technique changes fast, need change expensive fibre optic transmission equipment when the client adopts new terminal equipment.
The utility model content
The purpose of this utility model provides a kind of convenient, flexible single fiber list wavelength 1080P video optical multiplexer of a plurality of business interface application, product up-gradation and change that satisfies.
Single fiber list wavelength 1080P video optical multiplexer of the present utility model is achieved by following technical proposals:
Single fiber list wavelength 1080P video optical multiplexer comprises the optical transceiver main control chip; The input video digital-to-analogue conversion parts that are connected with this optical transceiver main control chip, output video digital-to-analogue conversion parts; The audio frequency digital-to-analogue conversion parts that are connected with this optical transceiver main control chip; The DDR2 memory that is connected with this optical transceiver main control chip; With the MCU single-chip microcomputer that optical transceiver main control chip, input video digital-to-analogue conversion parts and output video digital-to-analogue conversion parts link to each other, the external interface of input video digital-to-analogue conversion parts and output video digital-to-analogue conversion parts includes RGB, YUV, DVI and HDMI interface respectively.
The optical transceiver main control chip is a fpga chip, and the built-in hard IP kernel of FPGA is finished string and conversion designs.
Single fiber list wavelength 1080P video optical multiplexer of the present utility model compared with prior art has following good effect:
On single-core fiber list wavelength, realized the 1080P high-definition image transmission of a plurality of business interfaces (RGB, YUV, DVI, HDMI); make things convenient for the user when satisfying current use; take into account the progress of fast-changing end product port technique; when adopting new terminal equipment, the client need not to change expensive fibre optic transmission equipment, the protection customer resources.The hard IP kernel of FPGA is finished the board structure of circuit compactness of string and conversion designs, and size is less, the antijamming capability that helps PCB layout and improve system, and debugging is flexible in addition, and parameter is provided with convenient.
Description of drawings
The utility model will illustrate by example and with reference to the mode of accompanying drawing, wherein:
Fig. 1 is a system of the present utility model connection diagram.
Embodiment
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
Single fiber list wavelength 1080P video optical multiplexer as shown in Figure 1 comprises the fpga chip of built-in hard IP kernel; The input video digital-to-analogue conversion parts that are connected with this chip, output video digital-to-analogue conversion parts; The audio frequency digital-to-analogue conversion parts that are connected with this chip; The DDR2 memory that is connected with this chip; With the MCU single-chip microcomputer that chip, input video digital-to-analogue conversion parts and output video digital-to-analogue conversion parts link to each other, the external interface of input video digital-to-analogue conversion parts and output video digital-to-analogue conversion parts includes RGB, YUV, DVI and HDMI interface respectively.
FPGA is as the main control chip of system, and the course of work is:
At first receive the data of coming, then deposit this value in a DDR2 memory by the digital-to-analogue conversion parts.Meanwhile from another piece DDR2 memory, read the value of pixel, and send to the data encapsulation module, through the LZW compression, send 32 parallel-by-bit data again; Receive 32 bit data, deposit a DDR2 memory in.With the value of from another piece DDR2 memory, reading pixel,, send to the data encapsulation module therewith, recover HV, RGB, data such as YUV through the LZW decompress(ion).
BUF receives 32 bit data buffer memorys.State and which DDR2 that MUX selects module to be used to select which DDR2 to be in and is written into data are in the state that is read out data.The main task of module is to coordinate the read-write operation of two DDR2, and when first DDR2 was written into data, second DDR2 was read out data and supplies.After first DDR2 deposits complete piece image data in, two DDR2 exchange read-write operations, first DDR2 is by being written into transformation of data for being read out data, second DDR2 is by being read out transformation of data for being written into data, after second DDR2 deposits complete piece image data in, switch the read-write operation of two DDR2 again, so circulation.Deposit a two field picture at a high speed in, in the time that deposits a two field picture in, read viewable portion in the frame in another DDR2, the speed that reads so will reduce, and serial data stream also can be reduced accordingly.Thereby reduced transmission rate.
When powering in system, is responsible for the DDR2 controller module initialization DDR2.After treating that the DDR2 initialization finishes, controller module receives the index signal of peripheral module again, and sends corresponding read-write operation order according to index signal to DDR2, guarantees correctly writing and reading of data, and the refreshing of DDR2.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (2)
1. single fiber list wavelength 1080P video optical multiplexer comprises the optical transceiver main control chip; The input video digital-to-analogue conversion parts that are connected with this optical transceiver main control chip, output video digital-to-analogue conversion parts; The audio frequency digital-to-analogue conversion parts that are connected with this optical transceiver main control chip; The DDR2 memory that is connected with this optical transceiver main control chip; With optical transceiver main control chip, input video digital-to-analogue conversion parts and the MCU single-chip microcomputer that output video digital-to-analogue conversion parts link to each other, it is characterized in that: the external interface of input video digital-to-analogue conversion parts and output video digital-to-analogue conversion parts includes RGB, YUV, DVI and HDMI interface respectively.
2. single fiber list wavelength 1080P video optical multiplexer according to claim 1, it is characterized in that: described optical transceiver main control chip is a fpga chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009203104721U CN201499263U (en) | 2009-09-16 | 2009-09-16 | Single-fiber single-wavelength 1080P VOOP |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009203104721U CN201499263U (en) | 2009-09-16 | 2009-09-16 | Single-fiber single-wavelength 1080P VOOP |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201499263U true CN201499263U (en) | 2010-06-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009203104721U Expired - Fee Related CN201499263U (en) | 2009-09-16 | 2009-09-16 | Single-fiber single-wavelength 1080P VOOP |
Country Status (1)
| Country | Link |
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| CN (1) | CN201499263U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420964A (en) * | 2011-12-01 | 2012-04-18 | 吕宁 | Real-time high definition video transmitter |
| CN102420965A (en) * | 2011-12-01 | 2012-04-18 | 吕宁 | Real-time high-definition video receiving device |
| CN102497534A (en) * | 2011-12-01 | 2012-06-13 | 吕宁 | Distribution network full high definition video matrix system |
| CN109036276A (en) * | 2018-09-25 | 2018-12-18 | 深圳市峰泳科技有限公司 | A kind of Micro-OLED miniscope driving circuit |
-
2009
- 2009-09-16 CN CN2009203104721U patent/CN201499263U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420964A (en) * | 2011-12-01 | 2012-04-18 | 吕宁 | Real-time high definition video transmitter |
| CN102420965A (en) * | 2011-12-01 | 2012-04-18 | 吕宁 | Real-time high-definition video receiving device |
| CN102497534A (en) * | 2011-12-01 | 2012-06-13 | 吕宁 | Distribution network full high definition video matrix system |
| CN102497534B (en) * | 2011-12-01 | 2014-10-29 | 吕宁 | Distribution network full high definition video matrix system |
| CN109036276A (en) * | 2018-09-25 | 2018-12-18 | 深圳市峰泳科技有限公司 | A kind of Micro-OLED miniscope driving circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160421 Address after: 610000 Sichuan city of Chengdu province Tianfu Tianfu Avenue South Huayang Street No. 846 Patentee after: CHENGDU YINGDESI NETWORK TECHNOLOGY CO., LTD. Address before: 610000, No. 536, section one, Airport Road, SW port, Shuangliu, Sichuan, Chengdu Patentee before: Chengdu Vad Digital Systems Technology Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100602 Termination date: 20170916 |