CN203691517U - Circuit with limitation of signal bandwidth in DVI matrix - Google Patents
Circuit with limitation of signal bandwidth in DVI matrix Download PDFInfo
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- CN203691517U CN203691517U CN201320890173.6U CN201320890173U CN203691517U CN 203691517 U CN203691517 U CN 203691517U CN 201320890173 U CN201320890173 U CN 201320890173U CN 203691517 U CN203691517 U CN 203691517U
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Abstract
The utility model discloses a circuit with limitation of signal bandwidth in a DVI matrix, which comprises a signal source; a display with an EEPROM interface and a DVI interface, wherein EDID information is stored in the EEPROM; the DVI matrix which is connected to the signal source and the DVI interface and transmits video signals output by the signal source to a display for display; and a host which connects the display and the signal source, wherein the host comprises an I2C interface and a RS-232 interface, and is connected to the display by the I2C interface and connected to a level switch chip U3 by the RS-232 interface; and also comprises a key switch S1, a resistance R1 and a resistance R2, a 5V power source, a voltage comparator U1, a single processing chip U2, the level switch chip U3 and a linear voltage regulator. With the utility model, the signal bandwidth in the DVI matrix can be limited according to a user's operations to the key switch S1 in order to increase effective transmission distance of DVI signals.
Description
Technical field
The utility model relates to the circuit of signal bandwidth in a kind of DVI of restriction matrix.
Background technology
EDID is external display device identification data, and its data message that comprises display device is as resolution, refresh rate, maximum image size, color characteristic, the prior setup times that dispatches from the factory, frequency range restriction and monitor title etc.; In prior art, main frame, by DDC display data channel access display to obtain the EDID data message in display EEPROM, confirms that the display properties of display is as information such as resolution, to complete display and signal source communication explanation self performance.
In AV field, DVI matrix uses more and more extensive, it is for transferring to display by the DVI signal of signal source output, for the transmission of DVI signal, because the code stream of DVI signal is that signal bandwidth is very high, in transmitting procedure, can run into the restriction of signal transmission distance, such as the DVI signal with normal 1.65GHz, effective propagation path is 5m, but in actual applications, because the job site environment difference of DVI matrix does not make the DVI length of cable that needs not etc., and then can not ensure the effective propagation path of DVI signal, often cause the vision signal of signal source output cannot normally show on display device, DVI signal bandwidth equals the product of resolution and refreshing frequency, therefore in the time that DVI length of cable exceedes maximum effective propagation path corresponding to DVI signal bandwidth, can be by reducing resolution or refreshing frequency, and then signal bandwidth in reduction DVI matrix, thereby improve the effective propagation path of DVI signal, the problem of avoiding the vision signal of signal source output cannot normally show on display device.
Summary of the invention
The utility model is for the proposition of above problem, and develops the circuit of signal bandwidth in a kind of DVI of restriction matrix.
The technical solution of the utility model is:
A circuit that limits signal bandwidth in DVI matrix, comprising:
Signal source;
There is the display of EEPROM and DVI interface; In described EEPROM, store EDID information;
Connecting signal source and DVI interface, the DVI matrix that the video signal transmission that signal source is exported to display shows;
Connect the main frame of display and signal source; Described main frame has I2C interface and RS-232 interface, and this main frame connects display by I2C interface, connects level transferring chip U3 by RS-232 interface;
Also comprise:
Key switch S1, resistance R 1 and R2,5V power supply, voltage comparator U1, signal processing chip U2, level transferring chip U3 and linear voltage regulator chip U4;
Described key switch S1 and resistance R 1 are connected in series between 5V VDD-to-VSS mutually; The inverting input of described voltage comparator U1 is connected with the phase contact of key switch S1 and resistance R 1; The input of described linear voltage regulator chip U4 connects 5V power supply, and the output of this linear voltage regulator chip U4 is connected to the in-phase input end of voltage comparator U1 by resistance R 2; The output of described voltage comparator U1 is connected with the pin P1.0 of signal processing chip U2; The pin RXD of described signal processing chip U2 connects the pin RXIN of level transferring chip U3, and the pin TXD of this signal processing chip U2 connects the pin TXIN of level transferring chip U3; The pin RXOUT of described level transferring chip U3 is connected with the RS-232 interface that pin TXOUT has with main frame;
Further:
When key switch S1 is during in off-state, described voltage comparator U1 output high level, the EDID information in the EEPROM reading is exported to signal source by described main frame;
Closed key switch S1 in the time that user is greater than a threshold value according to DVI length of cable, described voltage comparator U1 output low level, described main frame will be exported to signal source after the resolution comprising in the EDID information in the EEPROM reading or refreshing frequency reduction;
Further, described voltage comparator U1 adopts LM311;
Further, described signal processing chip U2 adopts STC89C52;
Further, described level transferring chip U3 adopts MAX232;
Further, described linear voltage regulator chip U4 adopts AS1117.
Owing to having adopted technique scheme, the circuit of signal bandwidth in a kind of DVI of restriction matrix that the utility model provides, can realize DVI length of cable and be greater than a threshold value, operation according to user to key switch S1, main frame is exported to signal source after the resolution comprising in the EDID information reading or refreshing frequency information are reduced, signal source is exported corresponding vision signal according to EDID information and is shown to display via DVI Transfer-matrix, due to resolution or refreshing frequency reduction, the corresponding reduction of the bandwidth of video signal of output, and then signal bandwidth in restriction DVI matrix, thereby improve the effective propagation path of DVI signal, avoid because the job site environment difference of DVI matrix does not make the DVI length of cable that needs not etc., and then can not ensure the effective propagation path of DVI signal, the problem that often causes the vision signal of signal source output cannot normally show on display device.
Brief description of the drawings
Fig. 1 is circuit theory diagrams of the present utility model.
Embodiment
A kind of circuit that limits signal bandwidth in DVI matrix as shown in Figure 1, comprising: signal source; There is the display of EEPROM and DVI interface; In described EEPROM, store EDID information; Connecting signal source and DVI interface, the DVI matrix that the video signal transmission that signal source is exported to display shows; Connect the main frame of display and signal source; Described main frame has I2C interface and RS-232 interface, and this main frame connects display by I2C interface, connects level transferring chip U3 by RS-232 interface; Also comprise: key switch S1, resistance R 1 and R2,5V power supply, voltage comparator U1, signal processing chip U2, level transferring chip U3 and linear voltage regulator chip U4; Described key switch S1 and resistance R 1 are connected in series between 5V VDD-to-VSS mutually; The inverting input of described voltage comparator U1 is connected with the phase contact of key switch S1 and resistance R 1; The input of described linear voltage regulator chip U4 connects 5V power supply, and the output of this linear voltage regulator chip U4 is connected to the in-phase input end of voltage comparator U1 by resistance R 2; The output of described voltage comparator U1 is connected with the pin P1.0 of signal processing chip U2; The pin RXD of described signal processing chip U2 connects the pin RXIN of level transferring chip U3, and the pin TXD of this signal processing chip U2 connects the pin TXIN of level transferring chip U3; The pin RXOUT of described level transferring chip U3 is connected with the RS-232 interface that pin TXOUT has with main frame; Further: when key switch S1 is during in off-state, described voltage comparator U1 output high level, the EDID information in the EEPROM reading is exported to signal source by described main frame; Closed key switch S1 in the time that user is greater than a threshold value according to DVI length of cable, described voltage comparator U1 output low level, described main frame will be exported to signal source after the resolution comprising in the EDID information in the EEPROM reading or refreshing frequency reduction; Further, described voltage comparator U1 adopts LM311; Further, described signal processing chip U2 adopts STC89C52; Further, described level transferring chip U3 adopts MAX232; Further, described linear voltage regulator chip U4 adopts AS1117.
A kind of course of work that limits the circuit of signal bandwidth in DVI matrix described in the utility model is as follows:
When DVI length of cable is during lower than a threshold value, the effective propagation path of the corresponding DVI cable of DVI signal that this threshold value is certain bandwidth, user does not need any operation, key switch S1 is off-state, the inverting input of described voltage comparator U1 is 0V, linear voltage regulator chip U4 is 3.3V output by the 5V voltage transitions of input, the in-phase input end of voltage comparator U1 connects 3.3V by resistance R 2, voltage comparator U1 exports high level, this high level signal exports level transferring chip U3 to after encoding via signal processing chip U2, the high level signal of level transferring chip U3 after to coding carries out exporting to after level protocol conversion the RS232 interface of main frame, main frame is exported to signal source by the EDID information in the EEPROM reading after receiving high level signal, signal source is exported corresponding vision signal according to EDID information and is shown to display via DVI Transfer-matrix,
In the time that DVI length of cable is greater than a threshold value, user carries out key switch S1 closed procedure, the inverting input of described voltage comparator U1 becomes 5V, the in-phase input end of voltage comparator U1 connects 3.3V by resistance R 2, voltage comparator U1 output low level, this low level signal exports level transferring chip U3 to after encoding via signal processing chip U2, the low level signal of level transferring chip U3 after to coding carries out exporting to after level protocol conversion the RS232 interface of main frame, main frame will be exported to signal source after the resolution comprising in the EDID information in the EEPROM reading or the reduction of refreshing frequency information after receiving low level signal, signal source is exported corresponding vision signal according to EDID information and is shown to display via DVI Transfer-matrix, in real process, main frame can be by decrease resolution to 1024*768, this is the resolution that most displays can be supported, and then guarantee an available image, similarly, refreshing frequency can be reduced to 55Hz etc. by 60Hz, inventive point of the present utility model does not also lie in the technological means that main frame reduces the resolution comprising in the EDID information in the EEPROM reading or refreshing frequency information, the concrete technology of this part realizes utilizes main frame of the prior art all can complete, due to resolution or refresh rate reduction, the corresponding reduction of the bandwidth of video signal of output, and then signal bandwidth in restriction DVI matrix, thereby improve the effective propagation path of DVI signal, the problem of having avoided the vision signal of signal source output cannot normally show on display device.
The above; it is only preferably embodiment of the utility model; but protection range of the present utility model is not limited to this; any be familiar with those skilled in the art the utility model disclose technical scope in; be equal to replacement or changed according to the technical solution of the utility model and inventive concept thereof, within all should being encompassed in protection range of the present utility model.
Claims (6)
1. a circuit that limits signal bandwidth in DVI matrix, comprising:
Signal source;
There is the display of EEPROM and DVI interface; In described EEPROM, store EDID information;
Connecting signal source and DVI interface, the DVI matrix that the video signal transmission that signal source is exported to display shows;
Connect the main frame of display and signal source; Described main frame has I2C interface and RS-232 interface, and this main frame connects display by I2C interface;
Characterized by further comprising:
Key switch S1, resistance R 1 and R2,5V power supply, voltage comparator U1, signal processing chip U2, level transferring chip U3 and linear voltage regulator chip U4;
Described key switch S1 and resistance R 1 are connected in series between 5V VDD-to-VSS mutually; The inverting input of described voltage comparator U1 is connected with the phase contact of key switch S1 and resistance R 1; The input of described linear voltage regulator chip U4 connects 5V power supply, and the output of this linear voltage regulator chip U4 is connected to the in-phase input end of voltage comparator U1 by resistance R 2; The output of described voltage comparator U1 is connected with the pin P1.0 of signal processing chip U2; The pin RXD of described signal processing chip U2 connects the pin RXIN of level transferring chip U3, and the pin TXD of this signal processing chip U2 connects the pin TXIN of level transferring chip U3; The pin RXOUT of described level transferring chip U3 is connected with the RS-232 interface that pin TXOUT has with main frame.
2. a kind of circuit that limits signal bandwidth in DVI matrix according to claim 1, is characterized in that:
When key switch S1 is during in off-state, described voltage comparator U1 output high level, the EDID information in the EEPROM reading is exported to signal source by described main frame;
Closed key switch S1 in the time that user is greater than a threshold value according to DVI length of cable, described voltage comparator U1 output low level, described main frame will be exported to signal source after the resolution comprising in the EDID information in the EEPROM reading or refreshing frequency reduction.
3. a kind of circuit that limits signal bandwidth in DVI matrix according to claim 1, is characterized in that described voltage comparator U1 adopts LM311.
4. a kind of circuit that limits signal bandwidth in DVI matrix according to claim 1, is characterized in that described signal processing chip U2 adopts STC89C52.
5. a kind of circuit that limits signal bandwidth in DVI matrix according to claim 1, is characterized in that described level transferring chip U3 adopts MAX232.
6. a kind of circuit that limits signal bandwidth in DVI matrix according to claim 1, is characterized in that described linear voltage regulator chip U4 adopts AS1117.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320890173.6U CN203691517U (en) | 2013-12-31 | 2013-12-31 | Circuit with limitation of signal bandwidth in DVI matrix |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320890173.6U CN203691517U (en) | 2013-12-31 | 2013-12-31 | Circuit with limitation of signal bandwidth in DVI matrix |
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| Publication Number | Publication Date |
|---|---|
| CN203691517U true CN203691517U (en) | 2014-07-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201320890173.6U Expired - Fee Related CN203691517U (en) | 2013-12-31 | 2013-12-31 | Circuit with limitation of signal bandwidth in DVI matrix |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105045741A (en) * | 2015-06-22 | 2015-11-11 | 中航光电科技股份有限公司 | DVI optical transceiver and EDID information processing method for same |
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2013
- 2013-12-31 CN CN201320890173.6U patent/CN203691517U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105045741A (en) * | 2015-06-22 | 2015-11-11 | 中航光电科技股份有限公司 | DVI optical transceiver and EDID information processing method for same |
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Effective date of registration: 20160330 Address after: Hi Tech Park Kehai street Dalian city Liaoning province 116023 No. 3 office building A block 3 layer Patentee after: DALIAN GIGATEC TECHNOLOGY CO.,LTD. Address before: Hi Tech Park Kehai street Dalian city Liaoning province 116023 No. 3 Patentee before: DALIAN GIGATEC ELECTRONICS Co.,Ltd. |
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Granted publication date: 20140702 |