CN115941399A - High-speed VCM signal demodulation device - Google Patents
High-speed VCM signal demodulation device Download PDFInfo
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- CN115941399A CN115941399A CN202211533784.5A CN202211533784A CN115941399A CN 115941399 A CN115941399 A CN 115941399A CN 202211533784 A CN202211533784 A CN 202211533784A CN 115941399 A CN115941399 A CN 115941399A
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Abstract
The invention discloses a high-speed VCM signal demodulation device, and relates to a VCM signal demodulation and equalization technology in the field of satellite remote sensing data reception. The device comprises a carrier source, an orthogonal down converter, a clock source, an AD (analog-to-digital) converter, a matched filter, a sampling error conversion DDS (direct digital synthesis), a timing error extractor, a frame synchronization detection module, a carrier error conversion DDS, a carrier error weighting module, a frame header extraction module, a pilot frequency extraction module, a frequency offset estimation module, a pilot frequency carrier error extraction module, a data carrier error extraction module and a balancing module. The invention adopts the analog-digital mixed signal processing method, effectively reduces the consumption of VCM signal demodulation algorithm to FPGA logic resources, and improves the adaptability and stability of the device. The invention comprehensively utilizes the pilot signal and the data signal, completes VCM signal frequency offset estimation and carrier phase error calculation, and improves the accuracy and stability of VCM signal demodulation and carrier recovery.
Description
Technical Field
The invention relates to the field of communication and data transmission, in particular to a receiving and demodulating device which is used for a high-speed VCM signal system in a satellite remote sensing data transmission system.
Background
The traditional high-speed VCM demodulation device adopts an intermediate-frequency sampling all-digital implementation scheme and completes the demodulation of a high-speed VCM signal by using a VCM physical frame structure and pilot frequency information. However, since demodulation of the high-rate VCM signal is complex, a large amount of FPGA logic resources are consumed, which is not conducive to transplantation and debugging, and is also not conducive to integration of other transmission signal demodulation functions employed in the satellite remote sensing data transmission system, in addition, since the pilot frequency in the VCM physical frame is comb-inserted and the signal form is fixed, only the pilot frequency is utilized for operation processing, and the accuracy and real-time performance of carrier recovery and equalization filtering are poor, thereby reducing the performance of the high-rate VCM signal demodulation apparatus.
Disclosure of Invention
The present invention is directed to provide a high-rate UQPSK signal demodulation apparatus that avoids the above-mentioned disadvantages of the background art. The invention has the characteristics of high reliability, high stability, low complexity of realization and the like.
The purpose of the invention is realized as follows:
a high-speed VCM signal demodulation device comprises a carrier source 1, an orthogonal down converter 2, a clock source 3, a first AD4-1 and a second AD4-2, a first matched filter 5-1 and a second matched filter 5-2, a sampling error conversion DDS6, a timing error extractor 7, a frame synchronization detection module 8, a carrier error conversion DDS9, a carrier error weighting module 10, a frame header extraction module 11, a pilot frequency extraction module 12, a frequency offset estimation module 13, a pilot frequency carrier error extraction module 14, a data carrier error extraction module 15 and an equalization module 16;
the quadrature down converter 2 carries out analog quadrature down conversion on the input VCM intermediate frequency modulation signal to generate I/Q two paths of analog baseband signals;
the I/Q two paths of analog baseband signals are respectively converted into I/Q two paths of digital baseband signals through the first AD4-1 and the second AD 4-2;
the I/Q two paths of digital baseband signals are respectively processed by a first matched filter 5-1 and a second matched filter 5-2 and are branched to generate seven paths of I digital baseband signals and seven paths of Q digital baseband signals; the first path of I digital baseband signal and the first path of Q digital baseband signal are respectively transmitted to the timing error extractor 7, the second path of I digital baseband signal and the second path of Q digital baseband signal are respectively transmitted to the frame synchronization detection module 8, the third path of I digital baseband signal and the third path of Q digital baseband signal are respectively transmitted to the frame header extraction module 11, the fourth path of I digital baseband signal and the fourth path of Q digital baseband signal are respectively transmitted to the pilot extraction module 12, the fifth path of I digital baseband signal and the fifth path of Q digital baseband signal are respectively transmitted to the frequency offset estimation module 13, the sixth path of I digital baseband signal and the sixth path of Q digital baseband signal are respectively transmitted to the data carrier error extraction module 15, and the seventh path of I digital baseband signal and the seventh path of Q digital baseband signal are respectively transmitted to the equalization module 16;
the timing error extractor 7 generates an AD sampling timing error value, adjusts the current generated error value in real time and outputs an accumulated step signal, and the accumulated step signal is transmitted to a sampling error conversion DDS6;
the signal output by the sampling error conversion DDS6 is transmitted to the clock source 3;
the clock source 3 carries out frequency mixing filtering processing on an internally generated clock signal and a received sampling error conversion DDS6 output signal, generates an AD sampling clock signal and transmits the AD sampling clock signal to a first AD4-1 and a second AD4-2, and further completes timing synchronization of a VCM signal through AD sampling;
the frame synchronization detection module 8 completes frame header detection by using a frame header synchronization sequence, and then generates a frame synchronization indication signal and transmits the frame synchronization indication signal to the frame header extraction module 11;
the frame header extraction module 11 extracts frame header information from the third I path of received digital baseband signals and the third Q path of received digital baseband signals according to the received frame synchronization indication signal, so as to generate a pilot indication signal and a modulation system indication signal, transmit the pilot indication signal to the pilot extraction module 12, and transmit the modulation system indication signal to the data carrier error extraction module 15 and the equalization module 16, respectively;
the pilot extraction module 12 extracts two I/Q pilot signals from the fourth I and Q digital baseband signals according to the received pilot indication signal, and transmits the extracted two I/Q pilot signals to the frequency offset estimation module 13, the pilot carrier error extraction module 14 and the equalization module 16, respectively;
the frequency offset estimation module 13 receives the fifth I-path digital baseband signal and the fifth Q-path digital baseband signal, and performs coarse frequency offset estimation by a nonlinear estimation method, meanwhile, the frequency offset estimation module 13 receives the I/Q-path pilot signals, extracts a phase difference from two adjacent sets of pilot signals, performs differential operation on the phase difference to perform fine frequency offset estimation, and finally synthesizes the coarse frequency offset estimation value and the fine frequency offset estimation value into a frequency offset estimation signal and transmits the frequency offset estimation signal to the carrier error weighting module 10;
the pilot carrier error extraction module 14 generates a pilot carrier phase error signal in real time according to the received I/Q two-path pilot signals, and transmits the pilot carrier phase error signal to the carrier error weighting module 10;
the data carrier error extraction module 15 extracts a data carrier phase error signal in real time from the sixth path of received I digital baseband signal and the sixth path of received Q digital baseband signal in a decision feedback manner according to the received modulation system indication signal, and transmits the extracted data carrier phase error signal to the carrier error weighting module 10;
the carrier error weighting module 10 performs weighting mapping processing on the received frequency offset estimation signal, pilot carrier phase error signal and data carrier phase error signal to generate a carrier error value, adjusts an accumulated step value by using the currently generated carrier error value, and transmits the accumulated step value updated in real time to the carrier error conversion DDS9;
the signal output by the carrier error conversion DDS9 is transmitted to a carrier source 1, the carrier source 1 carries out frequency mixing filtering processing on a fixed frequency signal generated inside and a received carrier error conversion DDS9 output signal to generate a carrier signal, the carrier signal is transmitted to an orthogonal down converter 2, and then demodulation and carrier synchronization of a VCM signal are completed through the orthogonal down converter 2;
the equalization module 16 performs hard decision processing on the seventh I path of received digital baseband signals and the seventh Q path of received digital baseband signals according to the received modulation system indication signal, and further generates a data equalization error signal; meanwhile, the equalization module 16 receives the two I/Q pilot signals, generates a pilot equalization error signal by using a known pilot data value, then adjusts the adaptive filter coefficient in real time by using the data equalization error signal and the pilot equalization error signal, performs convolution filtering processing on the input two I/Q digital baseband signals by using the adaptive filter coefficient adjusted in real time, outputs the convolution filtered two I/Q digital baseband signals to other signal processing modules, and completes subsequent signal processing.
Compared with the background art, the invention has the following advantages:
1. compared with the traditional high-speed VCM signal demodulation device, the invention adopts an analog-digital mixed signal processing method, effectively reduces the consumption of VCM signal demodulation algorithm on FPGA logic resources, and improves the adaptability and stability of the device.
2. The invention comprehensively utilizes the pilot signal and the data signal, completes VCM signal frequency offset estimation and carrier phase error calculation, improves the precision and stability of VCM signal demodulation and carrier recovery, and further improves the system performance.
3. The invention fully utilizes the characteristics of the pilot signal and the data signal to complete the self-adaptive equalization of the VCM signal, wherein the high reliability of the pilot signal is utilized to improve the convergence speed of the equalization module, and simultaneously, a large amount of and various data signals are utilized to improve the convergence precision of the equalization module and further improve the system performance.
Drawings
Fig. 1 is a schematic block diagram of the present invention.
Detailed Description
Referring to fig. 1, a high-speed VCM signal demodulation apparatus includes a carrier source 1, an orthogonal down converter 2, a clock source 3, a first AD4-1 and a second AD4-2, a first matched filter 5-1 and a second matched filter 5-2, a sampling error conversion DDS6, a timing error extractor 7, a frame synchronization detection module 8, a carrier error conversion DDS9, a carrier error weighting module 10, a frame header extraction module 11, a pilot extraction module 12, a frequency offset estimation module 13, a pilot carrier error extraction module 14, a data carrier error extraction module 15, and an equalization module 16.
The quadrature down converter 2 carries out analog quadrature down conversion on the input VCM intermediate frequency modulation signal to generate I/Q two paths of analog baseband signals;
the I/Q two paths of analog baseband signals are respectively converted into I/Q two paths of digital baseband signals through sampling by a first AD4-1 and a second AD 4-2;
the I/Q two paths of digital baseband signals are respectively processed by a first matched filter 5-1 and a second matched filter 5-2 and generate seven paths of I digital baseband signals and seven paths of Q digital baseband signals after being shunted;
the first path of I digital baseband signals and the first path of Q digital baseband signals are respectively transmitted to a timing error extractor 7, the timing error extractor 7 generates AD sampling timing error values, the current generated error values are used for real-time adjustment and outputting accumulated stepping signals, and the accumulated stepping signals are transmitted to a sampling error conversion DDS6;
the signal output by the sampling error conversion DDS6 is transmitted to a clock source 3, the clock source 3 carries out frequency mixing filtering processing on an internally generated clock signal and a received sampling error conversion DDS6 output signal to generate an AD sampling clock signal and transmit the AD sampling clock signal to a first AD4-1 and a second AD4-2, and further timing synchronization of the VCM signal is completed through AD sampling;
the second path of I digital baseband signals and the second path of Q digital baseband signals are respectively transmitted to the frame synchronization detection module 8, and the frame synchronization detection module 8 completes frame header detection by using a frame header synchronization sequence, so as to generate frame synchronization indication signals and transmit the frame synchronization indication signals to the frame header extraction module 11;
the frame header extraction module 11 extracts frame header information from the third I path of received digital baseband signals and the third Q path of received digital baseband signals according to the received frame synchronization indication signal, so as to generate a pilot indication signal and a modulation system indication signal, transmit the pilot indication signal to the pilot extraction module 12, and transmit the modulation system indication signal to the data carrier error extraction module 15 and the equalization module 16, respectively;
the pilot extraction module 12 extracts two I/Q pilot signals from the fourth I and Q digital baseband signals according to the received pilot indication signal, and transmits the extracted two I/Q pilot signals to the frequency offset estimation module 13, the pilot carrier error extraction module 14 and the equalization module 16, respectively;
the frequency offset estimation module 13 receives the fifth I-path digital baseband signal and the fifth Q-path digital baseband signal, and performs coarse frequency offset estimation by a nonlinear estimation method, meanwhile, the frequency offset estimation module 13 receives the I/Q-path pilot signals, extracts a phase difference from two adjacent sets of pilot signals, performs differential operation on the phase difference to perform fine frequency offset estimation, and finally synthesizes the coarse frequency offset estimation value and the fine frequency offset estimation value into a frequency offset estimation signal, and transmits the frequency offset estimation signal to the carrier error weighting module 10;
the pilot carrier error extraction module 14 generates a pilot carrier phase error signal in real time according to the received I/Q two-path pilot signals, and transmits the pilot carrier phase error signal to the carrier error weighting module 10;
the data carrier error extraction module 15 extracts a data carrier phase error signal in real time from the sixth path of received I digital baseband signal and the sixth path of received Q digital baseband signal by a decision feedback method according to the received modulation system indication signal, and transmits the extracted data carrier phase error signal to the carrier error weighting module 10;
the carrier error weighting module 10 performs weighting mapping processing on the received frequency offset estimation signal, pilot carrier phase error signal and data carrier phase error signal to generate a carrier error value, adjusts an accumulated step value by using the currently generated carrier error value, and transmits the accumulated step value updated in real time to the carrier error conversion DDS9;
the signal output by the carrier error conversion DDS9 is transmitted to a carrier source 1, the carrier source 1 carries out frequency mixing filtering processing on a fixed frequency signal generated inside and a received carrier error conversion DDS9 output signal to generate a carrier signal, the carrier signal is transmitted to an orthogonal down converter 2, and then the demodulation and carrier synchronization of a VCM signal are completed through the orthogonal down converter 2;
the equalization module 16 performs hard decision processing on the seventh path of I digital baseband signal and the seventh path of Q digital baseband signal according to the received modulation system indication signal, and further generates a data equalization error signal; meanwhile, the equalization module receives the two paths of pilot signals I/Q, generates a pilot equalization error signal by using a known pilot data value, then adjusts the coefficient of the adaptive filter in real time by using the data equalization error signal and the pilot equalization error signal, performs convolution filtering processing on the input two paths of digital baseband signals I/Q by using the coefficient of the adaptive filter adjusted in real time, outputs the I/Q two paths of digital baseband signals subjected to convolution filtering to other signal processing modules and completes subsequent signal processing.
The device utilizes the principle to realize the purposes of high symbol rate VCM signal demodulation and carrier recovery.
In the embodiment, the first matched filter 5-1 and the second matched filter 5-2, the timing error extractor 7, the frame synchronization detection module 8, the carrier error weighting module 10, the frame header extraction module 11, the pilot frequency extraction module 12, the frequency offset estimation module 13, the pilot frequency carrier error extraction module 14, the data carrier error extraction module 15, and the equalization module 16 are all implemented by Virtex7 type FPGA manufactured by XILINX, usa.
In a word, the invention adopts an analog-digital mixed signal processing method aiming at a high-speed VCM signal system adopted in a satellite remote sensing data transmission system, thereby effectively reducing the consumption of VCM signal demodulation algorithm on FPGA logic resources and improving the adaptability and stability of the device. The invention comprehensively utilizes the pilot signal and the data signal, completes VCM signal frequency offset estimation and carrier phase error calculation, improves the accuracy and stability of VCM signal demodulation and carrier recovery, and further improves the system performance.
The invention fully utilizes the characteristics of the pilot signal and the data signal to complete the self-adaptive equalization of the VCM signal. Specifically, the invention utilizes the high reliability of the pilot signal to improve the convergence speed of the equalization module, utilizes a large amount of and various data signals to improve the convergence precision of the equalization module, and further improves the system performance.
Claims (1)
1. A high-speed VCM signal demodulation device is characterized by comprising a carrier source (1), an orthogonal down converter (2), a clock source (3), a first AD (4-1) and a second AD (4-2), a first matched filter (5-1) and a second matched filter (5-2), a sampling error conversion DDS (6), a timing error extractor (7), a frame synchronization detection module (8), a carrier error conversion DDS (9), a carrier error weighting module (10), a frame header extraction module (11), a pilot frequency extraction module (12), a frequency offset estimation module (13), a pilot frequency carrier error extraction module (14), a data carrier error extraction module (15) and an equalization module (16);
the quadrature down converter (2) carries out analog quadrature down conversion on the input VCM intermediate frequency modulation signal to generate I/Q two paths of analog baseband signals;
the I/Q two paths of analog baseband signals are respectively converted into I/Q two paths of digital baseband signals through sampling of a first AD (4-1) and a second AD (4-2);
the I/Q two paths of digital baseband signals are respectively processed by a first matched filter (5-1) and a second matched filter (5-2) and are branched to generate seven paths of I digital baseband signals and seven paths of Q digital baseband signals; the first path of I digital baseband signals and the first path of Q digital baseband signals are respectively transmitted to a timing error extractor (7), the second path of I digital baseband signals and the second path of Q digital baseband signals are respectively transmitted to a frame synchronization detection module (8), the third path of I digital baseband signals and the third path of Q digital baseband signals are respectively transmitted to a frame header extraction module (11), the fourth path of I digital baseband signals and the fourth path of Q digital baseband signals are respectively transmitted to a pilot frequency extraction module (12), the fifth path of I digital baseband signals and the fifth path of Q digital baseband signals are respectively transmitted to a frequency deviation estimation module (13), the sixth path of I digital baseband signals and the sixth path of Q digital baseband signals are respectively transmitted to a data carrier error extraction module (15), and the seventh path of I digital baseband signals and the seventh path of Q digital baseband signals are respectively transmitted to a balancing module (16);
the timing error extractor (7) generates an AD sampling timing error value, and the current generated error value is used for real-time adjustment and outputting an accumulated stepping signal, and the accumulated stepping signal is transmitted to the sampling error conversion DDS (6);
the signal output by the sampling error conversion DDS (6) is transmitted to a clock source (3);
the clock source (3) carries out frequency mixing filtering processing on an internally generated clock signal and a received sampling error conversion DDS (6) output signal, generates an AD sampling clock signal and transmits the AD sampling clock signal to a first AD (4-1) and a second AD (4-2), and further completes timing synchronization of VCM signals through AD sampling;
the frame synchronization detection module (8) completes frame header detection by using a frame header synchronization sequence, and further generates a frame synchronization indication signal and transmits the frame synchronization indication signal to the frame header extraction module (11);
the frame header extraction module (11) extracts frame header information from the third path of the received I digital baseband signals and the third path of the received Q digital baseband signals according to the received frame synchronization indication signals, further generates pilot frequency indication signals and modulation system indication signals, transmits the pilot frequency indication signals to the pilot frequency extraction module (12), and respectively transmits the modulation system indication signals to the data carrier error extraction module (15) and the equalization module (16);
the pilot frequency extracting module (12) extracts two paths of I/Q pilot frequency signals from a fourth path of received I digital baseband signals and a fourth path of received Q digital baseband signals according to the received pilot frequency indicating signals, and respectively transmits the extracted two paths of I/Q pilot frequency signals to the frequency offset estimating module (13), the pilot frequency carrier error extracting module (14) and the equalizing module (16);
the frequency offset estimation module (13) receives a fifth I path of digital baseband signals and a fifth Q path of digital baseband signals, frequency offset rough estimation is completed through a nonlinear estimation method, meanwhile, the frequency offset estimation module (13) receives I/Q path of pilot signals, phase differences are extracted from two adjacent groups of pilot signals, frequency offset fine estimation is completed through differential operation on the phase differences, finally, the frequency offset rough estimation value and the frequency offset fine estimation value are synthesized into a frequency offset estimation signal, and the frequency offset estimation signal is transmitted to the carrier error weighting module (10);
the pilot frequency carrier error extraction module (14) generates a pilot frequency carrier phase error signal in real time according to the received I/Q two-path pilot frequency signals and transmits the pilot frequency carrier phase error signal to the carrier error weighting module (10);
the data carrier error extraction module (15) extracts a data carrier phase error signal from a sixth path of received I digital baseband signal and a sixth path of received Q digital baseband signal in real time in a decision feedback mode according to the received modulation system indication signal, and transmits the extracted data carrier phase error signal to the carrier error weighting module (10);
the carrier error weighting module (10) carries out weighting mapping processing on the received frequency offset estimation signal, the pilot frequency carrier phase error signal and the data carrier phase error signal to generate a carrier error value, adjusts an accumulated step value by using the currently generated carrier error value and transmits the accumulated step value updated in real time to the carrier error conversion DDS (9);
signals output by the carrier error conversion DDS (9) are transmitted to a carrier source (1), the carrier source (1) carries out frequency mixing filtering processing on internally generated fixed frequency signals and received carrier error conversion DDS (9) output signals to generate carrier signals, the carrier signals are transmitted to an orthogonal down converter (2), and then demodulation and carrier synchronization of VCM signals are completed through the orthogonal down converter (2);
the equalization module (16) performs hard decision processing on the seventh path of received I digital baseband signal and the seventh path of received Q digital baseband signal according to the received modulation system indication signal, and further generates a data equalization error signal; meanwhile, the equalization module (16) receives the two paths of pilot signals I/Q, generates a pilot equalization error signal by using a known pilot data value, then adjusts the coefficient of the adaptive filter in real time by using the data equalization error signal and the pilot equalization error signal, performs convolution filtering processing on the two paths of input digital baseband signals I/Q by using the coefficient of the adaptive filter adjusted in real time, outputs the two paths of convolution filtered digital baseband signals I/Q to other signal processing modules and completes subsequent signal processing.
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