CN104333393B - Receiving terminal and receiving terminal method for air-ground narrow-band communication system of unmanned aerial vehicle - Google Patents
Receiving terminal and receiving terminal method for air-ground narrow-band communication system of unmanned aerial vehicle Download PDFInfo
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Abstract
The invention discloses a receiving terminal and a receiving terminal method for an air-ground narrow-band communication system of an unmanned aerial vehicle. The air-ground narrow-band communication system comprises a radio frequency receiving module, an intermediate-frequency filtering module, an ADC and an FPGA, the radio frequency receiving module receives communication signals from the outside and control signals from the FPGA, the output of the radio frequency receiving module is connected with the intermediate-frequency filtering module, the output of the intermediate-frequency filtering module is connected with the ADC, the output of the ADC is connected with the FPGA, the gain control output of the FPGA is connected with the radio frequency receiving module, and the FPGA outputs demodulating data through an internal port. The receiving terminal and receiving terminal method for the air-ground narrow-band communication system of the unmanned aerial vehicle can perfect an air-ground narrow-band signal communication sub-system and method of a system and method for the unmanned aerial vehicle capable of realizing remote measurement, remote control and data transmission; the receiving terminal and receiving terminal method for the air-ground narrow-band communication system of the unmanned aerial vehicle are suitable for an aerial unmanned aerial vehicle receiving terminal and method, and the receiving terminal and receiving terminal method have advantages of low resource consumption, precise data treatment and the like.
Description
Technical field
The present invention relates to a kind of receiving terminal for the air-ground narrow-band communication system of unmanned plane and its method.
Background technology
Unmanned plane has the advantages that cost effectiveness is low, zero injures and deaths and deployment are flexible, can help or even be that instead of the mankind very
Play a role in many scenes, such as the personnel after calamity search and rescue, infrastructure is supervised etc..No matter in civilian or military domain, unmanned
Machine all has wide application and development prospect.
The system of unmanned plane that passes of remote measurement, remote control, number can include Air-Ground two-way communication and ground-ground two-way communication two parts,
Divided according to wire data type, wideband signal communication and narrow band signal communication two types can be divided into, its middle width strip is believed
Number be unmanned plane reconnaissance image data transmission service and unmanned plane telemetry service, narrow band signal be distant between handheld terminal and unmanned plane
Control communication service, communication service between handheld terminal and car-mounted terminal.And a critically important link in narrow band communication is exactly it
Receiving terminal and its method, receiving terminal includes unmanned plane terminal.
Content of the invention
It is an object of the invention to overcoming the deficiencies in the prior art, provide that a kind of resource loss is low, data processing is accurate
Receiving terminal for the air-ground narrow-band communication system of unmanned plane and its method.
The purpose of the present invention is achieved through the following technical solutions：One kind is used for the air-ground narrow-band communication system of unmanned plane
Receiving terminal, it includes Receiver Module, intermediate frequency filtering module, ADC and FPGA, and Receiver Module receives from outside
Signal of communication and the control signal from FPGA, the output of Receiver Module is connected with intermediate frequency filtering module, intermediate frequency filter
The output of ripple module is connected with ADC, and the output of ADC is connected with FPGA, and the clock control output of FPGA is connected with ADC, FPGA's
Gain control output is connected with Receiver Module, and FPGA is also by internal interface demodulated output data；
Described FPGA includes down conversion module, decimal abstraction module, thick frequency offset correction module, narrow-band filtering module, position
Synchronization module, smart frequency deviation synchronization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module, down conversion module defeated
Enter and be connected with ADC, the output of down conversion module is connected with decimal abstraction module, the output of decimal abstraction module and thick frequency offset correction
Module connects, and the output of thick frequency offset correction module is connected with narrow-band filtering module, the output of narrow-band filtering module and bit synchronization mould
Block connects, and the output of bit sync module is connected with smart frequency deviation synchronization module, the output of smart frequency deviation synchronization module with decode/adjudicate mould
Block connects, and the output of decoding/judging module is connected with de-interleaving block, and the output of de-interleaving block is with the uniform velocity buffer module even
Connect, the output of at the uniform velocity buffer module exports demodulation gain by internal interface.
Described down conversion module includes orthogonal mixting circuit, low-pass filter circuit and digital controlled oscillation circuit, orthogonal mixing
The input of circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, and orthogonal mixting circuit output I, Q two paths of signals is extremely low
Bandpass filter circuit, low-pass filter circuit output I, Q two paths of signals is to decimal abstraction module.Described digital controlled oscillation circuit uses
Cordic algorithm, only consumes a small amount of register and adder resource, does not consume RAM, resource loss is substantially negligible not
Meter.
The baseband signal that described decimal abstraction module obtains to down conversion module carries out little several times extraction, output signal sample
It is worth to thick frequency offset correction module.
Because after despreading, signal bandwidth only has 180kHz, and highest Doppler shift reaches 3kHz, in some interference feelings
Under condition, frequency deviation may be outside transnormal phaselocked loop capture zone, so here carrier synchronization partial resolution is become " thick frequency deviation
Correction " and " smart frequency deviation is synchronous " two links.
Described thick frequency offset correction module includes orthogonal mixting circuit, elimination modulation intelligence circuit, fft circuit, spectral line peak
Value search circuit, calculating frequency deviation circuit and digital controlled oscillation circuit, orthogonal mixting circuit receives from the output of decimal abstraction module
Signal, the output of orthogonal mixting circuit is connected with narrow-band filtering module and elimination modulation intelligence circuit respectively, eliminates modulation intelligence
The output of circuit is connected with fft circuit, and the output of fft circuit is connected with spectral line peak search circuit, spectral line peak search circuit
Output with calculate frequency deviation circuit is connected, calculating frequency deviation circuit output be connected with digital controlled oscillation circuit, digital controlled oscillation circuit
Output is connected with orthogonal mixting circuit.
Input signal is 4 times of symbol sampler rates, enters 4 power computing modules, eliminates the modulation intelligence of QPSK, obtains single-tone
Frequency point information.Through FFT and spectral line peak value searching, you can obtain thick frequency deviation information.Wherein the points of FFT use at 2048 points, can
To obtain sufficiently low residual frequency deviation it is ensured that the normal capture of smart frequency deviation synchronization module.After correction once, subsequently FFT obtains several times
The thick frequency deviation information arriving is close, and peak value, enough then it is assumed that having stablized, need not correct again；Otherwise it is assumed that system step-out, again enter
The thick frequency offset correction of row.
Because frequency deviation is larger, DDC, enforcement is the filtering in somewhat broadband it is ensured that signal spectrum is without damage；In thick frequency deviation school
After the completion of just, then carry out a narrow-band filtering, further filter out the out-of-band noise of remnants.Described narrow-band filtering module be used for into
One step filters the out-of-band noise of remnants.
Because the signal bandwidth of narrow band signal is less, do not use the balancing techniques such as SCFDE.
Synchronous use Gardner algorithm, insensitive to a small amount of residual frequency deviation (according to 3kHz maximum frequency deviation, 4.5Mbaud/
S about baud rate calculate, residual frequency deviation be about chip rate 0.1% about), before may be located at frequency synchronization module.Input
After data carries out little several times interpolation/extraction, obtain the signal of 4 times of symbol sampler rates；Gardner position is carried out to 4 times of sample value signals
Timing error estimate, obtains instantaneous error value, after loop filter filters high-frequency noise, drives NCO to produce timing interpolation
Enable and interpolated parameter；" Farrow timing interpolation " module uses farrow structure, and interpolation obtains accurate bit decision point,
Pass through eventually to export Buffer output；Described Farrow structure is that a kind of efficient polynomial interpolation realizes structure.
Described bit sync module include input buffer module, reg module, Timing error estimate module, loop filter,
Digital controlled oscillation circuit, timing interpolation module, output buffer module and two shift registers, the input of input buffer module with narrow
Band filtration module connects, and the output of input buffer module is connected with reg module, and the output of reg module is posted with one of displacement
Storage connects, and the output of this shift register is connected with timing interpolation module, and a road of timing interpolation module exports and another
Shift register connects, and the output of this shift register is connected with timing error module, the output of Timing error estimate module and
Loop filter connects, and the output of loop filter is connected with digital controlled oscillation circuit, and the output of digital controlled oscillation circuit is interior with timing
Slotting module connects, and another road output of timing interpolation module is by exporting buffer module output data；
Described smart frequency deviation synchronization module include orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and
Loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition numeral
Phaselocked loop, exterior I, the input of Q two-way are connected with bit sync module, and the output of orthogonal mixting circuit is electric with phase error estimation and phase error respectively
Road and decoding/judging module connect, and the output of phase error estimation and phase error circuit is connected with loop filter circuit, loop filter circuit
Output is connected with digital controlled oscillation circuit, and the output of digital controlled oscillation circuit is connected with orthogonal mixting circuit.Described numerical control vibration electricity
The realization on road uses DDS algorithm, rather than cordic algorithm, because the sequential amount of delay of cordic logic is relatively in FPGA
Greatly, lead to loop delay big, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk it is ensured that loop captures
Behavior and the performance following the tracks of behavior.
Described decoding/judging module uses Viterbi soft-decision algorithm, and described de-interleaving block is used for realizing simply
Buffering read-write.
Described at the uniform velocity buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control
Oscillation module, data buffering module receives input data and input clock, a road output and the buffering capacity prison of data buffering module
Survey module to connect, another road output output data, the output of buffering capacity monitoring modular and the loop filtering mould of data buffering module
Block connects, and the output of loop filtering module is connected with numerical control oscillation module, and a road of numerical control oscillation module exports and data buffering
Module connects, another road output clock signal of numerical control oscillation module.
Described Receiver Module includes duplexer, transmitting terminal processing module, receiving terminal processing module and drive module,
Described duplexer for receiving and sending data, the output of described transmitting terminal processing module is connected with duplexer, receiving terminal
The input of processing module is connected with duplexer, the output of drive module respectively with transmitting terminal processing module and receiving terminal processing module
Connect；
Described drive module includes crystal oscillator, local oscillator, work(sub-module, two drive amplification modules and driver, local oscillator
Two-way input is connected with crystal oscillator and SPI code respectively, and the output of local oscillator is connected with work(sub-module, and the two-way output of work(sub-module is respectively
It is connected with two drive amplification modules, the output of two drive amplification modules is processed with transmitting terminal processing module and receiving terminal respectively
Module connects, and the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drives and put
Module and power amplifier module, a road of frequency mixing module inputs as intermediate-freuqncy signal, in another road input of frequency mixing module and drive module
One of drive amplification module connect, the output of frequency mixing module is connected with filtration module, the output of filtration module and amplification
Module connects, and the output of the output of amplification module and the driver of drive module is all connected with numerical control attenuation module, numerical control attenuation
The output of module is connected with driving amplification module, and the output of drive amplification module is connected with power amplifier module, the output of power amplifier module and duplexer
Connect；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtering
Module and amplification module, the input of low noise amplification module is connected with duplexer, and the output of low noise amplification module is with filtration module even
Connect, the output of filtration module is connected with amplification module, another drive amplification module of the output of amplification module and drive module
Output be all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, and filtration module is connected with amplification module, puts
Big module output signal.
A kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane it is characterised in that：It includes following step
Suddenly：
S1：Receiver Module accepts the gain control signal from outside signal of communication and from FPGA, passes through
It is sent to intermediate frequency filtering module after conversion；
S2：Intermediate frequency filtering module carries out intermediate frequency filtering to the signal inputting from Receiver Module, and is sent to ADC；
S3：ADC receives the signal from the output of intermediate frequency filtering module, is sent to FPGA after conversion；
S4：After FPGA is processed to signal, condition data is exported by internal interface, FPGA is also to Receiver Module
Outputing gain control signal.
Described step S4 includes following sub-step：
S41：Down conversion module in FPGA carries out down-converted to the input from ADC, and exports to decimal extraction
Module；
S42：Decimal abstraction module carries out little several times extraction to the baseband signal receiving, and output signal sample value is to thick frequency deviation
Correction module；
S43：Thick frequency offset correction module carries out to the input signal of many times of symbol sampler rates obtaining thick frequency deviation information process, and
Output information is to narrow-band filtering module；
S44：Narrow-band filtering module filters the out-of-band noise of remnants, exports to bit sync module；
S45：Bit sync module carries out bit synchronization process to input signal, outputs signal to smart frequency deviation synchronization module；
S46：Smart frequency deviation synchronization module carries out carrier synchronization using digital phase-locked loop, completes basic synchronous demodulation, output
Signal is to decoding/judging module；
S47：Decoding/judging module receipt signal carries out folding coding it is ensured that the demodulation signal to noise ratio of entirety, and exports to solution
Interleaving block；Described folding coding uses Viterbi soft-decision algorithm.
S48：De-interleaving block enters row buffering read-write, afterwards by signal output at the uniform velocity buffer module；
S49：At the uniform velocity demodulating data is at the uniform velocity exported by buffer module by internal interface.
Described step S41 includes following sub-step：
S411：Orthogonal mixting circuit receives and is derived from the input of ADC and the input of digital controlled oscillation circuit, exports I, Q two-way
Signal adopts cordic algorithm to low-pass filter circuit, described digital controlled oscillation circuit；
S412：Low-pass filtering module carries out to input signal exporting to decimal abstraction module after LPF.
Described step S43 includes following sub-step：
S431：Orthogonal mixting circuit receives the many times of symbol sampler rate signals from the input of decimal abstraction module, and exports
To elimination modulation intelligence module；
S432：Eliminate modulation intelligence module and eliminate modulation intelligence, obtain single-tone frequency point information；
S433：FFT module carries out FFT to single-tone frequency point information, and exports to spectral line peak value searching mould
Block；
S434：Spectral line peak value searching module carries out peak value searching, obtains thick frequency deviation information, and exports to calculating frequency deviation mould
Block；
S435：Calculate frequency deviation module thick frequency deviation information is calculated, judge whether that needs proceed to correct：
（1）If the follow-up thick frequency deviation message that FFT obtains several times is close, peak value enough, then result is sequentially output to numerical control
After oscillation module and orthogonal frequency mixing module, it is directly output to narrow-band filtering module；
（2）It is believed that system step-out in the case of other, result is sequentially output to numerical control oscillation module, orthogonal frequency mixing module
With return to step S432 after elimination modulation intelligence module.
Described step S45 includes following sub-step：
S451：Gardner bit timing estimation error will be carried out from narrow-band filtering module input data, obtain instantaneous error
Value；
S452：Loop filter filters high-frequency noise；
S453：Drive digital controlled oscillation circuit to produce timing interpolation to enable and interpolated parameter；
S454：Interpolation is timed to data, obtains accurate bit decision point；
S455：By output buffer output result to frequency deviation synchronization module.
Described step S46 includes following sub-step：
S461：Orthogonal mixting circuit carries out orthogonal mixing to from bit sync module input signal, outputs signal to phase place by mistake
Difference estimating circuit；
S462：Phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit；
S463：Loop filter circuit is filtered, and exports to digital controlled oscillation circuit；
S464：Digital controlled oscillation circuit outputs signal to orthogonal mixting circuit, and described digital controlled oscillation circuit adopts DDS to calculate
Method；
S465：Orthogonal mixting circuit outputs signal to decoding/judging module.
Described step S49 includes following sub-step：
S491：Data buffering module receives the data and clock from de-interleaving block input, outputs signal to buffering capacity
Detection module；
S492：Buffering capacity detection module is monitored to the buffering capacity of data buffer module, outputs signal to loop simultaneously
Filtration module；
S493：After loop filtering module is filtered, output signal to numerical control oscillation module；
S494：Numerical control oscillation module has two-way to export, a road output clock, a road output signal control data buffering mould
Block；
S495：Data buffering module output data.
The invention has the beneficial effects as follows：（1）The signal of ADC input obtains baseband signal through down coversion, in down coversion
Digital controlled oscillation circuit is realized using cordic algorithm, only consumes a small amount of register and adder resource, does not consume RAM, resource
Loss is substantially negligible to be disregarded；（2）Baseband signal carries out little several times extraction, obtains the signal sample of 4 times of chip rates, then
Carry out matched filtering, advantage of this is that the calculating beneficial to matched filtering coefficient；（3）Because after despreading, signal bandwidth only has
180kHz about, and highest Doppler shift reaches 3kHz, at certain interference situations., frequency deviation may transnormal phaselocked loop
Outside capture zone, so here carrier synchronization partial resolution is become " thick frequency offset correction " and " smart frequency deviation is synchronous " two links；（4）
Because frequency deviation is larger, DDC, enforcement is the filtering in somewhat broadband it is ensured that signal spectrum is without damage；（5）Complete in thick frequency offset correction
Cheng Hou, then carry out a narrow-band filtering, further filter out the out-of-band noise of remnants；（6）The signal bandwidth of narrow band signal is less, no
Reuse the balancing techniques such as SCFDE, cost-effective；（7）Bit information after judgement, through channel decoding, obtains the knot after error correction
Really, in order to support the precise time label of remote measurement, demodulating data will at the uniform velocity be exported；（8）Due to above some, the present invention just can fit
For a kind of can the receiving terminal of air-ground narrow-band communication system of unmanned plane that passes of remote measurement, remote control, number and its method, receiving terminal
Including unmanned plane terminal.
Brief description
Fig. 1 is present configuration block diagram；
Fig. 2 is FPGA function module structure chart；
Fig. 3 is down conversion module structure chart；
Fig. 4 is thick frequency offset correction function structure chart；
Fig. 5 is bit sync module structure chart；
Fig. 6 is Farrow structured flowchart；
Fig. 7 is smart frequency deviation synchronization structure figure；
Fig. 8 is at the uniform velocity buffer module structure chart；
Fig. 9 is radio frequency receiving block structural diagram；
Figure 10 is the inventive method flow chart.
Specific embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings：As shown in figure 1, a kind of be used for unmanned plane ground
The receiving terminal of empty narrow-band communication system, it includes Receiver Module, intermediate frequency filtering module, ADC and FPGA, radio frequency receiving
Block receives the control signal from outside signal of communication and from FPGA, the output of Receiver Module and intermediate frequency filtering mould
Block connects, and the output of intermediate frequency filtering module is connected with ADC, and the output of ADC is connected with FPGA, the clock control of FPGA export and
ADC connects, and the gain control output of FPGA is connected with Receiver Module, and FPGA is also by internal interface demodulated output data；
As shown in Fig. 2 described FPGA includes down conversion module, decimal abstraction module, thick frequency offset correction module, arrowband filter
Ripple module, bit sync module, smart frequency deviation synchronization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module, lower change
The input of frequency module is connected with ADC, and the output of down conversion module is connected with decimal abstraction module, the output of decimal abstraction module with
Thick frequency offset correction module connects, and the output of thick frequency offset correction module is connected with narrow-band filtering module, the output of narrow-band filtering module
Be connected with bit sync module, the output of bit sync module is connected with smart frequency deviation synchronization module, the output of smart frequency deviation synchronization module and
Decoding/judging module connects, and the output of decoding/judging module is connected with de-interleaving block, the output of de-interleaving block and at the uniform velocity
Buffer module connects, and the output of at the uniform velocity buffer module exports demodulation gain by internal interface.
As shown in figure 3, described down conversion module includes orthogonal mixting circuit, low-pass filter circuit and numerical control vibration electricity
Road, the input of orthogonal mixting circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, and orthogonal mixting circuit exports I, Q
, to low-pass filter circuit, low-pass filter circuit output I, Q two paths of signals is to decimal abstraction module for two paths of signals.Described numerical control is shaken
Swing circuit and use cordic algorithm, only consume a small amount of register and adder resource, do not consume RAM, resource loss is substantially
It is negligible.
The baseband signal that described decimal abstraction module obtains to down conversion module carries out little several times extraction, output signal sample
It is worth to thick frequency offset correction module.
Because after despreading, signal bandwidth only has 180kHz, and highest Doppler shift reaches 3kHz, in some interference feelings
Under condition, frequency deviation may be outside transnormal phaselocked loop capture zone, so here carrier synchronization partial resolution is become " thick frequency deviation
Correction " and " smart frequency deviation is synchronous " two links.
As shown in figure 4, described thick frequency offset correction module includes orthogonal mixting circuit, elimination modulation intelligence circuit, FFT electricity
Road, spectral line peak search circuit, calculating frequency deviation circuit and digital controlled oscillation circuit, orthogonal mixting circuit receives and extracts mould from decimal
The signal of block output, the output of orthogonal mixting circuit is connected with narrow-band filtering module and elimination modulation intelligence circuit respectively, eliminates
The output of modulation intelligence circuit is connected with fft circuit, and the output of fft circuit is connected with spectral line peak search circuit, spectral line peak value
The output of search circuit is connected with calculating frequency deviation circuit, and the output calculating frequency deviation circuit is connected with digital controlled oscillation circuit, and numerical control is shaken
The output swinging circuit is connected with orthogonal mixting circuit.
Input signal is 4 times of symbol sampler rates, enters 4 power computing modules, eliminates the modulation intelligence of QPSK, obtains single-tone
Frequency point information.Through FFT and spectral line peak value searching, you can obtain thick frequency deviation information.Wherein the points of FFT use at 2048 points, can
To obtain sufficiently low residual frequency deviation it is ensured that the normal capture of smart frequency deviation synchronization module.After correction once, subsequently FFT obtains several times
The thick frequency deviation information arriving is close, and peak value, enough then it is assumed that having stablized, need not correct again；Otherwise it is assumed that system step-out, again enter
The thick frequency offset correction of row.
Because frequency deviation is larger, DDC, enforcement is the filtering in somewhat broadband it is ensured that signal spectrum is without damage；In thick frequency deviation school
After the completion of just, then carry out a narrow-band filtering, further filter out the out-of-band noise of remnants.Described narrow-band filtering module be used for into
One step filters the out-of-band noise of remnants.
Because the signal bandwidth of narrow band signal is less, do not use the balancing techniques such as SCFDE.
Synchronous use Gardner algorithm, insensitive to a small amount of residual frequency deviation (according to 3kHz maximum frequency deviation, 4.5Mbaud/
S about baud rate calculate, residual frequency deviation be about chip rate 0.1% about), before may be located at frequency synchronization module.Input
After data carries out little several times interpolation/extraction, obtain the signal of 4 times of symbol sampler rates；Gardner position is carried out to 4 times of sample value signals
Timing error estimate, obtains instantaneous error value, after loop filter filters high-frequency noise, drives NCO to produce timing interpolation
Enable and interpolated parameter；" Farrow timing interpolation " module uses farrow structure, and interpolation obtains accurate bit decision point,
Pass through eventually to export Buffer output；As shown in fig. 6, described Farrow structure is a kind of efficient polynomial interpolation realizes structure.
As shown in figure 5, described bit sync module include input buffer module, reg module, Timing error estimate module,
Loop filter, digital controlled oscillation circuit, timing interpolation module, output buffer module and two shift registers, input buffering mould
The input of block is connected with narrow-band filtering module, input buffer module output be connected with reg module, the output of reg module and its
In shift register connect, the output of this shift register is connected with timing interpolation module, a road of timing interpolation module
Output is connected with another shift register, and the output of this shift register is connected with timing error module, Timing error estimate
The output of module is connected with loop filter, and the output of loop filter is connected with digital controlled oscillation circuit, digital controlled oscillation circuit
Output is connected with timing interpolation module, and another road output of timing interpolation module is by exporting buffer module output data；
As shown in fig. 7, described smart frequency deviation synchronization module includes orthogonal mixting circuit, digital controlled oscillation circuit, phase error
Estimating circuit and loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filtering electricity
Road forms digital phase-locked loop, and exterior I, the input of Q two-way are connected with bit sync module, the output of orthogonal mixting circuit respectively with phase place
Error estimation circuit and decoding/judging module connect, and the output of phase error estimation and phase error circuit is connected with loop filter circuit, loop
The output of filter circuit is connected with digital controlled oscillation circuit, and the output of digital controlled oscillation circuit is connected with orthogonal mixting circuit.Described
The realization of digital controlled oscillation circuit uses DDS algorithm, rather than cordic algorithm because in FPGA cordic logic sequential
Amount of delay is larger, leads to loop delay big, affects capturing frequency deviation ability, and DDS only have 1 to 3 clk time delay it is ensured that
Loop capturing behavior and the performance following the tracks of behavior.
Described decoding/judging module uses Viterbi soft-decision algorithm, and described de-interleaving block is used for realizing simply
Buffering read-write.
As shown in figure 8, described at the uniform velocity buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering
Module and numerical control oscillation module, data buffering module receives input data and input clock, a road output of data buffering module
Be connected with buffering capacity monitoring modular, another road output output data of data buffering module, the output of buffering capacity monitoring modular with
Loop filtering module connects, and the output of loop filtering module is connected with numerical control oscillation module, a road output of numerical control oscillation module
It is connected with data buffering module, another road output clock signal of numerical control oscillation module.
As shown in figure 9, described Receiver Module includes duplexer, transmitting terminal processing module, receiving terminal processing module
And drive module, described duplexer for receiving and sending data, the described output of transmitting terminal processing module and duplexer
Connect, the input of receiving terminal processing module is connected with duplexer, the output of drive module respectively with transmitting terminal processing module and connecing
Receiving end processing module connects；
Described drive module includes crystal oscillator, local oscillator, work(sub-module, two drive amplification modules and driver, local oscillator
Two-way input is connected with crystal oscillator and SPI code respectively, and the output of local oscillator is connected with work(sub-module, and the two-way output of work(sub-module is respectively
It is connected with two drive amplification modules, the output of two drive amplification modules is processed with transmitting terminal processing module and receiving terminal respectively
Module connects, and the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drives and put
Module and power amplifier module, a road of frequency mixing module inputs as intermediate-freuqncy signal, in another road input of frequency mixing module and drive module
One of drive amplification module connect, the output of frequency mixing module is connected with filtration module, the output of filtration module and amplification
Module connects, and the output of the output of amplification module and the driver of drive module is all connected with numerical control attenuation module, numerical control attenuation
The output of module is connected with driving amplification module, and the output of drive amplification module is connected with power amplifier module, the output of power amplifier module and duplexer
Connect；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtering
Module and amplification module, the input of low noise amplification module is connected with duplexer, and the output of low noise amplification module is with filtration module even
Connect, the output of filtration module is connected with amplification module, another drive amplification module of the output of amplification module and drive module
Output be all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, and filtration module is connected with amplification module, puts
Big module output signal.
As shown in Figure 10, a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane it is characterised in that：It
Comprise the following steps：
S1：Receiver Module accepts the gain control signal from outside signal of communication and from FPGA, passes through
It is sent to intermediate frequency filtering module after conversion；
S2：Intermediate frequency filtering module carries out intermediate frequency filtering to the signal inputting from Receiver Module, and is sent to ADC；
S3：ADC receives the signal from the output of intermediate frequency filtering module, is sent to FPGA after conversion；
S4：After FPGA is processed to signal, condition data is exported by internal interface, FPGA is also to Receiver Module
Outputing gain control signal.
Described step S4 includes following sub-step：
S41：Down conversion module in FPGA carries out down-converted to the input from ADC, and exports to decimal extraction
Module；
S42：Decimal abstraction module carries out little several times extraction to the baseband signal receiving, and output signal sample value is to thick frequency deviation
Correction module；
S43：Thick frequency offset correction module carries out to the input signal of many times of symbol sampler rates obtaining thick frequency deviation information process, and
Output information is to narrow-band filtering module；
S44：Narrow-band filtering module filters the out-of-band noise of remnants, exports to bit sync module；
S45：Bit sync module carries out bit synchronization process to input signal, outputs signal to smart frequency deviation synchronization module；
S46：Smart frequency deviation synchronization module carries out carrier synchronization using digital phase-locked loop, completes basic synchronous demodulation, output
Signal is to decoding/judging module；
S47：Decoding/judging module receipt signal carries out folding coding it is ensured that the demodulation signal to noise ratio of entirety, and exports to solution
Interleaving block；Described folding coding uses Viterbi soft-decision algorithm.
S48：De-interleaving block enters row buffering read-write, afterwards by signal output at the uniform velocity buffer module；
S49：At the uniform velocity demodulating data is at the uniform velocity exported by buffer module by internal interface.
Described step S41 includes following sub-step：
S411：Orthogonal mixting circuit receives and is derived from the input of ADC and the input of digital controlled oscillation circuit, exports I, Q two-way
Signal adopts cordic algorithm to low-pass filter circuit, described digital controlled oscillation circuit；
S412：Low-pass filtering module carries out to input signal exporting to decimal abstraction module after LPF.
Described step S43 includes following sub-step：
S431：Orthogonal mixting circuit receives the many times of symbol sampler rate signals from the input of decimal abstraction module, and exports
To elimination modulation intelligence module；
S432：Eliminate modulation intelligence module and eliminate modulation intelligence, obtain single-tone frequency point information；
S433：FFT module carries out FFT to single-tone frequency point information, and exports to spectral line peak value searching mould
Block；
S434：Spectral line peak value searching module carries out peak value searching, obtains thick frequency deviation information, and exports to calculating frequency deviation mould
Block；
S435：Calculate frequency deviation module thick frequency deviation information is calculated, judge whether that needs proceed to correct：
（1）If the follow-up thick frequency deviation message that FFT obtains several times is close, peak value enough, then result is sequentially output to numerical control
After oscillation module and orthogonal frequency mixing module, it is directly output to narrow-band filtering module；
（2）It is believed that system step-out in the case of other, result is sequentially output to numerical control oscillation module, orthogonal frequency mixing module
With return to step S432 after elimination modulation intelligence module.
Described step S45 includes following sub-step：
S451：Gardner bit timing estimation error will be carried out from narrow-band filtering module input data, obtain instantaneous error
Value；
S452：Loop filter filters high-frequency noise；
S453：Drive digital controlled oscillation circuit to produce timing interpolation to enable and interpolated parameter；
S454：Interpolation is timed to data, obtains accurate bit decision point；
S455：By output buffer output result to frequency deviation synchronization module.
Described step S46 includes following sub-step：
S461：Orthogonal mixting circuit carries out orthogonal mixing to from bit sync module input signal, outputs signal to phase place by mistake
Difference estimating circuit；
S462：Phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit；
S463：Loop filter circuit is filtered, and exports to digital controlled oscillation circuit；
S464：Digital controlled oscillation circuit outputs signal to orthogonal mixting circuit, and described digital controlled oscillation circuit adopts DDS to calculate
Method；
S465：Orthogonal mixting circuit outputs signal to decoding/judging module.
Described step S49 includes following sub-step：
S491：Data buffering module receives the data and clock from de-interleaving block input, outputs signal to buffering capacity
Detection module；
S492：Buffering capacity detection module is monitored to the buffering capacity of data buffer module, outputs signal to loop simultaneously
Filtration module；
S493：After loop filtering module is filtered, output signal to numerical control oscillation module；
S494：Numerical control oscillation module has two-way to export, a road output clock, a road output signal control data buffering mould
Block；
S495：Data buffering module output data.
Claims (8)
1. a kind of receiving terminal for the air-ground narrow-band communication system of unmanned plane it is characterised in that：It include Receiver Module,
Intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the control letter from outside signal of communication and from FPGA
Number, the output of Receiver Module is connected with intermediate frequency filtering module, and the output of intermediate frequency filtering module is connected with ADC, the output of ADC
It is connected with FPGA, the clock control output of FPGA is connected with ADC, the gain control output of FPGA is connected with Receiver Module,
FPGA is also by internal interface demodulated output data；
Described FPGA includes down conversion module, decimal abstraction module, thick frequency offset correction module, narrow-band filtering module, bit synchronization
Module, smart frequency deviation synchronization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module, the input of down conversion module and
ADC connects, and the output of down conversion module is connected with decimal abstraction module, the output of decimal abstraction module and thick frequency offset correction module
Connect, the output of thick frequency offset correction module is connected with narrow-band filtering module, the output of narrow-band filtering module is with bit sync module even
Connect, the output of bit sync module is connected with smart frequency deviation synchronization module, the output of smart frequency deviation synchronization module is with decoding/judging module even
Connect, the output of decoding/judging module is connected with de-interleaving block, the output of de-interleaving block is connected with the uniform velocity buffer module, even
The output of fast buffer module exports demodulation gain by internal interface；
Described down conversion module includes the first orthogonal mixting circuit, low-pass filter circuit and the first digital controlled oscillation circuit, and first
The input of orthogonal mixting circuit is connected with ADC input signal and the first digital controlled oscillation circuit respectively, and the first orthogonal mixting circuit is defeated
Go out I, Q two paths of signals to low-pass filter circuit, low-pass filter circuit output I, Q two paths of signals is to decimal abstraction module, described
First digital controlled oscillation circuit uses cordic algorithm；
Described thick frequency offset correction module includes the second orthogonal mixting circuit, elimination modulation intelligence circuit, fft circuit, spectral line peak
Value search circuit, calculating frequency deviation circuit and the second digital controlled oscillation circuit, the second orthogonal mixting circuit receives and extracts mould from decimal
The signal of block output, the output of the second orthogonal mixting circuit is connected with narrow-band filtering module and elimination modulation intelligence circuit respectively,
The output eliminating modulation intelligence circuit is connected with fft circuit, and the output of fft circuit is connected with spectral line peak search circuit, spectral line
The output of peak search circuit is connected with calculating frequency deviation circuit, calculates the output of frequency deviation circuit with the second digital controlled oscillation circuit even
Connect, the output of the second digital controlled oscillation circuit is connected with orthogonal mixting circuit；
Described bit sync module include input buffer module, reg module, Timing error estimate module, loop filter, the 3rd
Digital controlled oscillation circuit, timing interpolation module, output buffer module and two shift registers, the input of input buffer module with narrow
Band filtration module connects, and the output of input buffer module is connected with reg module, and the output of reg module is posted with one of displacement
Storage connects, and the output of this shift register is connected with timing interpolation module, and a road of timing interpolation module exports and another
Shift register connects, and the output of this shift register is connected with timing error module, the output of Timing error estimate module and
Loop filter connects, and the output of loop filter is connected with the 3rd digital controlled oscillation circuit, the output of the 3rd digital controlled oscillation circuit
It is connected with timing interpolation module, another road output of timing interpolation module is by exporting buffer module output data；
Described smart frequency deviation synchronization module includes the 4th orthogonal mixting circuit, the 4th digital controlled oscillation circuit, phase error estimation and phase error electricity
Road and loop filter circuit, the 4th orthogonal mixting circuit, the 4th digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filtering
Circuit forms digital phase-locked loop, and exterior I, the input of Q two-way are connected with bit sync module, and the output of the 4th orthogonal mixting circuit is respectively
It is connected with phase error estimation and phase error circuit and decoding/judging module, the output of phase error estimation and phase error circuit is with loop filter circuit even
Connect, the output of loop filter circuit is connected with the 4th digital controlled oscillation circuit, the output of the 4th digital controlled oscillation circuit is orthogonal with the 4th
Mixting circuit connects, the practical DDS algorithm of the 4th described digital controlled oscillation circuit；
Described at the uniform velocity buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and the 5th numerical control
Oscillation module, data buffering module receives input data and input clock, a road output and the buffering capacity prison of data buffering module
Survey module to connect, another road output output data, the output of buffering capacity monitoring modular and the loop filtering mould of data buffering module
Block connects, and the output of loop filtering module is connected with the 5th numerical control oscillation module, a road of the 5th numerical control oscillation module export and
Data buffering module connects, another road output clock signal of the 5th numerical control oscillation module.
2. a kind of receiving terminal for the air-ground narrow-band communication system of unmanned plane according to claim 1 it is characterised in that：
Described Receiver Module includes duplexer, transmitting terminal processing module, receiving terminal processing module and drive module, described duplex
Device for receiving and sending data, the output of described transmitting terminal processing module is connected with duplexer, receiving terminal processing module
Input be connected with duplexer, the output of drive module is connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described drive module includes crystal oscillator, local oscillator, work(sub-module, two drive amplification modules and driver, the two-way of local oscillator
Input is connected with crystal oscillator and SPI code respectively, and the output of local oscillator is connected with work(sub-module, and the two-way of work(sub-module exports respectively with two
Individual drive amplification module connects, the output of two drive amplification modules respectively with transmitting terminal processing module and receiving terminal processing module
Connect, the output of driver is connected with transmitting terminal processing module, described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module include frequency mixing module, the first filtration module, the first amplification module, numerical control attenuation module,
Drive amplification module and power amplifier module, a road of frequency mixing module inputs as intermediate-freuqncy signal, another road input of frequency mixing module and driving mould
One of drive amplification module in block connects, and the output of frequency mixing module is connected with the first filtration module, the first filtration module
Output be connected with the first amplification module, the output of the output of the first amplification module and the driver of drive module is all declined with numerical control
Subtract module to connect, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, power amplifier
The output of module is connected with duplexer；
Described receiving terminal processing module include low noise amplification module, the second filtration module, the second amplification module, frequency mixing module,
3rd filtration module and the 3rd amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module
Be connected with the second filtration module, the output of the second filtration module is connected with the second amplification module, the output of the second amplification module and
The output of another drive amplification module of drive module is all connected with frequency mixing module, and the output of frequency mixing module filters mould with the 3rd
Block connects, and the 3rd filtration module is connected with the 3rd amplification module, the 3rd amplification module output signal.
3. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane it is characterised in that：It comprises the following steps：
S1：Receiver Module accepts the gain control signal from outside signal of communication and from FPGA, through conversion
It is sent to intermediate frequency filtering module afterwards；
S2：Intermediate frequency filtering module carries out intermediate frequency filtering to the signal inputting from Receiver Module, and is sent to ADC；
S3：ADC receives the signal from the output of intermediate frequency filtering module, is sent to FPGA after conversion；
S4：After FPGA is processed to signal, condition data is exported by internal interface, FPGA also exports to Receiver Module
Gain control signal；
Described step S4 includes following sub-step：
S41：Down conversion module in FPGA carries out down-converted to the input from ADC, and exports to decimal abstraction module；
S42：Decimal abstraction module carries out little several times extraction to the baseband signal receiving, and output signal sample value is to thick frequency offset correction
Module；
S43：Thick frequency offset correction module carries out to the input signal of many times of symbol sampler rates obtaining thick frequency deviation information process, and exports
Information is to narrow-band filtering module；
S44：Narrow-band filtering module filters the out-of-band noise of remnants, exports to bit sync module；
S45：Bit sync module carries out bit synchronization process to input signal, outputs signal to smart frequency deviation synchronization module；
S46：Smart frequency deviation synchronization module carries out carrier synchronization using digital phase-locked loop, completes basic synchronous demodulation, output signal
To decoding/judging module；
S47：Decoding/judging module receipt signal carries out folding coding it is ensured that the demodulation signal to noise ratio of entirety, and exports to deinterleaving
Module；Described folding coding uses Viterbi soft-decision algorithm；
S48：De-interleaving block enters row buffering read-write, afterwards by signal output at the uniform velocity buffer module；
S49：At the uniform velocity demodulating data is at the uniform velocity exported by buffer module by internal interface.
4. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 3, its feature
It is：Described step S41 includes following sub-step：
S411：First orthogonal mixting circuit receives and is derived from the input of ADC and the input of the first digital controlled oscillation circuit, exports I, Q
Two paths of signals adopts cordic algorithm to low-pass filter circuit, the first described digital controlled oscillation circuit；
S412：Low-pass filtering module carries out to input signal exporting to decimal abstraction module after LPF.
5. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 3, its feature
It is：Described step S43 includes following sub-step：
S431：Second orthogonal mixting circuit receives the many times of symbol sampler rate signals from the input of decimal abstraction module, and exports
To elimination modulation intelligence module；
S432：Eliminate modulation intelligence module and eliminate modulation intelligence, obtain single-tone frequency point information；
S433：FFT module carries out FFT to single-tone frequency point information, and exports to spectral line peak value searching module；
S434：Spectral line peak value searching module carries out peak value searching, obtains thick frequency deviation information, and exports to calculating frequency deviation module；
S435：Calculate frequency deviation module thick frequency deviation information is calculated, judge whether that needs proceed to correct：
（1）If the follow-up thick frequency deviation message that FFT obtains several times is close, peak value enough, then result is sequentially output to the second numerical control
After oscillation module and the second orthogonal frequency mixing module, it is directly output to narrow-band filtering module；
（2）It is believed that system step-out in the case of other, result is sequentially output to the second numerical control oscillation module, the second orthogonal mixing
Return to step S432 after module and elimination modulation intelligence module.
6. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 3, its feature
It is：Described step S45 includes following sub-step：
S451：Gardner bit timing estimation error will be carried out from narrow-band filtering module input data, obtain instantaneous error value；
S452：Loop filter filters high-frequency noise；
S453：Drive the 3rd digital controlled oscillation circuit to produce timing interpolation to enable and interpolated parameter；
S454：Interpolation is timed to data, obtains accurate bit decision point；
S455：By output buffer output result to frequency deviation synchronization module.
7. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 3, its feature
It is：Described step S46 includes following sub-step：
S461：4th orthogonal mixting circuit carries out orthogonal mixing to from bit sync module input signal, outputs signal to phase place by mistake
Difference estimating circuit；
S462：Phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit；
S463：Loop filter circuit is filtered, and exports to the 4th digital controlled oscillation circuit；
S464：4th digital controlled oscillation circuit outputs signal to the 4th orthogonal mixting circuit, and the 4th described digital controlled oscillation circuit is adopted
Use DDS algorithm；
S465：4th orthogonal mixting circuit outputs signal to decoding/judging module.
8. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 3, its feature
It is：Described step S49 includes following sub-step：
S491：Data buffering module receives the data and clock from de-interleaving block input, outputs signal to buffering capacity detection
Module；
S492：Buffering capacity detection module is monitored to the buffering capacity of data buffer module, outputs signal to loop filtering simultaneously
Module；
S493：After loop filtering module is filtered, output signal to the 5th numerical control oscillation module；
S494：5th numerical control oscillation module has two-way to export, a road output clock, a road output signal control data buffering mould
Block；
S495：Data buffering module output data.
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