CN204180063U - A kind of receiving terminal for unmanned plane ground-to-air wideband communication system - Google Patents
A kind of receiving terminal for unmanned plane ground-to-air wideband communication system Download PDFInfo
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- CN204180063U CN204180063U CN201420718515.0U CN201420718515U CN204180063U CN 204180063 U CN204180063 U CN 204180063U CN 201420718515 U CN201420718515 U CN 201420718515U CN 204180063 U CN204180063 U CN 204180063U
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Abstract
The utility model discloses a kind of receiving terminal for unmanned plane ground-to-air wideband communication system, it comprises Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receiving communication signal and the control signal from FPGA, the output of Receiver Module and intermediate frequency filtering model calling, the output of intermediate frequency filtering module is connected by ADC and FPGA, the gain of FPGA controls to export and is connected with Receiver Module, FPGA is demodulated output data also, described FPGA comprises down conversion module, AGC control module, decimal abstraction module, matched filtering module, bit synchronization module, frequency deviation synchronization module, frequency domain equalization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module.The utility model to can remote measurement, remote control, number pass unmanned plane system in air-ground wideband signal communication subsystem carry out perfect, be applicable to handheld terminal and the car-mounted terminal on ground simultaneously.
Description
Technical field
The utility model relates to a kind of receiving terminal for unmanned plane ground-to-air wideband communication system.
Background technology
Unmanned plane has that cost effectiveness is low, zero injures and deaths and dispose the advantages such as flexible, can help or even replace the mankind to play a role in a lot of scene, as personnel's search and rescue, infrastructure supervision etc. after calamity.No matter in civilian or military domain, unmanned plane all has wide application and development prospect.
The system of unmanned plane that passes of remote measurement, remote control, number can comprise Air-Ground two-way communication and ground-ground two-way communication two parts, divide according to wire data type, wideband signal communication can be divided into communicate with narrow band signal two types, wherein broadband signal is unmanned plane reconnaissance image data transmission service and unmanned plane telemetry service, narrow band signal is underwater acoustic remote control business between handheld terminal and unmanned plane, communication service between handheld terminal and car-mounted terminal.And a link very important in broadband connections is exactly its receiving terminal, receiving terminal comprises handheld terminal and car-mounted terminal.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, provides a kind of for can the receiving terminal of ground-to-air wideband communication system of unmanned plane that passes of remote measurement, remote control, number, high to the handling property of signal.
The purpose of this utility model is achieved through the following technical solutions: a kind of receiving terminal for unmanned plane ground-to-air wideband communication system comprises Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the signal of communication from outside and the control signal from FPGA, the output of Receiver Module and intermediate frequency filtering model calling, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control of FPGA exports and is connected with ADC, the gain of FPGA controls to export and is connected with Receiver Module, FPGA is also by internal interface demodulated output data, the size that intermediate frequency filtering module receives from the signal of Receiver Module is 160MHz, be 30db by the gain control range of FPGA radio frequency receiver module,
Described FPGA comprises down conversion module, AGC control module, decimal abstraction module, matched filtering module, bit synchronization module, frequency deviation synchronization module, frequency domain equalization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module, the input of down conversion module is connected with ADC, the output of down conversion module is connected with AGC control module, the gain of AGC control module controls to export to divide and is connected with Receiver Module, the conciliation output of AGC control module is connected with decimal abstraction module, the output of decimal abstraction module and matched filtering model calling, the output of matched filtering module and bit synchronization model calling, the output of bit synchronization module is connected with frequency deviation synchronization module, the output of frequency deviation synchronization module and frequency domain equalization model calling, the output of frequency domain equalization module is connected with decoding/judging module, the output of decoding/judging module is connected with de-interleaving block, the output of de-interleaving block is connected with at the uniform velocity buffer module, at the uniform velocity the output of buffer module is exported by internal interface and reconciles gain.
Described down conversion module comprises quadrature downconvert circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of quadrature downconvert circuit is connected with external input signal and digital controlled oscillation circuit respectively, quadrature downconvert circuit exports I, Q two paths of signals to low-pass filter circuit, and low-pass filter circuit exports I, Q two paths of signals to AGC control module.Digital controlled oscillation circuit uses cordic algorithm to realize, and only consume a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible.
Described AGC control module exports AGC gain control signal to Receiver Module, and AGC control module also exports baseband signal to decimal abstraction module.Because native system is that non-high-speed is cruised, so the change of signal power is relatively slower, judge to return the received power control overflow that the circuit structure controlling radio frequency can meet native system again by FPGA.
Described decimal abstraction module carries out little several times extraction to the baseband signal that down-conversion and AGC control to obtain, and output signal sample value is to matched filtering module.
Described bit synchronization module comprises input buffer module, reg module, Timing error estimate module, loop filter, digital controlled oscillation circuit, timing interpose module, export buffer module and two shift registers, the input of input buffer module and matched filtering model calling, the output of input buffer module and reg model calling, the output of reg module is connected with one of them shift register, the output of this shift register is connected with timing interpose module, one tunnel of timing interpose module exports and is connected with another shift register, the output of this shift register and timing error model calling, the output of Timing error estimate module is connected with loop filter, the output of loop filter is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with timing interpose module, another road of timing interpose module exports and exports data by exporting buffer module.Bit synchronization uses Gardner algorithm, to a small amount of residual frequency deviation insensitive (according to 3kHz maximum frequency deviation, about 4.5Mbaud/s baud rate is calculated, and residual frequency deviation is approximately about 0.1% of chip rate), before can being positioned at frequency synchronization module.After input data carry out the interpolation/extraction of little several times, obtain the signal of 4 times of symbol sampler rates; Carry out gardner bit timing estimation error to 4 times of sample value signals, obtain instantaneous error value, after loop filter filter away high frequency noise, driving N CO produces the enable and interpolated parameter of timing interpolation; " Farrow timing interpolation " module uses farrow structure, and interpolation obtains bit decision point accurately, eventually through output Buffer output; Described Farrow structure is a kind of polynomial interpolation implementation structure efficiently.
Described frequency deviation synchronization module is smart frequency offset tracking module, described frequency deviation synchronization module comprises quadrature downconvert circuit, NCO circuit, phase error estimation and phase error circuit and loop filter circuit, quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way is connected with quadrature downconvert circuit, the output of quadrature downconvert circuit is connected with phase error estimation and phase error circuit and frequency domain equalization circuit respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with quadrature downconvert circuit, the realization of described digital controlled oscillation circuit uses DDS algorithm, instead of cordic algorithm, because the sequential amount of delay of cordic logic is larger in FPGA, cause loop delay large, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, the performance of loop capturing behavior and tracking behavior can be ensured.
Frequency domain equalization adopts single-carrier wave frequency domain equalization technology, converts the signal into frequency domain and carries out channel estimating and equilibrium, switches back to time domain again after equilibrium is complete, described frequency domain equalization module comprises three FFT modules and FFT1, FFT2 and FFT3, two IFFT modules and IFFT1 and IFFT2, unique word search module, channel estimation module, local unique word module, mend 0 module and channel equalization module, input signal is connected with FFT1 and unique word search module respectively, the output of local keyword module is connected with FFT2, unique word search module, the output of FFT1 with FFT2 is connected with channel estimation module, the output of channel estimation module is connected with IFFT1, output and benefit 0 model calling of IFFT1, mend output and the FFT3 model calling of 0 module, the output of FFT1 with FFT3 is connected with channel equalization module, channel equalization module is connected with IFFT2, IFFT2 outputs signal.
For down link, count channel error correction, frame structure loss etc. in, information rate is higher, reaches about 10Mbps, multidiameter more than ten code elements, so should channel equalization be considered.If use traditional single carrier wave time domain balanced, when the number of symbols that multipath delay exceedes is more, the exponent number taking out sef-adapting filter can be caused excessive, thus computing is complicated and affect the sequential handling capacity of logical circuit.Native system adopts up-to-date channel equalization technique SCFDE (single carrier frequency domain equalization) solving multipath interference.SCFDE and OFDM(OFDM) be all carry out channel estimating and equilibrium on frequency domain, balanced compared to traditional single carrier wave time domain, there is higher computational efficiency and equalization performance, become the focus of current communication system, and as the balancing technique scheme that IEEE802.16 with 4G communicates.And SCFDE is compared to OFDM, there is following advantage: (1) SCFDE can overcome the too high problem of OFDM technology PAR (papr), thus transmitting terminal can use the RF power amplifier of low cost; (2) SCFDE can overcome OFDM technology to the more sensitive weakness of deviation ratio, more reliable than OFDM in high-speed aircraft communication; (3) although SCFDE and OFDM is signal link operational model similar (existing IFFT and FFT), but the IFFT of OFDM is placed on transmitting terminal, and IFFT and FFT of SCFDE is at receiving terminal, such air carrier can consume less hardware resource as transmitting terminal, for very beneficial the miniaturization of transmitting terminal and optimised power consumption.(4) SCFDE is not when using chnnel coding, can be subject to the damage of frequency selective fading unlike OFDM.
Described decoding/judging module uses Viterbi soft-decision algorithm, and described de-interleaving block simply cushions read-write for realizing.
Described at the uniform velocity buffer module comprises data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel of data buffering module exports and is connected with buffering capacity monitoring modular, another road of data buffering module exports data, the output of buffering capacity monitoring modular and loop filtering model calling, the output of loop filtering module is connected with numerical control oscillation module, one tunnel of numerical control oscillation module exports and data buffering model calling, and another road of numerical control oscillation module exports output clock.
Described Receiver Module comprises duplexer, transmitting terminal processing module, receiving terminal processing module and driver module, described duplexer is used for receiving and sending data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, and the output of driver module is connected with transmitting terminal processing module and receiving terminal processing module respectively;
Described driver module comprises crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, described local oscillator needs SPI code to control, described driver exports 5 parallel-by-bit control codes, the output of crystal oscillator is connected with local oscillator, the output of local oscillator is connected with merit sub-module, the two-way of merit sub-module export respectively with two drive amplification model calling, two drive amplification modules are connected with transmitting terminal processing module and receiving terminal processing module respectively, and driver is connected with transmitting terminal processing module;
Described transmitting terminal processing module comprises frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, the input of frequency mixing module respectively with one of them the drive amplification model calling in intermediate-freuqncy signal and driver module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of amplification module and numerical control attenuation model calling, another road input of numerical control attenuation module is connected with the driver of driver module, the output of numerical control attenuation module with drive amplification module and be connected, the output of driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer,
Described receiving terminal processing module comprises low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of amplification module is connected with frequency mixing module, another road input of frequency mixing module and another drive amplification model calling of driver module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, and amplification module outputs signal.
It also comprises a clock, and the output of described clock is connected with FPGA and ADC respectively.
The beneficial effects of the utility model are: the signal that (1) ADC inputs obtains baseband signal through down-conversion, digital controlled oscillation circuit in down-conversion uses cordic algorithm to realize, only consume a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible, (2) baseband signal carries out little several times extraction, obtains the signal sample of 4 times of chip rates, then carries out matched filtering, and the benefit done like this is the calculating being beneficial to shaping matched filter coefficient, (3) signal after coupling enters bit synchronization and frequency deviation synchronization module, complete basic synchronous demodulation, because residual frequency deviation after DDC is about 0.1% of chip rate, the receiving algorithm of frequency deviation synchronization module is synchronous without the need to considering thick frequency deviation, directly carry out smart frequency offset tracking, the realization of the digital controlled oscillation circuit in essence frequency offset tracking uses DDS, instead of cordic algorithm, because the sequential amount of delay of cordic logic is larger in FPGA, cause loop delay large, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, the performance of loop capturing behavior and tracking behavior can be ensured, (4) subsequently, use frequency-domain equalization technology to carry out channel uncoiling, then carry out bit decision, ensure overall demodulation signal to noise ratio, frequency domain equalization adopts single-carrier wave frequency domain equalization technology, converts the signal into frequency domain and carries out channel estimating and equilibrium, switches back to time domain again after equilibrium is complete, (5) bit information after judgement is through channel decoding, and obtain the result after error correction, in order to support the precise time label of remote measurement, demodulating data will at the uniform velocity export, (6) due to above some, the utility model be just applicable to a kind of can the receiving terminal of ground-to-air wideband communication system of unmanned plane that passes of remote measurement, remote control, number, receiving terminal comprises handheld terminal and car-mounted terminal.
Accompanying drawing explanation
Fig. 1 is the utility model block diagram;
Fig. 2 is FPGA function module structure chart;
Fig. 3 is down conversion module structure chart;
Fig. 4 is bit synchronization function structure chart;
Fig. 5 is Farrow structured flowchart;
Fig. 6 is frequency deviation synchronization module structure chart;
Fig. 7 is frequency domain equalization function structure chart;
Fig. 8 is frame structure schematic diagram;
Fig. 9 is at the uniform velocity buffer module structure chart;
Figure 10 is radio frequency receiving block structural diagram.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail: as shown in Figure 1, it comprises Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the signal of communication from outside and the control signal from FPGA, the output of Receiver Module and intermediate frequency filtering model calling, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control of FPGA exports and is connected with ADC, the gain of FPGA controls to export and is connected with Receiver Module, FPGA is also by internal interface demodulated output data, the size that intermediate frequency filtering module receives from the signal of Receiver Module is 160MHz, be 30db by the gain control range of FPGA radio frequency receiver module,
As shown in Figure 2, described FPGA comprises down conversion module, AGC control module, decimal abstraction module, matched filtering module, bit synchronization module, frequency deviation synchronization module, frequency domain equalization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module, the input of down conversion module is connected with ADC, the output of down conversion module is connected with AGC control module, the gain of AGC control module controls to export to divide and is connected with Receiver Module, the conciliation output of AGC control module is connected with decimal abstraction module, the output of decimal abstraction module and matched filtering model calling, the output of matched filtering module and bit synchronization model calling, the output of bit synchronization module is connected with frequency deviation synchronization module, the output of frequency deviation synchronization module and frequency domain equalization model calling, the output of frequency domain equalization module is connected with decoding/judging module, the output of decoding/judging module is connected with de-interleaving block, the output of de-interleaving block is connected with at the uniform velocity buffer module, at the uniform velocity the output of buffer module is exported by internal interface and reconciles gain.
The signal of ADC input obtains baseband signal through down-conversion; Baseband signal carries out little several times extraction, obtains the signal sample of 4 times of chip rates, then carries out matched filtering, and the benefit done like this is the calculating being beneficial to shaping matched filter coefficient; Signal after coupling enters bit synchronization and frequency deviation synchronization module, completes basic synchronous demodulation; Subsequently, use frequency-domain equalization technology to carry out channel uncoiling, then carry out bit decision, ensure overall demodulation signal to noise ratio; Bit information after judgement, through channel decoding, obtains the result after error correction, finally at the uniform velocity Buffer output.
As shown in Figure 3, described down conversion module comprises quadrature downconvert circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of quadrature downconvert circuit is connected with external input signal and digital controlled oscillation circuit respectively, quadrature downconvert circuit exports I, Q two paths of signals to low-pass filter circuit, and low-pass filter circuit exports I, Q two paths of signals to AGC control module.Digital controlled oscillation circuit uses cordic algorithm to realize, and only consume a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible.
Described AGC control module is done adaptive power according to the power of signal and is controlled, and for ensureing the signal to noise ratio of demodulating algorithm, AGC control module exports AGC gain control signal to Receiver Module.Because native system is that non-high-speed is cruised, so the change of signal power is relatively slow, the circuit structure judging to return again control RF by FPGA can meet the received power control overflow of native system.
Described decimal abstraction module carries out little several times extraction to the baseband signal that down-conversion and AGC control to obtain, and the signal sample exporting 4 times of chip rates, to matched filtering module, is beneficial to the calculating of shaping matched filter coefficient; As shown in Figure 4, described bit synchronization module adopts Gardner algorithm, after input data carry out the interpolation/extraction of little several times, obtain the signal of 4 times of symbol sampler rates, gardner bit timing estimation error is carried out to 4 times of sample value signals, obtain instantaneous error value, after loop filter filter away high frequency noise, driving N CO produces the enable and interpolated parameter of timing interpolation; " Farrow timing interpolation " module uses Farrow structure, and interpolation obtains bit decision point accurately, and eventually through output Buffer output, described Farrow structure is a kind of polynomial interpolation implementation structure efficiently, and its logical construction as shown in Figure 5.
As shown in Figure 6, because residual frequency deviation after DDC is about 0.1% of chip rate, receiving algorithm is synchronous without the need to considering thick frequency deviation, directly carry out smart frequency offset tracking, described frequency deviation synchronization module is smart frequency offset tracking module, described frequency deviation synchronization module comprises quadrature downconvert circuit, NCO circuit, phase error estimation and phase error circuit and loop filter circuit, quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way is connected with quadrature downconvert circuit, the output of quadrature downconvert circuit is connected with phase error estimation and phase error circuit and frequency domain equalization circuit respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with quadrature downconvert circuit, the realization of described digital controlled oscillation circuit uses DDS algorithm, instead of cordic algorithm, because the sequential amount of delay of cordic logic is larger in FPGA, cause loop delay large, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, the performance of loop capturing behavior and tracking behavior can be ensured.
Frequency domain equalization adopts single-carrier wave frequency domain equalization technology, converts the signal into frequency domain and carries out channel estimating and equilibrium, switches back to time domain again after equilibrium is complete; For down link, count channel error correction, frame structure loss etc. in, information rate is higher, reaches about 10Mbps, multidiameter more than ten code elements, so should channel equalization be considered.If use traditional single carrier wave time domain balanced, when the number of symbols that multipath delay exceedes is more, the exponent number taking out sef-adapting filter can be caused excessive, thus computing is complicated and affect the sequential handling capacity of logical circuit.Native system adopts up-to-date channel equalization technique SCFDE (single carrier frequency domain equalization) solving multipath interference.SCFDE and OFDM(OFDM) be all carry out channel estimating and equilibrium on frequency domain, balanced compared to traditional single carrier wave time domain, there is higher computational efficiency and equalization performance, become the focus of current communication system, and as the balancing technique scheme that IEEE802.16 with 4G communicates.And SCFDE is compared to OFDM, there is following advantage: (1) SCFDE can overcome the too high problem of OFDM technology PAR (papr), thus transmitting terminal can use the RF power amplifier of low cost; (2) SCFDE can overcome OFDM technology to the more sensitive weakness of deviation ratio, more reliable than OFDM in high-speed aircraft communication; (3) although SCFDE and OFDM is signal link operational model similar (existing IFFT and FFT), but the IFFT of OFDM is placed on transmitting terminal, and IFFT and FFT of SCFDE is at receiving terminal, such air carrier can consume less hardware resource as transmitting terminal, for very beneficial the miniaturization of transmitting terminal and optimised power consumption.(4) SCFDE is not when using chnnel coding, can be subject to the damage of frequency selective fading unlike OFDM.
As shown in Figure 7, described frequency domain equalization module comprises three FFT modules and FFT1, FFT2 and FFT3, two IFFT modules and IFFT1 and IFFT2, unique word search module, channel estimation module, local unique word module, mend 0 module and channel equalization module, the signal of input is connected with FFT1 and unique word search module respectively, the output of local keyword module is connected with FFT2, unique word search module, the output of FFT1 with FFT2 is connected with channel estimation module, the output of channel estimation module is connected with IFFT1, output and benefit 0 model calling of IFFT1, mend output and the FFT3 model calling of 0 module, the output of FFT1 with FFT3 is connected with channel equalization module, channel equalization module is connected with IFFT2, IFFT2 outputs signal.As shown in Figure 8, Frame is continuous repeating frame structure, and unique word UW adopts Frank sequence, and its time domain has suitable PAR and amplitude distribution, has frequency band flat characteristic simultaneously, be beneficial to the reference as channel estimating on frequency domain.The length of UW is set to 128bit, the time of about corresponding 14.2us, and actual surmountable multidiameter delay is not less than 5us.Data load length is 1024bit.Then framing loss is approximately 1/8.Frame is known, and channel estimating carries out computing according to UW; Equilibrium then all carries out computing for UW and data load.Native system adopts the most direct zero forcing equalization, does not need to use feedback adjusting.In channel estimation phase, use 64 FFT, estimate 64 channel frequency coefficients.And time FFT and IFFT of 512 used during balancing operational, so just need to be inserted into 512 parameters by 64 channel coefficients.Concrete method is, after the coefficient of 64 is carried out IFFT, the length of 0 one-tenth 512 is mended at end, then carries out FFT and be transformed into frequency domain, obtains the frequency domain parameter of 512, delivers to channel equalization module.Time balanced, FFT and IFFT all uses Steam IO sequential, ensures enough handling capacities.In fact use Burst IO also can deal with, because native system chip rate only has about 15Mbaud/s, it is multiplexing that the clock rate that 100MHz can be used even higher obtains sequential.
Described decoding/judging module uses Viterbi soft-decision algorithm, calls Xilinx official IPCORE.
Described de-interleaving block simply cushions read-write for realizing.
Due to ADC sampling clock and actual signal element speed and non-integer multiple, add in demodulating process that may have been used high power clock carrys out improving operational speed, so module is above actually intermittently enable sequential.In order to support the precise time label of remote measurement, here demodulating data is at the uniform velocity exported.As shown in Figure 9, described at the uniform velocity buffer module comprises data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel of data buffering module exports and is connected with buffering capacity monitoring modular, another road of data buffering module exports data, the output of buffering capacity monitoring modular and loop filtering model calling, the output of loop filtering module is connected with numerical control oscillation module, one tunnel of numerical control oscillation module exports and data buffering model calling, another road of numerical control oscillation module exports output clock.
As shown in Figure 10, described Receiver Module comprises duplexer, transmitting terminal processing module, receiving terminal processing module and driver module, described duplexer is used for receiving and sending data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, and the output of driver module is connected with transmitting terminal processing module and receiving terminal processing module respectively;
Described driver module comprises crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, described local oscillator needs SPI code to control, described driver exports 5 parallel-by-bit control codes, the output of crystal oscillator is connected with local oscillator, the output of local oscillator is connected with merit sub-module, the two-way of merit sub-module export respectively with two drive amplification model calling, two drive amplification modules are connected with transmitting terminal processing module and receiving terminal processing module respectively, and driver is connected with transmitting terminal processing module;
Described transmitting terminal processing module comprises frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, the input of frequency mixing module respectively with one of them the drive amplification model calling in intermediate-freuqncy signal and driver module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of amplification module and numerical control attenuation model calling, another road input of numerical control attenuation module is connected with the driver of driver module, the output of numerical control attenuation module with drive amplification module and be connected, the output of driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer,
Described receiving terminal processing module comprises low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of amplification module is connected with frequency mixing module, another road input of frequency mixing module and another drive amplification model calling of driver module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, and amplification module outputs signal.
At receive path, 1520 ± 40MHz(downlink telemetry/picture signal) signal amplifies post filtering through low noise and amplifies, is mixed to 160 ± 4MHz intermediate frequency.Export after being amplified by intermediate frequency, power output is-5dBm ~ 0dBm.
Claims (8)
1. the receiving terminal for unmanned plane ground-to-air wideband communication system, it is characterized in that: it comprises Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the signal of communication from outside and the control signal from FPGA, the output of Receiver Module and intermediate frequency filtering model calling, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control of FPGA exports and is connected with ADC, the gain of FPGA controls to export and is connected with Receiver Module, and FPGA is also by internal interface demodulated output data;
Described FPGA comprises down conversion module, AGC control module, decimal abstraction module, matched filtering module, bit synchronization module, frequency deviation synchronization module, frequency domain equalization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module, the input of down conversion module is connected with ADC, the output of down conversion module is connected with AGC control module, the gain of AGC control module controls to export to divide and is connected with Receiver Module, the conciliation output of AGC control module is connected with decimal abstraction module, the output of decimal abstraction module and matched filtering model calling, the output of matched filtering module and bit synchronization model calling, the output of bit synchronization module is connected with frequency deviation synchronization module, the output of frequency deviation synchronization module and frequency domain equalization model calling, the output of frequency domain equalization module is connected with decoding/judging module, the output of decoding/judging module is connected with de-interleaving block, the output of de-interleaving block is connected with at the uniform velocity buffer module, at the uniform velocity the output of buffer module exports demodulation gain by internal interface.
2. a kind of receiving terminal for unmanned plane ground-to-air wideband communication system according to claim 1, it is characterized in that: described down conversion module comprises quadrature downconvert circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of quadrature downconvert circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, quadrature downconvert circuit exports I, Q two paths of signals to low-pass filter circuit, low-pass filter circuit exports I, Q two paths of signals to AGC control module, and described digital controlled oscillation circuit uses cordic algorithm.
3. a kind of receiving terminal for unmanned plane ground-to-air wideband communication system according to claim 1, it is characterized in that: described bit synchronization module comprises input buffer module, reg module, Timing error estimate module, loop filter, digital controlled oscillation circuit, timing interpose module, export buffer module and two shift registers, the input of input buffer module and matched filtering model calling, the output of input buffer module and reg model calling, the output of reg module is connected with one of them shift register, the output of this shift register is connected with timing interpose module, one tunnel of timing interpose module exports and is connected with another shift register, the output of this shift register and timing error model calling, the output of Timing error estimate module is connected with loop filter, the output of loop filter is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with timing interpose module, another road of timing interpose module exports and exports data by exporting buffer module.
4. a kind of receiving terminal for unmanned plane ground-to-air wideband communication system according to claim 1, it is characterized in that: described frequency deviation synchronization module comprises quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way is connected with quadrature downconvert circuit, the output of quadrature downconvert circuit is connected with phase error estimation and phase error circuit and frequency domain equalization circuit respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with quadrature downconvert circuit, the practical DDS algorithm of described digital controlled oscillation circuit.
5. a kind of receiving terminal for unmanned plane ground-to-air wideband communication system according to claim 1, it is characterized in that: described frequency domain equalization module comprises three FFT modules and FFT1, FFT2 and FFT3, two IFFT modules and IFFT1 and IFFT2, unique word search module, channel estimation module, local unique word module, mend 0 module and channel equalization module, input signal is connected with FFT1 and unique word search module respectively, the output of local keyword module is connected with FFT2, unique word search module, the output of FFT1 with FFT2 is connected with channel estimation module, the output of channel estimation module is connected with IFFT1, output and benefit 0 model calling of IFFT1, mend output and the FFT3 model calling of 0 module, the output of FFT1 with FFT3 is connected with channel equalization module, channel equalization module is connected with IFFT2, IFFT2 outputs signal.
6. a kind of receiving terminal for unmanned plane ground-to-air wideband communication system according to claim 1, it is characterized in that: described at the uniform velocity buffer module comprises data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel of data buffering module exports and is connected with buffering capacity monitoring modular, another road of data buffering module exports data, the output of buffering capacity monitoring modular and loop filtering model calling, the output of loop filtering module is connected with numerical control oscillation module, one tunnel of numerical control oscillation module exports and data buffering model calling, another road clock signal of numerical control oscillation module.
7. a kind of receiving terminal for unmanned plane ground-to-air wideband communication system according to claim 1, it is characterized in that: described Receiver Module comprises duplexer, transmitting terminal processing module, receiving terminal processing module and driver module, described duplexer for receive and send data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, and the output of driver module is connected with transmitting terminal processing module and receiving terminal processing module respectively;
Described driver module comprises crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way of merit sub-module export respectively with two drive amplification model calling, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes;
Described transmitting terminal processing module comprises frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel of frequency mixing module is input as intermediate-freuqncy signal, the input of another road and one of them the drive amplification model calling in driver module of frequency mixing module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driver module all with numerical control attenuation model calling, the output of numerical control attenuation module with drive amplification module and be connected, the output of driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer,
Described receiving terminal processing module comprises low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of amplification module is all connected with frequency mixing module with the output of another drive amplification module of driver module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, and amplification module outputs signal.
8. a kind of receiving terminal for unmanned plane ground-to-air wideband communication system according to claim 1, is characterized in that: it also comprises a clock, and the output of described clock is connected with FPGA and ADC respectively.
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| CN201420718515.0U CN204180063U (en) | 2014-11-26 | 2014-11-26 | A kind of receiving terminal for unmanned plane ground-to-air wideband communication system |
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| CN201420718515.0U CN204180063U (en) | 2014-11-26 | 2014-11-26 | A kind of receiving terminal for unmanned plane ground-to-air wideband communication system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104378130A (en) * | 2014-11-26 | 2015-02-25 | 成都中远信电子科技有限公司 | Receiving terminal for unmanned aerial vehicle land-to-air wideband communication system |
| CN104393885A (en) * | 2014-11-26 | 2015-03-04 | 成都中远信电子科技有限公司 | Receiving terminal and method for ground-air broadband communication system for unmanned aerial vehicle |
| CN106841840A (en) * | 2016-11-24 | 2017-06-13 | 中国电子科技集团公司第四十研究所 | A kind of data processing method of low-frequency range variable intermediate frequency |
-
2014
- 2014-11-26 CN CN201420718515.0U patent/CN204180063U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104378130A (en) * | 2014-11-26 | 2015-02-25 | 成都中远信电子科技有限公司 | Receiving terminal for unmanned aerial vehicle land-to-air wideband communication system |
| CN104393885A (en) * | 2014-11-26 | 2015-03-04 | 成都中远信电子科技有限公司 | Receiving terminal and method for ground-air broadband communication system for unmanned aerial vehicle |
| CN104393885B (en) * | 2014-11-26 | 2016-08-31 | 成都中远信电子科技有限公司 | A kind of reception terminal for unmanned plane ground-to-air wideband communication system and method thereof |
| CN106841840A (en) * | 2016-11-24 | 2017-06-13 | 中国电子科技集团公司第四十研究所 | A kind of data processing method of low-frequency range variable intermediate frequency |
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