CN104333391B - A kind of air-ground narrow band communication method for unmanned plane - Google Patents
A kind of air-ground narrow band communication method for unmanned plane Download PDFInfo
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Abstract
A kind of air-ground narrow band communication method for unmanned plane, it includes ground installation step of transmitting and unmanned plane receiving step；Described ground installation step of transmitting includes following sub-step: the S11: the one FPGA sends to DAC after the data signal of transmission being processed, and transmitting power control signal is to radiofrequency emitting module simultaneously；After the data signal received is changed by S12:DAC, send tremendously high frequency filter circuit；S13: the high-frequency filter circuit signal to receiving carries out High frequency filter process, is sent to radiofrequency emitting module afterwards；S14: radiofrequency emitting module launches signal of communication.The present invention is to carrying out perfect by the earth-space communication subsystem in the system of unmanned plane that passes of remote measurement, remote control, number, it is achieved a kind of air-ground broadband connections method for unmanned plane, has that transmitting terminal is low in energy consumption, receiving terminal data process the advantage such as accurately.
Description
Technical field
The present invention relates to a kind of air-ground narrow band communication method for unmanned plane.
Background technology
Unmanned plane has that cost effectiveness is low, zero injures and deaths and dispose the advantage such as flexibly, can help even to replace the mankind to play a role in a lot of scenes, such as the personnel's search and rescue after calamity, infrastructure supervision etc..No matter in civilian or military domain, unmanned plane all has wide application and development prospect.
The system of unmanned plane that passes of remote measurement, remote control, number can include Air-Ground two-way communication and ground-ground two-way communication two parts, divide according to wire data type, wideband signal communication can be divided into communicate with narrow band signal two types, wherein broadband signal is unmanned plane reconnaissance image data transmission service and unmanned plane telemetry service, narrow band signal is underwater acoustic remote control business between handheld terminal and unmanned plane, communication service between handheld terminal and car-mounted terminal.And narrow band communication includes the transmitting terminal for ground installation and the reception terminal for ground unmanned plane, it is therefore desirable to a kind of air-ground narrow band communication method for unmanned plane.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, it is provided that a kind of transmitting terminal is low in energy consumption, receiving terminal data process the accurate air-ground narrow band communication method for unmanned plane.
It is an object of the invention to be achieved through the following technical solutions: a kind of air-ground narrow band communication method for unmanned plane, it includes ground installation step of transmitting and unmanned plane receiving step；
Described ground installation step of transmitting includes following sub-step:
S11: the one FPGA sends to DAC after the data signal of transmission being processed, and transmitting power control signal is to radiofrequency emitting module simultaneously；
After the data signal received is changed by S12:DAC, send tremendously high frequency filter circuit；
S13: the high-frequency filter circuit signal to receiving carries out High frequency filter process, is sent to radiofrequency emitting module afterwards；
S14: radiofrequency emitting module launches signal of communication；
Described unmanned plane receiving step includes following sub-step:
S21: Receiver Module accepts the signal of communication from outside and the gain control signal from the 2nd FPGA, is sent to intermediate frequency filtering module after conversion；
S22: the intermediate frequency filtering module signal to inputting from Receiver Module carries out intermediate frequency filtering, and is sent to ADC；
S23:ADC receives the signal from the output of intermediate frequency filtering module, is sent to the 2nd FPGA after conversion；
After signal is processed by the S24: the two FPGA, exporting condition data by internal interface, the 2nd FPGA is also to Receiver Module outputing gain control signal.
Described step S11 includes following sub-step:
S111: data source is sent into interleaving block and is interleaved operation；
S112: data intertexture completed are sent into framing module and are carried out framing；
S113: the data completed by framing are sent in convolutional encoder module and are carried out convolutional encoding；
S114: data convolutional encoding completed are sent into QPSK mapping block and are carried out QPSK mapping；
S115: the data mapped by QPSK send into molding filtration module, is shaped filtering；
S116: data filtering completed send into DUC module, carry out Digital Up Convert process, directly will change to intermediate frequency on signal；
S117: digital medium-frequency signal is sent in DAC.
Molding filtration described in step S115 uses the root raised cosine filtering of alhpa=0.5, and exponent number is 50 rank.
Described step S24 includes following sub-step:
Down conversion module in S241:FPGA carries out down-converted to the input from ADC, and exports to decimal abstraction module；
S242: the decimal abstraction module baseband signal to receiving carries out little several times extraction, output signal sample value is to thick frequency offset correction module；
S243: thick frequency offset correction module obtains thick frequency deviation information and correction process to input signal, and exports to bit sync module；
S244: bit sync module carries out bit synchronization process to input signal, outputs signal to narrow-band filtering module；
S245: narrow-band filtering module further filters out the out-of-band noise of remnants, outputs signal to essence frequency deviation synchronization module；
S246: essence frequency deviation synchronization module uses digital phase-locked loop to carry out carrier synchronization, completes basic synchronous demodulation, outputs signal to decoding/judging module；
S247: decoding/judging module receives signal and carries out folding coding, it is ensured that overall demodulation signal to noise ratio, and exports to de-interleaving block；
S248: de-interleaving block carries out buffering read-write, exports signal at the uniform velocity buffer module afterwards；
S249: demodulating data is at the uniform velocity exported by the uniform velocity buffer module by internal interface.
Described step S241 includes following sub-step:
S2411: orthogonal mixting circuit receives the input from ADC and the input of digital controlled oscillation circuit, output I, Q two paths of signals to low-pass filter circuit, and described digital controlled oscillation circuit uses cordic algorithm；
S2412: low-pass filtering module exports to decimal abstraction module after input signal is carried out LPF.
Described step S243 includes following sub-step:
S2431: orthogonal mixting circuit receives the many times of symbol sampler rate signals from the input of decimal abstraction module, and exports to eliminating modulation intelligence module；
S2432: eliminate modulation intelligence module and eliminate modulation intelligence, it is thus achieved that single audio frequency dot information；
S2433:FFT module carries out FFT to single audio frequency dot information, and exports to spectral line peak value searching module；
S2434: spectral line peak value searching module carries out peak value searching, obtains thick frequency deviation information, and exports to calculating frequency deviation module；
S2435: calculate frequency deviation module and thick frequency deviation information is calculated, it may be judged whether need to proceed to correct:
(1) if the thick frequency deviation message that obtains of follow-up FFT several times is close, peak value is enough, then result be sequentially output after numerical control oscillation module and orthogonal frequency mixing module, be directly output to narrow-band filtering module；
(2), in the case of other, it is believed that system step-out, result is sequentially output after numerical control oscillation module, orthogonal frequency mixing module and elimination modulation intelligence module, returns step S2432.
Described step S245 includes following sub-step:
S2451: gardner bit timing estimation error will be carried out from narrow-band filtering module input data, and obtain instantaneous error value；
S2452: loop filter filters high-frequency noise；
S2453: drive digital controlled oscillation circuit to produce timing interpolation and enable and interpolated parameter；
S2454: data are timed interpolation, obtains bit decision point accurately；
S2455: by output buffer output result to frequency deviation synchronization module.
Described step S246 includes following sub-step:
S2461: orthogonal mixting circuit carries out orthogonal mixing to from bit sync module input signal, outputs signal to phase error estimation and phase error circuit；
S2462: phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit；
S2463: loop filter circuit is filtered, output is to digital controlled oscillation circuit；
S2464: digital controlled oscillation circuit outputs signal to orthogonal mixting circuit, and described digital controlled oscillation circuit uses DDS algorithm；
S2465: orthogonal mixting circuit outputs signal to decoding/judging module.
Folding coding described in step S247 uses Viterbi soft-decision algorithm.
Described step S249 includes following sub-step:
S2491: data buffering module receives the data from de-interleaving block input and clock, outputs signal to buffering capacity detection module；
S2492: the buffering capacity of data buffer module is monitored by buffering capacity detection module, outputs signal to loop filtering module simultaneously；
S2493: after loop filtering module is filtered, outputs signal to numerical control oscillation module；
S2494: numerical control oscillation module has two-way to export, a road output clock, a road output signal controls data buffering module；
S2495: data buffering module output data.
Described Receiver Module is identical with radiofrequency emitting module structure, including duplexer, transmitting terminal processing module, receiving terminal processing module and driving module, being used for of described duplexer receives and sends data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, drives the output of module to be connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described driving module includes crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way output of merit sub-module is connected with two drive amplification modules respectively, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel input of frequency mixing module is intermediate-freuqncy signal, another road input of frequency mixing module is connected with driving one of them the drive amplification module in module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driving module is all connected with numerical control attenuation module, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and another drive amplification module of driving module is all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, amplification module output signal.
The invention has the beneficial effects as follows: for transmitting terminal: native system uses frequency division multiple access to work while supporting multi-aircraft, in the case of frequency division multiple access, base band instantaneous modulation speed ratio is relatively low, under same effective speed, the required transient transmission power consumed of aircraft is much lower relative to time division multiple acess and CDMA, and this is very important for the SUAV that volume and power are the most limited；For receiving terminal: the signal of (1) ADC input obtains baseband signal through down coversion, digital controlled oscillation circuit in down coversion uses cordic algorithm to realize, only consuming a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible to be disregarded；(2) baseband signal carries out little several times extraction, obtains the signal sample of 4 times of chip rates, then carries out matched filtering, advantage of this is that the calculating of beneficially matched filtering coefficient；(3) due to despreading after signal bandwidth only have about 180kHz, and high-doppler frequency deviation reaches 3kHz, at certain interference situations., frequency deviation may be outside transnormal phaselocked loop capture zone, so carrier synchronization partial resolution becomes " thick frequency offset correction " and " essence frequency deviation synchronization " two links here；(4) relatively big due to frequency deviation, DDC, enforcement is the filtering in somewhat broadband, it is ensured that signal spectrum is without damage；(5) after thick frequency offset correction completes, then carry out a narrow-band filtering, further filter out the out-of-band noise of remnants；(6) narrow band signal bandwidth is less, not in use by balancing techniques such as SCFDE, cost-effective；(7) bit information after judgement is through channel decoding, obtains the result after error correction, and in order to support the precise time label of remote measurement, demodulating data will at the uniform velocity export；(8) due to above some, the present invention is just applicable to that a kind of transmitting terminal is low in energy consumption, receiving terminal data process accurately can the reception terminal of the air-ground narrow-band communication system of unmanned plane that passes of remote measurement, remote control, number, receive terminal and include unmanned plane terminal.
Accompanying drawing explanation
Fig. 1 is ground installation step of transmitting flow chart of the present invention；
Fig. 2 is unmanned plane receiving step flow chart of the present invention；
Fig. 3 is the device schematic diagram of the method dependence of the present invention in embodiment；
Fig. 4 is step S11 sub-step flow chart；
Fig. 5 is step S24 sub-step flow chart；
Fig. 6 is the down conversion module structure chart that embodiment realizes step S241；
Fig. 7 is the thick frequency offset correction function structure chart that embodiment realizes step S243；
Fig. 8 is the bit sync module structure chart that embodiment realizes step S245；
Fig. 9 is Farrow structured flowchart；
Figure 10 is the smart frequency deviation synchronization module structure chart that embodiment realizes step S246；
Figure 11 is the at the uniform velocity buffer module structure chart that embodiment realizes step S249；
Figure 12 is ground surface end radiofrequency emitting module structure chart；
Figure 13 is unmanned plane end Receiver Module structure chart.
Detailed description of the invention
Technical scheme is described in further detail below in conjunction with the accompanying drawings: a kind of air-ground narrow band communication method for unmanned plane, it includes ground installation step of transmitting and unmanned plane receiving step；
As it is shown in figure 1, described ground installation step of transmitting includes following sub-step:
S11: the one FPGA sends to DAC after the data signal of transmission being processed, and transmitting power control signal is to radiofrequency emitting module simultaneously；
After the data signal received is changed by S12:DAC, send tremendously high frequency filter circuit；
S13: the high-frequency filter circuit signal to receiving carries out High frequency filter process, is sent to radiofrequency emitting module afterwards；
S14: radiofrequency emitting module launches signal of communication；
As shown in Figure 3, the unmanned plane transmitting terminal completing this step includes a FPGA, DAC, high-frequency filter circuit and radiofrequency emitting module, the data signal output of the oneth FPGA is connected with DAC, the power of the oneth FPGA controls output and is connected with radiofrequency emitting module, the output of DAC is connected with filter circuit, and the output of filter circuit is connected with radiofrequency emitting module；It is 70MHz that radiofrequency emitting module receives from the intermediate-freuqncy signal size of filter circuit, is 30db by FPGA to the Power control range of radiofrequency emitting module.
As in figure 2 it is shown, described unmanned plane receiving step includes following sub-step:
S21: Receiver Module accepts the signal of communication from outside and the gain control signal from the 2nd FPGA, is sent to intermediate frequency filtering module after conversion；
S22: the intermediate frequency filtering module signal to inputting from Receiver Module carries out intermediate frequency filtering, and is sent to ADC；
S23:ADC receives the signal from the output of intermediate frequency filtering module, is sent to the 2nd FPGA after conversion；
After signal is processed by the S24: the two FPGA, exporting condition data by internal interface, the 2nd FPGA is also to Receiver Module outputing gain control signal.
As shown in Figure 3, the ground installation receiving terminal completing this step includes Receiver Module, intermediate frequency filtering module, ADC and the 2nd FPGA, Receiver Module receives the signal of communication from outside and the control signal from the 2nd FPGA, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with the 2nd FPGA, the clock control output of the 2nd FPGA is connected with ADC, the gain control output of the 2nd FPGA is connected with Receiver Module, and the 2nd FPGA is also by internal interface demodulated output data；It is 70MHz that intermediate frequency filtering module receives from the size of the signal of Receiver Module, is 30db by FPGA to the gain control range of Receiver Module.
As shown in Figure 4, described step S11 includes following sub-step:
S111: data source is sent into interleaving block and is interleaved operation；
S112: data intertexture completed are sent into framing module and are carried out framing；
S113: the data completed by framing are sent in convolutional encoder module and are carried out convolutional encoding；
S114: data convolutional encoding completed are sent into QPSK mapping block and are carried out QPSK mapping；
S115: the data mapped by QPSK send into molding filtration module, is shaped filtering；
S116: data filtering completed send into DUC module, carry out Digital Up Convert process, directly will change to intermediate frequency on signal；
S117: digital medium-frequency signal is sent in DAC.
Molding filtration described in step S115 uses the root raised cosine filtering of alhpa=0.5, and exponent number is 50 rank.
As it is shown in figure 5, described step S24 includes following sub-step:
Down conversion module in S241:FPGA carries out down-converted to the input from ADC, and exports to decimal abstraction module；
S242: the decimal abstraction module baseband signal to receiving carries out little several times extraction, output signal sample value is to thick frequency offset correction module；
S243: thick frequency offset correction module obtains thick frequency deviation information and correction process to input signal, and exports to bit sync module；
S244: bit sync module carries out bit synchronization process to input signal, outputs signal to narrow-band filtering module；
S245: narrow-band filtering module further filters out the out-of-band noise of remnants, outputs signal to essence frequency deviation synchronization module；
S246: essence frequency deviation synchronization module uses digital phase-locked loop to carry out carrier synchronization, completes basic synchronous demodulation, outputs signal to decoding/judging module；
S247: decoding/judging module receives signal and carries out folding coding, it is ensured that overall demodulation signal to noise ratio, and exports to de-interleaving block；
S248: de-interleaving block carries out buffering read-write, exports signal at the uniform velocity buffer module afterwards；
S249: demodulating data is at the uniform velocity exported by the uniform velocity buffer module by internal interface.
As shown in Figure 6, the down conversion module realizing step S241 includes orthogonal mixting circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of orthogonal mixting circuit is connected with external input signal and digital controlled oscillation circuit respectively, orthogonal mixting circuit output I, Q two paths of signals is to low-pass filter circuit, and low-pass filter circuit output I, Q two paths of signals is to decimal abstraction module.Digital controlled oscillation circuit uses cordic algorithm to realize, and only consumes a small amount of register and adder resource, does not consume RAM, and resource loss is substantially negligible to be disregarded.
Described step S241 includes following sub-step:
S2411: orthogonal mixting circuit receives the input from ADC and the input of digital controlled oscillation circuit, output I, Q two paths of signals to low-pass filter circuit, and described digital controlled oscillation circuit uses cordic algorithm；
S2412: low-pass filtering module exports to decimal abstraction module after input signal is carried out LPF.
Owing to after despreading, signal bandwidth only has about 180kHz, and high-doppler frequency deviation reaches 3kHz, at certain interference situations., frequency deviation may be outside transnormal phaselocked loop capture zone, so carrier synchronization partial resolution becomes " thick frequency offset correction " and " essence frequency deviation synchronization " two links here.
Owing to frequency deviation is relatively big, DDC, enforcement is the filtering in somewhat broadband, it is ensured that signal spectrum is without damage；After thick frequency offset correction completes, then carry out a narrow-band filtering, further filter out the out-of-band noise of remnants.
Narrow band signal signal bandwidth is less, does not use the balancing techniques such as SCFDE.
As shown in Figure 7, the thick frequency offset correction module realizing step S243 includes orthogonal mixting circuit, eliminate modulation intelligence circuit, fft circuit, spectral line peak search circuit, calculate frequency deviation circuit and digital controlled oscillation circuit, orthogonal mixting circuit receives the signal from the output of decimal abstraction module, the output of orthogonal mixting circuit is connected with narrow-band filtering module and elimination modulation intelligence circuit respectively, the output eliminating modulation intelligence circuit is connected with fft circuit, the output of fft circuit is connected with spectral line peak search circuit, the output of spectral line peak search circuit is connected with calculating frequency deviation circuit, the output calculating frequency deviation circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit.
Input signal is 4 times of symbol sampler rates, enters 4 power computing modules, eliminates the modulation intelligence of QPSK, it is thus achieved that single audio frequency dot information.Through FFT and spectral line peak value searching, thick frequency deviation information can be obtained.Wherein use 2048 points of counting of FFT, it is possible to obtain of a sufficiently low residual frequency deviation, it is ensured that the normal capture of essence frequency deviation synchronization module.
After correction once, the thick frequency deviation information that follow-up FFT several times obtains is close, and peak value is enough, then it is assumed that stablized, it is not necessary to correct again；Otherwise it is assumed that system step-out, re-start thick frequency offset correction.
Described step S243 includes following sub-step:
S2431: orthogonal mixting circuit receives the many times of symbol sampler rate signals from the input of decimal abstraction module, and exports to eliminating modulation intelligence module；
S2432: eliminate modulation intelligence module and eliminate modulation intelligence, it is thus achieved that single audio frequency dot information；
S2433:FFT module carries out FFT to single audio frequency dot information, and exports to spectral line peak value searching module；
S2434: spectral line peak value searching module carries out peak value searching, obtains thick frequency deviation information, and exports to calculating frequency deviation module；
S2435: calculate frequency deviation module and thick frequency deviation information is calculated, it may be judged whether need to proceed to correct:
(1) if the thick frequency deviation message that obtains of follow-up FFT several times is close, peak value is enough, then result be sequentially output after numerical control oscillation module and orthogonal frequency mixing module, be directly output to narrow-band filtering module；
(2), in the case of other, it is believed that system step-out, result is sequentially output after numerical control oscillation module, orthogonal frequency mixing module and elimination modulation intelligence module, returns step S2432.
nullAs shown in Figure 8，The bit sync module of implementation method step S244 includes inputting buffer module、Reg module、Timing error estimate module、Loop filter、Digital controlled oscillation circuit、Regularly interpolation module、Output buffer module and two shift registers，The input of input buffer module is connected with narrow-band filtering module，The output of input buffer module is connected with reg module，The output of reg module is connected with one of them shift register，The output of this shift register is connected with timing interpolation module，Regularly a road output of interpolation module is connected with another shift register，The output of this shift register is connected with timing error module，The output of Timing error estimate module is connected with loop filter，The output of loop filter is connected with digital controlled oscillation circuit，The output of digital controlled oscillation circuit is connected with timing interpolation module，Regularly another road output of interpolation module is by output buffer module output data.Regularly interpolation module uses Farrow structure, and interpolation obtains bit decision point accurately, and eventually through output Buffer output, described Farrow structure is that a kind of efficient polynomial interpolation realizes structure, and its logical construction is as shown in Figure 9.
Described step S244 includes following sub-step:
S2451: gardner bit timing estimation error will be carried out from narrow-band filtering module input data, and obtain instantaneous error value；
S2452: loop filter filters high-frequency noise；
S2453: drive digital controlled oscillation circuit to produce timing interpolation and enable and interpolated parameter；
S2454: data are timed interpolation, obtains bit decision point accurately；
S2455: by output buffer output result to frequency deviation synchronization module.
As shown in Figure 10, realize step S246 smart frequency deviation synchronization module include orthogonal mixting circuit, NCO circuit, phase error estimation and phase error circuit and loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way connects with orthogonal mixting circuit, the output of orthogonal mixting circuit is connected with phase error estimation and phase error circuit and judgement/decoding module respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit；The realization of described digital controlled oscillation circuit uses DDS algorithm, rather than cordic algorithm, because the sequential amount of delay of cordic logic is bigger in FPGA, cause loop delay big, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, it is ensured that loop capturing behavior and the performance of the behavior of tracking.
Described step S246 includes following sub-step:
S2461: orthogonal mixting circuit carries out orthogonal mixing to from bit sync module input signal, outputs signal to phase error estimation and phase error circuit；
S2462: phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit；
S2463: loop filter circuit is filtered, output is to digital controlled oscillation circuit；
S2464: digital controlled oscillation circuit outputs signal to orthogonal mixting circuit, and described digital controlled oscillation circuit uses DDS algorithm；
S2465: orthogonal mixting circuit outputs signal to decoding/judging module.
Folding coding described in step S247 uses Viterbi soft-decision algorithm, calls Xilinx official IPCORE.
Due to ADC sampling clock and actual signal element speed non-integer multiple, add that may have been used high power clock in demodulating process carrys out improving operational speed, so the sequential that module above the most discontinuously enables.In order to support the precise time label of remote control, here demodulating data is at the uniform velocity exported.As shown in figure 11, the at the uniform velocity buffer module realizing step S249 includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel output of data buffering module is connected with buffering capacity monitoring modular, another road output output data of data buffering module, the output of buffering capacity monitoring modular is connected with loop filtering module, the output of loop filtering module is connected with numerical control oscillation module, one tunnel output of numerical control oscillation module is connected with data buffering module, another road output output clock of numerical control oscillation module.
Described step S249 includes following sub-step:
S2491: data buffering module receives the data from de-interleaving block input and clock, outputs signal to buffering capacity detection module；
S2492: the buffering capacity of data buffer module is monitored by buffering capacity detection module, outputs signal to loop filtering module simultaneously；
S2493: after loop filtering module is filtered, outputs signal to numerical control oscillation module；
S2494: numerical control oscillation module has two-way to export, a road output clock, a road output signal controls data buffering module；
S2495: data buffering module output data.
As shown in figure 12, described Receiver Module is identical with radiofrequency emitting module structure, including duplexer, transmitting terminal processing module, receiving terminal processing module and driving module, being used for of described duplexer receives and sends data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, drives the output of module to be connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described driving module includes crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way output of merit sub-module is connected with two drive amplification modules respectively, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel input of frequency mixing module is intermediate-freuqncy signal, another road input of frequency mixing module is connected with driving one of them the drive amplification module in module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driving module is all connected with numerical control attenuation module, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and another drive amplification module of driving module is all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, amplification module output signal.
As shown in figure 11, at transmission channel, the 70 up remote signals of MHz() after intermediate-freuqncy signal enters this module, through fading to the up remote signal of 1430MHz(with the mixing of frequency conversion local oscillator) it is interior that (each unmanned plane takies 7MHz bandwidth, totally 5 groups of unmanned planes, and frequency range is spaced about 10MHz, i.e. take 80MHz bandwidth), amplified carrying out numerical control attenuation, attenuation range is 30dB, makes signal have 30dB dynamic range.Then may amplify the signal to export as upward signal.Wherein numerical-control attenuator needs 5 parallel-by-bit codes to control, and local oscillator needs SPI code to control.
As shown in figure 12, receive passage, the up remote signal of 1430MHz() signal through low noise amplify post filtering amplify again, be mixed to 70 ± 2MHz.Exporting after being amplified by intermediate frequency, power output is-5dBm～0dBm.
Claims (9)
1. the air-ground narrow band communication method for unmanned plane, it is characterised in that: it includes ground installation step of transmitting and unmanned plane receiving step；
Described ground installation step of transmitting includes following sub-step:
S11: the one FPGA sends to DAC after the data signal of transmission being processed, and transmitting power control signal is to radiofrequency emitting module simultaneously；
After the data signal received is changed by S12:DAC, send tremendously high frequency filter circuit；
S13: the high-frequency filter circuit signal to receiving carries out High frequency filter process, is sent to radiofrequency emitting module afterwards；
S14: radiofrequency emitting module launches signal of communication；
Described unmanned plane receiving step includes following sub-step:
S21: Receiver Module receives the signal of communication from outside and the gain control signal from the 2nd FPGA, is sent to intermediate frequency filtering module after conversion；
S22: the intermediate frequency filtering module signal to inputting from Receiver Module carries out intermediate frequency filtering, and is sent to ADC；
S23:ADC receives the signal from the output of intermediate frequency filtering module, is sent to the 2nd FPGA after conversion；
After signal is processed by the S24: the two FPGA, by internal interface demodulated output data, the 2nd FPGA is also to Receiver Module outputing gain control signal；
Described step S11 includes following sub-step:
S111: data source is sent into interleaving block and is interleaved operation；
S112: data intertexture completed are sent into framing module and are carried out framing；
S113: the data completed by framing are sent in convolutional encoder module and are carried out convolutional encoding；
S114: data convolutional encoding completed are sent into QPSK mapping block and are carried out QPSK mapping；
S115: the data mapped by QPSK send into molding filtration module, is shaped filtering；
S116: data filtering completed send into DUC module, carry out Digital Up Convert process, directly up-convert the signals to intermediate frequency；
S117: digital medium-frequency signal is sent in DAC.
A kind of air-ground narrow band communication method for unmanned plane the most according to claim 1, it is characterised in that: the molding filtration described in step S115 uses the root raised cosine filtering of alhpa=0.5, and exponent number is 50 rank.
A kind of air-ground narrow band communication method for unmanned plane the most according to claim 1, it is characterised in that: described step S24 includes following sub-step:
Down conversion module in S241:FPGA carries out down-converted to the input from ADC, and exports to decimal abstraction module；
S242: the decimal abstraction module baseband signal to receiving carries out little several times extraction, output signal sample value is to thick frequency offset correction module；
S243: thick frequency offset correction module obtains thick frequency deviation information and correction process to input signal, and exports to bit sync module；
S244: bit sync module carries out bit synchronization process to input signal, outputs signal to narrow-band filtering module；
S245: narrow-band filtering module further filters out the out-of-band noise of remnants, outputs signal to essence frequency deviation synchronization module；
S246: essence frequency deviation synchronization module uses digital phase-locked loop to carry out carrier synchronization, completes synchronous demodulation, outputs signal to decoding/judging module；
S247: decoding/judging module receives signal and carries out folding coding, it is ensured that overall demodulation signal to noise ratio, and exports to de-interleaving block；Described folding coding uses Viterbi soft-decision algorithm；
S248: de-interleaving block carries out buffering read-write, exports signal at the uniform velocity buffer module afterwards；
S249: demodulating data is at the uniform velocity exported by the uniform velocity buffer module by internal interface.
A kind of air-ground narrow band communication method for unmanned plane the most according to claim 3, it is characterised in that: described step S241 includes following sub-step:
S2411: orthogonal mixting circuit receives the input from ADC and the input of digital controlled oscillation circuit, output I, Q two paths of signals to low-pass filter circuit, and described digital controlled oscillation circuit uses cordic algorithm；
S2412: low-pass filtering module exports to decimal abstraction module after input signal is carried out LPF.
A kind of air-ground narrow band communication method for unmanned plane the most according to claim 3, it is characterised in that: described step S243 includes following sub-step:
S2431: orthogonal mixting circuit receives the many times of symbol sampler rate signals from the input of decimal abstraction module, and exports to eliminating modulation intelligence module；
S2432: eliminate modulation intelligence module and eliminate modulation intelligence, it is thus achieved that single audio frequency dot information；
S2433:FFT module carries out FFT to single audio frequency dot information, and exports to spectral line peak value searching module；
S2434: spectral line peak value searching module carries out peak value searching, obtains thick frequency deviation information, and exports to calculating frequency deviation module；
S2435: calculate frequency deviation module and thick frequency deviation information is calculated, it may be judged whether need to proceed to correct:
(1) if the thick frequency deviation message that obtains of follow-up FFT several times is close, peak value is enough, then result be sequentially output after numerical control oscillation module and orthogonal frequency mixing module, be directly output to narrow-band filtering module；Described peak value enough refers to peak value and reaches detection threshold；
(2), in the case of other, it is believed that system step-out, result is sequentially output after numerical control oscillation module, orthogonal frequency mixing module and elimination modulation intelligence module, returns step S2432.
A kind of air-ground narrow band communication method for unmanned plane the most according to claim 3, it is characterised in that: described step S244 includes following sub-step:
S2441: gardner bit timing estimation error will be carried out from thick frequency offset correction module input data, and obtain instantaneous error value；
S2442: loop filter filters high-frequency noise；
S2443: drive digital controlled oscillation circuit to produce timing interpolation and enable and interpolated parameter；
S2444: data are timed interpolation, obtains bit decision point accurately；
S2445: by output buffer output result to frequency deviation synchronization module.
A kind of air-ground narrow band communication method for unmanned plane the most according to claim 3, it is characterised in that: described step S246 includes following sub-step:
S2461: orthogonal mixting circuit carries out orthogonal mixing to from narrow-band filtering input signal, outputs signal to phase error estimation and phase error circuit；
S2462: phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit；
S2463: loop filter circuit is filtered, output is to digital controlled oscillation circuit；
S2464: digital controlled oscillation circuit outputs signal to orthogonal mixting circuit, and described digital controlled oscillation circuit uses DDS algorithm；
S2465: orthogonal mixting circuit outputs signal to decoding/judging module.
A kind of air-ground narrow band communication method for unmanned plane the most according to claim 3, it is characterised in that: described step S249 includes following sub-step:
S2491: data buffering module receives the data from de-interleaving block input and clock, outputs signal to buffering capacity detection module；
S2492: the buffering capacity of data buffer module is monitored by buffering capacity detection module, outputs signal to loop filtering module simultaneously；
S2493: after loop filtering module is filtered, outputs signal to numerical control oscillation module；
S2494: numerical control oscillation module has two-way to export, a road output clock, a road output signal controls data buffering module；
S2495: data buffering module output data.
A kind of air-ground narrow band communication method for unmanned plane the most according to claim 1, it is characterized in that: described Receiver Module is identical with radiofrequency emitting module structure, including duplexer, transmitting terminal processing module, receiving terminal processing module and driving module, described duplexer is used for receiving and sending data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, drives the output of module to be connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described driving module includes crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way output of merit sub-module is connected with two drive amplification modules respectively, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；The control code of the input input 5bit of described driver；
Described transmission
End processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel input of frequency mixing module is intermediate-freuqncy signal, another road input of frequency mixing module is connected with driving one of them the drive amplification module in module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driving module is all connected with numerical control attenuation module, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and another drive amplification module of driving module is all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, amplification module output signal.
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