CN104393885B - A kind of reception terminal for unmanned plane ground-to-air wideband communication system and method thereof - Google Patents
A kind of reception terminal for unmanned plane ground-to-air wideband communication system and method thereof Download PDFInfo
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Abstract
The invention discloses a kind of reception terminal for unmanned plane ground-to-air wideband communication system and method thereof, it includes Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives signal of communication and the control signal from FPGA, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected by ADC with FPGA, the gain control output of FPGA is connected with Receiver Module, FPGA also demodulated output data, described FPGA includes down conversion module, AGC control module, decimal abstraction module, matched filtering module, bit sync module, frequency deviation synchronization module, frequency domain equalization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module.The present invention to can remote measurement, remote control, number pass unmanned plane system and method in air-ground wideband signal communication subsystem and method carry out perfect, be simultaneously suitable for handheld terminal and the car-mounted terminal on ground.
Description
Technical field
The present invention relates to a kind of reception terminal for unmanned plane ground-to-air wideband communication system and method thereof.
Background technology
Unmanned plane has that cost effectiveness is low, zero injures and deaths and dispose the advantage such as flexibly, can help even to replace the mankind to play a role in a lot of scenes, such as the personnel's search and rescue after calamity, infrastructure supervision etc..No matter in civilian or military domain, unmanned plane all has wide application and development prospect.
The system of unmanned plane that passes of remote measurement, remote control, number can include Air-Ground two-way communication and ground-ground two-way communication two parts, divide according to wire data type, wideband signal communication can be divided into communicate with narrow band signal two types, wherein broadband signal is unmanned plane reconnaissance image data transmission service and unmanned plane telemetry service, narrow band signal is underwater acoustic remote control business between handheld terminal and unmanned plane, communication service between handheld terminal and car-mounted terminal.And a link critically important in broadband connections is exactly its reception terminal, receives terminal and include handheld terminal and car-mounted terminal.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, it is provided that a kind of signal transacting is accurately for reception terminal and the method thereof of unmanned plane ground-to-air wideband communication system.
It is an object of the invention to be achieved through the following technical solutions: a kind of reception terminal for unmanned plane ground-to-air wideband communication system, it includes Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the signal of communication from outside and the control signal from FPGA, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control output of FPGA is connected with ADC, the gain control output of FPGA is connected with Receiver Module, FPGA is also by internal interface demodulated output data；
nullDescribed FPGA includes down conversion module、AGC control module、Decimal abstraction module、Matched filtering module、Bit sync module、Frequency deviation synchronization module、Frequency domain equalization module、Decoding/judging module、De-interleaving block and at the uniform velocity buffer module，The input of down conversion module is connected with ADC，The output of down conversion module is connected with AGC control module，The gain control output point of AGC control module is connected with Receiver Module，The conciliation output of AGC control module is connected with decimal abstraction module，The output of decimal abstraction module is connected with matched filtering module，The output of matched filtering module is connected with bit sync module，The output of bit sync module is connected with frequency deviation synchronization module，The output of frequency deviation synchronization module is connected with frequency domain equalization module，The output of frequency domain equalization module is connected with decoding/judging module，The output of decoding/judging module is connected with de-interleaving block，The output of de-interleaving block is connected with at the uniform velocity buffer module，The at the uniform velocity output of buffer module exports demodulation gain by internal interface.
Described down conversion module includes orthogonal mixting circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of orthogonal mixting circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, orthogonal mixting circuit output I, Q two paths of signals is to low-pass filter circuit, and low-pass filter circuit output I, Q two paths of signals is to AGC control module.Digital controlled oscillation circuit uses cordic algorithm to realize, and only consumes a small amount of register and adder resource, does not consume RAM, and resource loss is substantially negligible to be disregarded.
Described AGC control module exports AGC gain control signal to Receiver Module, and AGC control module also exports baseband signal to decimal abstraction module.Because native system is non-high-speed cruise, so the change of signal power is relatively slower, judge that the circuit structure returning again to control radio frequency can meet the reception power control requirements of native system by FPGA.
The baseband signal that down coversion and AGC are controlled to obtain by described decimal abstraction module carries out little several times extraction, and output signal sample value is to matched filtering module.
nullDescribed bit sync module includes inputting buffer module、Reg module、Timing error estimate module、Loop filter、Digital controlled oscillation circuit、Regularly interpolation module、Output buffer module and two shift registers，The input of input buffer module is connected with matched filtering module，The output of input buffer module is connected with reg module，The output of reg module is connected with one of them shift register，The output of this shift register is connected with timing interpolation module，Regularly a road output of interpolation module is connected with another shift register，The output of this shift register is connected with timing error module，The output of Timing error estimate module is connected with loop filter，The output of loop filter is connected with digital controlled oscillation circuit，The output of digital controlled oscillation circuit is connected with timing interpolation module，Regularly another road output of interpolation module is by output buffer module output data.Bit synchronization uses Gardner algorithm, to a small amount of residual frequency deviation insensitive (according to 3kHz maximum frequency deviation, about 4.5Mbaud/s baud rate is calculated, and residual frequency deviation is about about the 0.1% of chip rate), before may be located at frequency synchronization module.After input data carry out little several times interpolation/extraction, obtain the signal of 4 times of symbol sampler rates；4 times of sample value signals are carried out gardner bit timing estimation error, obtains instantaneous error value, after filtering high-frequency noise by loop filter, drive NCO to produce timing interpolation and enable and interpolated parameter；" Farrow timing interpolation " module uses farrow structure, and interpolation obtains bit decision point accurately, eventually through output Buffer output；Described Farrow structure is that a kind of efficient polynomial interpolation realizes structure.
Described frequency deviation synchronization module includes orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way connects with orthogonal mixting circuit, the output of orthogonal mixting circuit is connected with phase error estimation and phase error circuit and frequency domain equalization circuit respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit.The realization of described digital controlled oscillation circuit uses DDS algorithm, rather than cordic algorithm, because the sequential amount of delay of cordic logic is bigger in FPGA, cause loop delay big, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, it is ensured that loop capturing behavior and the performance of the behavior of tracking.
nullDescribed frequency domain equalization module includes three i.e. FFT1 of FFT module、FFT2 and FFT3、Two i.e. IFFT1 and IFFT2 of IFFT module、Unique word search module、Channel estimation module、Local unique word module、Mend 0 module and channel equalization module，Input signal is connected with FFT1 and unique word search module respectively，The output of local keyword module is connected with FFT2，Unique word search module、The output of FFT1 and FFT2 is connected with channel estimation module，The output of channel estimation module is connected with IFFT1，The output of IFFT1 is connected with mending 0 module，The output mending 0 module is connected with FFT3 module，The output of FFT1 and FFT3 is connected with channel equalization module，Channel equalization module is connected with IFFT2，IFFT2 output signal.
For downlink, counting channel error correction, frame structure loss etc. in, information rate is higher, reaches about 10Mbps, and multidiameter is more than ten code elements, so it is also contemplated that channel equalization.If using traditional single carrier wave time domain to equalize, when the number of symbols that multipath delay exceedes is more, the exponent number taking out sef-adapting filter can be caused excessive, thus computing is complicated and affects the sequential handling capacity of logic circuit.Native system uses up-to-date channel equalization technique SCFDE (single carrier frequency domain equalization) to solve multi-path jamming.SCFDE and OFDM(OFDM) it is all on frequency domain, carry out channel estimation and equilibrium, compared to traditional single carrier wave time domain equilibrium, there is higher computational efficiency and equalization performance, have become as the focus of current communication system, and the balancing technique scheme communicated as IEEE802.16 with 4G.And SCFDE is compared to OFDM, has the advantage that (1) SCFDE can overcome the too high problem of OFDM technology PAR (papr), thus transmitting terminal can use the RF power amplifier of low cost；(2) SCFDE can overcome OFDM technology weakness more sensitive to deviation ratio, more relatively reliable than OFDM in high-speed aircraft communicates；(3) although SCFDE with OFDM is at signal link operational model similar (there is IFFT and FFT), but the IFFT of OFDM is placed on transmitting terminal, and IFFT and FFT of SCFDE is at receiving terminal, so air carrier can consume less hardware resource as transmitting terminal, very good for the miniaturization and optimised power consumption of transmitting terminal.(4) SCFDE is not in the case of using channel coding, unlike OFDM can be damaged by frequency selective fading.
Described decoding/judging module uses Viterbi soft-decision algorithm, and described de-interleaving block is used for realizing simply buffering read-write.
Described at the uniform velocity buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel output of data buffering module is connected with buffering capacity monitoring modular, another road output output data of data buffering module, the output of buffering capacity monitoring modular is connected with loop filtering module, the output of loop filtering module is connected with numerical control oscillation module, one tunnel output of numerical control oscillation module is connected with data buffering module, another road output clock signal of numerical control oscillation module.
Described Receiver Module includes duplexer, transmitting terminal processing module, receiving terminal processing module and drives module, being used for of described duplexer receives and sends data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, drives the output of module to be connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described driving module includes crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way output of merit sub-module is connected with two drive amplification modules respectively, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel input of frequency mixing module is intermediate-freuqncy signal, another road input of frequency mixing module is connected with driving one of them the drive amplification module in module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driving module is all connected with numerical control attenuation module, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and another drive amplification module of driving module is all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, amplification module output signal.
It also includes a clock, and the output of described clock is connected with FPGA and ADC respectively.
A kind of reception terminal method for unmanned plane ground-to-air wideband communication system, it comprises the following steps:
S1: Receiver Module accepts the signal of communication from outside and the gain control signal from FPGA, is sent to intermediate frequency filtering module after conversion；
S2: the intermediate frequency filtering module signal to inputting from Receiver Module carries out intermediate frequency filtering, and is sent to ADC；
S3:ADC receives the signal from the output of intermediate frequency filtering module, is sent to FPGA after conversion；
After signal is processed by S4:FPGA, exporting condition data by internal interface, FPGA is also to Receiver Module outputing gain control signal.
Described step S4 includes following sub-step:
Down conversion module in S401:FPGA carries out down-converted to the input from ADC, and exports to AGC control module；
S402:AGC control module is done adaptive power according to the power of signal and is controlled, and outputing gain control signal is to Receiver Module, and output simultaneously reconciles signal to decimal abstraction module；
S403: the decimal abstraction module baseband signal to receiving carries out little several times extraction, and output signal sample value is to matched filtering module；
S404: matched filtering module enters matched filtering to input signal, and exports to bit sync module；
S405: bit sync module carries out bit synchronization process to input signal, outputs signal to frequency deviation synchronization module；
S406: frequency deviation synchronization module uses digital phase-locked loop to carry out carrier synchronization, completes basic synchronous demodulation, outputs signal to frequency domain equalization module；
S407: frequency domain equalization module converts the signal into frequency domain and carries out channel estimation and equilibrium, switches back to time domain again, output signal to decoding/judging module after having equalized；
S408: decoding/judging module receives signal and carries out folding coding, it is ensured that overall demodulation signal to noise ratio, and exports to de-interleaving block；
S409: de-interleaving block carries out buffering read-write, exports signal at the uniform velocity buffer module afterwards；
S410: demodulating data is at the uniform velocity exported by the uniform velocity buffer module by internal interface.
Described step S401 includes following sub-step:
S4011: orthogonal mixting circuit receives the input from ADC and the input of digital controlled oscillation circuit, output I, Q two paths of signals to low-pass filter circuit, and described digital controlled oscillation circuit uses cordic algorithm；
S4012: low-pass filtering module exports to AGC module after input signal is carried out LPF.
Described step S405 includes following sub-step:
S4051: gardner bit timing estimation error will be carried out from matched filtering module input data, and obtain instantaneous error value；
S4052: loop filter filters high-frequency noise；
S4053: drive digital controlled oscillation circuit to produce timing interpolation and enable and interpolated parameter；
S4054: data are timed interpolation, obtains bit decision point accurately；
S4055: by output buffer output result to frequency deviation synchronization module.
Described step S406 includes following sub-step:
S4061: orthogonal mixting circuit carries out orthogonal mixing to from bit sync module input signal, outputs signal to phase error estimation and phase error circuit；
S4062: phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit；
S4063: loop filter circuit is filtered, output is to digital controlled oscillation circuit；
S4064: digital controlled oscillation circuit outputs signal to orthogonal mixting circuit, and described digital controlled oscillation circuit uses DDS algorithm；
S4065: orthogonal mixting circuit outputs signal to frequency domain equalization module.
Described step S407 includes following sub-step:
The signal of S4071: frequency deviation synchronization module input is separately input into the first fft circuit and unique word search module；
S4072: local unique word module output signal is to the second fft circuit；
S4073: the first fft circuit, the second fft circuit and unique word search module output signal to channel estimation module simultaneously and carry out channel estimation；
S4074: channel estimation module outputs signal to an IFFT circuit；
S4075: the one IFFT circuit output signal is to mending 0 module；
S4076: mend 0 module output signal to the 3rd fft circuit；
S4077: the first fft circuit and the 3rd fft circuit output signal to channel equalization module simultaneously and carry out channel equalization；
S4078: channel equalization module passes through the 2nd IFFT circuit output signal to decoding/judging module.
Described step S410 includes following sub-step:
S4101: data buffering module receives the data from de-interleaving block input and clock, outputs signal to buffering capacity detection module；
S4102: the buffering capacity of data buffer module is monitored by buffering capacity detection module, outputs signal to loop filtering module simultaneously；
S4103: after loop filtering module is filtered, outputs signal to numerical control oscillation module；
S4104: numerical control oscillation module has two-way to export, a road output clock, a road output signal controls data buffering module；
S4105: data buffering module output data.
The invention has the beneficial effects as follows: the signal of (1) ADC input obtains baseband signal through down coversion, digital controlled oscillation circuit in down coversion uses cordic algorithm to realize, only consuming a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible to be disregarded；(2) baseband signal carries out little several times extraction, obtains the signal sample of 4 times of chip rates, then carries out matched filtering, advantage of this is that the calculating being beneficially molded matched filter coefficient；(3) signal after coupling enters bit synchronization and frequency deviation synchronization module, complete basic synchronous demodulation, owing to after DDC, residual frequency deviation is about the 0.1% of chip rate, the receiving algorithm of frequency deviation synchronization module is without considering that thick frequency deviation synchronizes, directly carry out essence frequency offset tracking, the realization of the digital controlled oscillation circuit in essence frequency offset tracking uses DDS, rather than cordic algorithm, because the sequential amount of delay of cordic logic is bigger in FPGA, cause loop delay big, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, can ensure that loop capturing behavior and the performance of the behavior of tracking；(4) subsequently, use frequency-domain equalization technology to carry out channel uncoiling, then carry out bit decision, ensure overall demodulation signal to noise ratio, frequency domain equalization uses single-carrier wave frequency domain equalization technology, converts the signal into frequency domain and carries out channel estimation and equilibrium, switches back to time domain after having equalized again；(5) bit information after judgement is through channel decoding, obtains the result after error correction, and in order to support the precise time label of remote measurement, demodulating data will at the uniform velocity export；(6) due to above some, the present invention be just applicable to a kind of can the reception terminal of ground-to-air wideband communication system of unmanned plane that passes of remote measurement, remote control, number and method thereof, receive terminal and include handheld terminal and car-mounted terminal.
Accompanying drawing explanation
Fig. 1 is present configuration block diagram；
Fig. 2 is FPGA function module structure chart；
Fig. 3 is down conversion module structure chart；
Fig. 4 is bit sync module structure chart；
Fig. 5 is Farrow structured flowchart；
Fig. 6 is frequency deviation synchronization module structure chart；
Fig. 7 is frequency domain equalization function structure chart；
Fig. 8 is at the uniform velocity buffer module structure chart；
Fig. 9 is radio frequency receiving block structural diagram；
Figure 10 is the inventive method flow chart.
Detailed description of the invention
Technical scheme is described in further detail below in conjunction with the accompanying drawings: as shown in Figure 1, a kind of reception terminal for unmanned plane ground-to-air wideband communication system, it includes Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the signal of communication from outside and the control signal from FPGA, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control output of FPGA is connected with ADC, the gain control output of FPGA is connected with Receiver Module, FPGA is also by internal interface demodulated output data；
nullAs shown in Figure 2，Described FPGA includes down conversion module、AGC control module、Decimal abstraction module、Matched filtering module、Bit sync module、Frequency deviation synchronization module、Frequency domain equalization module、Decoding/judging module、De-interleaving block and at the uniform velocity buffer module，The input of down conversion module is connected with ADC，The output of down conversion module is connected with AGC control module，The gain control output point of AGC control module is connected with Receiver Module，The conciliation output of AGC control module is connected with decimal abstraction module，The output of decimal abstraction module is connected with matched filtering module，The output of matched filtering module is connected with bit sync module，The output of bit sync module is connected with frequency deviation synchronization module，The output of frequency deviation synchronization module is connected with frequency domain equalization module，The output of frequency domain equalization module is connected with decoding/judging module，The output of decoding/judging module is connected with de-interleaving block，The output of de-interleaving block is connected with at the uniform velocity buffer module，The at the uniform velocity output of buffer module exports demodulation gain by internal interface.
As shown in Figure 3, described down conversion module includes orthogonal mixting circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of orthogonal mixting circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, orthogonal mixting circuit output I, Q two paths of signals is to low-pass filter circuit, and low-pass filter circuit output I, Q two paths of signals is to AGC control module.Digital controlled oscillation circuit uses cordic algorithm to realize, and only consumes a small amount of register and adder resource, does not consume RAM, and resource loss is substantially negligible to be disregarded.
Described AGC control module exports AGC gain control signal to Receiver Module, and AGC control module also exports baseband signal to decimal abstraction module.Because native system is non-high-speed cruise, so the change of signal power is relatively slower, judge that the circuit structure returning again to control radio frequency can meet the reception power control requirements of native system by FPGA.
The baseband signal that down coversion and AGC are controlled to obtain by described decimal abstraction module carries out little several times extraction, and output signal sample value is to matched filtering module.
nullAs shown in Figure 4，Described bit sync module includes inputting buffer module、Reg module、Timing error estimate module、Loop filter、Digital controlled oscillation circuit、Regularly interpolation module、Output buffer module and two shift registers，The input of input buffer module is connected with matched filtering module，The output of input buffer module is connected with reg module，The output of reg module is connected with one of them shift register，The output of this shift register is connected with timing interpolation module，Regularly a road output of interpolation module is connected with another shift register，The output of this shift register is connected with timing error module，The output of Timing error estimate module is connected with loop filter，The output of loop filter is connected with digital controlled oscillation circuit，The output of digital controlled oscillation circuit is connected with timing interpolation module，Regularly another road output of interpolation module is by output buffer module output data.Bit synchronization uses Gardner algorithm, to a small amount of residual frequency deviation insensitive (according to 3kHz maximum frequency deviation, about 4.5Mbaud/s baud rate is calculated, and residual frequency deviation is about about the 0.1% of chip rate), before may be located at frequency synchronization module.After input data carry out little several times interpolation/extraction, obtain the signal of 4 times of symbol sampler rates；4 times of sample value signals are carried out gardner bit timing estimation error, obtains instantaneous error value, after filtering high-frequency noise by loop filter, drive NCO to produce timing interpolation and enable and interpolated parameter；" Farrow timing interpolation " module uses farrow structure, and interpolation obtains bit decision point accurately, eventually through output Buffer output；Described Farrow structure is that a kind of efficient polynomial interpolation realizes structure, as shown in Figure 5.
As shown in Figure 6, described frequency deviation synchronization module includes orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way connects with orthogonal mixting circuit, the output of orthogonal mixting circuit is connected with phase error estimation and phase error circuit and frequency domain equalization circuit respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit.The realization of described digital controlled oscillation circuit uses DDS algorithm, rather than cordic algorithm, because the sequential amount of delay of cordic logic is bigger in FPGA, cause loop delay big, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, it is ensured that loop capturing behavior and the performance of the behavior of tracking.
nullAs shown in Figure 7，Described frequency domain equalization module includes three i.e. FFT1 of FFT module、FFT2 and FFT3、Two i.e. IFFT1 and IFFT2 of IFFT module、Unique word search module、Channel estimation module、Local unique word module、Mend 0 module and channel equalization module，Input signal is connected with FFT1 and unique word search module respectively，The output of local keyword module is connected with FFT2，Unique word search module、The output of FFT1 and FFT2 is connected with channel estimation module，The output of channel estimation module is connected with IFFT1，The output of IFFT1 is connected with mending 0 module，The output mending 0 module is connected with FFT3 module，The output of FFT1 and FFT3 is connected with channel equalization module，Channel equalization module is connected with IFFT2，IFFT2 output signal.
For downlink, counting channel error correction, frame structure loss etc. in, information rate is higher, reaches about 10Mbps, and multidiameter is more than ten code elements, so it is also contemplated that channel equalization.If using traditional single carrier wave time domain to equalize, when the number of symbols that multipath delay exceedes is more, the exponent number taking out sef-adapting filter can be caused excessive, thus computing is complicated and affects the sequential handling capacity of logic circuit.Native system uses up-to-date channel equalization technique SCFDE (single carrier frequency domain equalization) to solve multi-path jamming.SCFDE and OFDM(OFDM) it is all on frequency domain, carry out channel estimation and equilibrium, compared to traditional single carrier wave time domain equilibrium, there is higher computational efficiency and equalization performance, have become as the focus of current communication system, and the balancing technique scheme communicated as IEEE802.16 with 4G.And SCFDE is compared to OFDM, has the advantage that (1) SCFDE can overcome the too high problem of OFDM technology PAR (papr), thus transmitting terminal can use the RF power amplifier of low cost；(2) SCFDE can overcome OFDM technology weakness more sensitive to deviation ratio, more relatively reliable than OFDM in high-speed aircraft communicates；(3) although SCFDE with OFDM is at signal link operational model similar (there is IFFT and FFT), but the IFFT of OFDM is placed on transmitting terminal, and IFFT and FFT of SCFDE is at receiving terminal, so air carrier can consume less hardware resource as transmitting terminal, very good for the miniaturization and optimised power consumption of transmitting terminal.(4) SCFDE is not in the case of using channel coding, unlike OFDM can be damaged by frequency selective fading.
Described decoding/judging module uses Viterbi soft-decision algorithm, and described de-interleaving block is used for realizing simply buffering read-write.
As shown in Figure 8, described at the uniform velocity buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel output of data buffering module is connected with buffering capacity monitoring modular, another road output output data of data buffering module, the output of buffering capacity monitoring modular is connected with loop filtering module, the output of loop filtering module is connected with numerical control oscillation module, one tunnel output of numerical control oscillation module is connected with data buffering module, another road output clock signal of numerical control oscillation module.
As shown in Figure 9, described Receiver Module includes duplexer, transmitting terminal processing module, receiving terminal processing module and drives module, being used for of described duplexer receives and sends data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, drives the output of module to be connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described driving module includes crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way output of merit sub-module is connected with two drive amplification modules respectively, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel input of frequency mixing module is intermediate-freuqncy signal, another road input of frequency mixing module is connected with driving one of them the drive amplification module in module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driving module is all connected with numerical control attenuation module, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and another drive amplification module of driving module is all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, amplification module output signal.
Receive passage, 1520 ± 40MHz(downlink telemetry/picture signal) signal through low noise amplify post filtering amplify again, be mixed to 160 ± 4MHz intermediate frequency.Exporting after being amplified by intermediate frequency, power output is-5dBm～0dBm.
It also includes a clock, and the output of described clock is connected with FPGA and ADC respectively.
As shown in Figure 10, a kind of reception terminal method for unmanned plane ground-to-air wideband communication system, it comprises the following steps:
S1: Receiver Module accepts the signal of communication from outside and the gain control signal from FPGA, is sent to intermediate frequency filtering module after conversion；
S2: the intermediate frequency filtering module signal to inputting from Receiver Module carries out intermediate frequency filtering, and is sent to ADC；
S3:ADC receives the signal from the output of intermediate frequency filtering module, is sent to FPGA after conversion；
After signal is processed by S4:FPGA, exporting condition data by internal interface, FPGA is also to Receiver Module outputing gain control signal.
Described step S4 includes following sub-step:
Down conversion module in S401:FPGA carries out down-converted to the input from ADC, and exports to AGC control module；
S402:AGC control module is done adaptive power according to the power of signal and is controlled, and outputing gain control signal is to Receiver Module, and output simultaneously reconciles signal to decimal abstraction module；
S403: the decimal abstraction module baseband signal to receiving carries out little several times extraction, and output signal sample value is to matched filtering module；
S404: matched filtering module enters matched filtering to input signal, and exports to bit sync module；
S405: bit sync module carries out bit synchronization process to input signal, outputs signal to frequency deviation synchronization module；
S406: frequency deviation synchronization module uses digital phase-locked loop to carry out carrier synchronization, completes basic synchronous demodulation, outputs signal to frequency domain equalization module；
S407: frequency domain equalization module converts the signal into frequency domain and carries out channel estimation and equilibrium, switches back to time domain again, output signal to decoding/judging module after having equalized；
S408: decoding/judging module receives signal and carries out folding coding, it is ensured that overall demodulation signal to noise ratio, and exports to de-interleaving block；
S409: de-interleaving block carries out buffering read-write, exports signal at the uniform velocity buffer module afterwards；
S410: demodulating data is at the uniform velocity exported by the uniform velocity buffer module by internal interface.
Described step S401 includes following sub-step:
S4011: orthogonal mixting circuit receives the input from ADC and the input of digital controlled oscillation circuit, output I, Q two paths of signals to low-pass filter circuit, and described digital controlled oscillation circuit uses cordic algorithm；
S4012: low-pass filtering module exports to AGC module after input signal is carried out LPF.
Described step S405 includes following sub-step:
S4051: gardner bit timing estimation error will be carried out from matched filtering module input data, and obtain instantaneous error value；
S4052: loop filter filters high-frequency noise；
S4053: drive digital controlled oscillation circuit to produce timing interpolation and enable and interpolated parameter；
S4054: data are timed interpolation, obtains bit decision point accurately；
S4055: by output buffer output result to frequency deviation synchronization module.
Described step S406 includes following sub-step:
S4061: orthogonal mixting circuit carries out orthogonal mixing to from bit sync module input signal, outputs signal to phase error estimation and phase error circuit；
S4062: phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit；
S4063: loop filter circuit is filtered, output is to digital controlled oscillation circuit；
S4064: digital controlled oscillation circuit outputs signal to orthogonal mixting circuit, and described digital controlled oscillation circuit uses DDS algorithm；
S4065: orthogonal mixting circuit outputs signal to frequency domain equalization module.
Described step S407 includes following sub-step:
The signal of S4071: frequency deviation synchronization module input is separately input into the first fft circuit and unique word search module；
S4072: local unique word module output signal is to the second fft circuit；
S4073: the first fft circuit, the second fft circuit and unique word search module output signal to channel estimation module simultaneously and carry out channel estimation；
S4074: channel estimation module outputs signal to an IFFT circuit；
S4075: the one IFFT circuit output signal is to mending 0 module；
S4076: mend 0 module output signal to the 3rd fft circuit；
S4077: the first fft circuit and the 3rd fft circuit output signal to channel equalization module simultaneously and carry out channel equalization；
S4078: channel equalization module passes through the 2nd IFFT circuit output signal to decoding/judging module.
Described step S410 includes following sub-step:
S4101: data buffering module receives the data from de-interleaving block input and clock, outputs signal to buffering capacity detection module；
S4102: the buffering capacity of data buffer module is monitored by buffering capacity detection module, outputs signal to loop filtering module simultaneously；
S4103: after loop filtering module is filtered, outputs signal to numerical control oscillation module；
S4104: numerical control oscillation module has two-way to export, a road output clock, a road output signal controls data buffering module；
S4105: data buffering module output data.
Claims (9)
1. the reception terminal for unmanned plane ground-to-air wideband communication system, it is characterized in that: it includes Receiver Module, intermediate frequency filtering module, ADC and FPGA, the gain control that Receiver Module receives from outside signal of communication and from FPGA exports, the output of Receiver Module is connected with intermediate frequency filtering module, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control output of FPGA is connected with ADC, the gain control output of FPGA is connected with Receiver Module, and FPGA is also by internal interface demodulated output data；
nullDescribed FPGA includes down conversion module、AGC control module、Decimal abstraction module、Matched filtering module、Bit sync module、Frequency deviation synchronization module、Frequency domain equalization module、Decoding/judging module、De-interleaving block and at the uniform velocity buffer module，The input of down conversion module is connected with ADC，The output of down conversion module is connected with AGC control module，The gain control output point of AGC control module is connected with Receiver Module，The conciliation output of AGC control module is connected with decimal abstraction module，The output of decimal abstraction module is connected with matched filtering module，The output of matched filtering module is connected with bit sync module，The output of bit sync module is connected with frequency deviation synchronization module，The output of frequency deviation synchronization module is connected with frequency domain equalization module，The output of frequency domain equalization module is connected with decoding/judging module，The output of decoding/judging module is connected with de-interleaving block，The output of de-interleaving block is connected with at the uniform velocity buffer module，The at the uniform velocity output of buffer module exports demodulation gain by internal interface.
A kind of reception terminal for unmanned plane ground-to-air wideband communication system the most according to claim 1, it is characterized in that: described down conversion module includes orthogonal mixting circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of orthogonal mixting circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, orthogonal mixting circuit output I, Q two paths of signals is to low-pass filter circuit, low-pass filter circuit output I, Q two paths of signals uses cordic algorithm to AGC control module, described digital controlled oscillation circuit；
nullDescribed bit sync module includes inputting buffer module、Register module、Timing error estimate module、Loop filter、Digital controlled oscillation circuit、Regularly interpolation module、Output buffer module and two shift registers，The input of input buffer module is connected with matched filtering module，The output of input buffer module is connected with register module，The output of register module is connected with one of them shift register，The output of this shift register is connected with timing interpolation module，Regularly a road output of interpolation module is connected with another shift register，The output of this shift register is connected with timing error module，The output of Timing error estimate module is connected with loop filter，The output of loop filter is connected with digital controlled oscillation circuit，The output of digital controlled oscillation circuit is connected with timing interpolation module，Regularly another road output of interpolation module is by output buffer module output data；
Described frequency deviation synchronization module includes orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, orthogonal mixting circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way connects with orthogonal mixting circuit, the output of orthogonal mixting circuit is connected with phase error estimation and phase error circuit and frequency domain equalization circuit respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit connects with orthogonal mixting circuit, described digital controlled oscillation circuit practicality DDS algorithm；
nullDescribed frequency domain equalization module includes three i.e. FFT1 of FFT module、FFT2 and FFT3、Two i.e. IFFT1 and IFFT2 of IFFT module、Unique word search module、Channel estimation module、Local unique word module、Mend 0 module and channel equalization module，Input signal is connected with FFT1 and unique word search module respectively，The output of local keyword module is connected with FFT2，Unique word search module、The output of FFT1 and FFT2 is connected with channel estimation module，The output of channel estimation module is connected with IFFT1，The output of IFFT1 is connected with mending 0 module，The output mending 0 module is connected with FFT3 module，The output of FFT1 and FFT3 is connected with channel equalization module，Channel equalization module is connected with IFFT2，IFFT2 output signal；
Described at the uniform velocity buffer module includes data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel output of data buffering module is connected with buffering capacity monitoring modular, another road output output data of data buffering module, the output of buffering capacity monitoring modular is connected with loop filtering module, the output of loop filtering module is connected with numerical control oscillation module, one tunnel output of numerical control oscillation module is connected with data buffering module, another road output clock signal of numerical control oscillation module.
A kind of reception terminal for unmanned plane ground-to-air wideband communication system the most according to claim 1, it is characterized in that: described Receiver Module includes duplexer, transmitting terminal processing module, receiving terminal processing module and drives module, being used for of described duplexer receives and sends data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, drives the output of module to be connected with transmitting terminal processing module and receiving terminal processing module respectively；
Described driving module includes crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way output of merit sub-module is connected with two drive amplification modules respectively, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes；
Described transmitting terminal processing module includes frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel input of frequency mixing module is intermediate-freuqncy signal, another road input of frequency mixing module is connected with driving one of them the drive amplification module in module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driving module is all connected with numerical control attenuation module, the output of numerical control attenuation module is connected with driving amplification module, the output driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer；
Described receiving terminal processing module includes low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and another drive amplification module of driving module is all connected with frequency mixing module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, amplification module output signal.
4. the reception terminal method for unmanned plane ground-to-air wideband communication system, it is characterised in that: it comprises the following steps:
S1: Receiver Module accepts the signal of communication from outside and the gain control signal from FPGA, is sent to intermediate frequency filtering module after conversion；
S2: the intermediate frequency filtering module signal to inputting from Receiver Module carries out intermediate frequency filtering, and is sent to ADC；
S3:ADC receives the signal from the output of intermediate frequency filtering module, is sent to FPGA after conversion；
After signal is processed by S4:FPGA, exporting condition data by internal interface, FPGA is also to Receiver Module outputing gain control signal；
Described step S4 includes following sub-step:
Down conversion module in S401:FPGA carries out down-converted to the input from ADC, and exports to AGC control module；
S402:AGC control module is done adaptive power according to the power of signal and is controlled, and outputing gain control signal is to Receiver Module, and output simultaneously reconciles signal to decimal abstraction module；
S403: the decimal abstraction module baseband signal to receiving carries out little several times extraction, and output signal sample value is to matched filtering module；
S404: matched filtering module enters matched filtering to input signal, and exports to bit sync module；
S405: bit sync module carries out bit synchronization process to input signal, outputs signal to frequency deviation synchronization module；
S406: frequency deviation synchronization module uses digital phase-locked loop to carry out carrier synchronization, completes basic synchronous demodulation, outputs signal to frequency domain equalization module；
S407: frequency domain equalization module converts the signal into frequency domain and carries out channel estimation and equilibrium, switches back to time domain again, output signal to decoding/judging module after having equalized；
S408: decoding/judging module receives signal and carries out folding coding, it is ensured that overall demodulation signal to noise ratio, and exports to de-interleaving block；
S409: de-interleaving block carries out buffering read-write, exports signal at the uniform velocity buffer module afterwards；
S410: demodulating data is at the uniform velocity exported by the uniform velocity buffer module by internal interface.
A kind of reception terminal method for unmanned plane ground-to-air wideband communication system the most according to claim 4, it is characterised in that: described step S401 includes following sub-step:
S4011: orthogonal mixting circuit receives the input from ADC and the input of digital controlled oscillation circuit, output I, Q two paths of signals to low-pass filter circuit, and described digital controlled oscillation circuit uses cordic algorithm；
S4012: low-pass filtering module exports to AGC module after input signal is carried out LPF.
A kind of reception terminal method for unmanned plane ground-to-air wideband communication system the most according to claim 4, it is characterised in that: described step S405 includes following sub-step:
S4051: gardner bit timing estimation error will be carried out from matched filtering module input data, and obtain instantaneous error value；
S4052: loop filter filters high-frequency noise；
S4053: drive digital controlled oscillation circuit to produce timing interpolation and enable and interpolated parameter；
S4054: data are timed interpolation, obtains bit decision point accurately；
S4055: by output buffer output result to frequency deviation synchronization module.
A kind of reception terminal method for unmanned plane ground-to-air wideband communication system the most according to claim 4, it is characterised in that: described step S406 includes following sub-step:
S4061: orthogonal mixting circuit carries out orthogonal mixing to from bit sync module input signal, outputs signal to phase error estimation and phase error circuit；
S4062: phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit；
S4063: loop filter circuit is filtered, output is to digital controlled oscillation circuit；
S4064: digital controlled oscillation circuit outputs signal to orthogonal mixting circuit, and described digital controlled oscillation circuit uses DDS algorithm；
S4065: orthogonal mixting circuit outputs signal to frequency domain equalization module.
A kind of reception terminal method for unmanned plane ground-to-air wideband communication system the most according to claim 4, it is characterised in that: described step S407 includes following sub-step:
The signal of S4071: frequency deviation synchronization module input is separately input into the first fft circuit and unique word search module；
S4072: local unique word module output signal is to the second fft circuit；
S4073: the first fft circuit, the second fft circuit and unique word search module output signal to channel estimation module simultaneously and carry out channel estimation；
S4074: channel estimation module outputs signal to an IFFT circuit；
S4075: the one IFFT circuit output signal is to mending 0 module；
S4076: mend 0 module output signal to the 3rd fft circuit；
S4077: the first fft circuit and the 3rd fft circuit output signal to channel equalization module simultaneously and carry out channel equalization；
S4078: channel equalization module passes through the 2nd IFFT circuit output signal to decoding/judging module.
A kind of reception terminal method for unmanned plane ground-to-air wideband communication system the most according to claim 4, it is characterised in that: described step S410 includes following sub-step:
S4101: data buffering module receives the data from de-interleaving block input and clock, outputs signal to buffering capacity detection module；
S4102: the buffering capacity of data buffer module is monitored by buffering capacity detection module, outputs signal to loop filtering module simultaneously；
S4103: after loop filtering module is filtered, outputs signal to numerical control oscillation module；
S4104: numerical control oscillation module has two-way to export, a road output clock, a road output signal controls data buffering module；
S4105: data buffering module output data.
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| CN109412613A (en) * | 2018-10-16 | 2019-03-01 | 湖南迈克森伟电子科技有限公司 | High-speed digital transmission sending device |
| CN109286406B (en) * | 2018-10-16 | 2019-12-13 | 湖南迈克森伟电子科技有限公司 | high-speed data transmission receiving device |
| CN109309512B (en) * | 2018-11-23 | 2023-09-08 | 四川灵通电讯有限公司 | Channel quality test and configuration negotiation device for copper wire transmission system and application method |
| CN110620599B (en) * | 2019-06-27 | 2022-01-18 | 上海航天电子有限公司 | Microminiature unmanned aerial vehicle data link terminal equipment |
| CN111935052B (en) * | 2020-07-23 | 2022-03-08 | 哈尔滨工业大学 | Adaptive carrier and symbol combined synchronization method for QPSK signal |
| CN112532560B (en) * | 2020-12-01 | 2023-01-31 | 四川灵通电讯有限公司 | System for adaptively modulating QAM (quadrature amplitude modulation) modulation mode in copper wire transmission and application method |
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