CN104333393A - Receiving terminal and receiving terminal method for air-ground narrow-band communication system of unmanned aerial vehicle - Google Patents
Receiving terminal and receiving terminal method for air-ground narrow-band communication system of unmanned aerial vehicle Download PDFInfo
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Abstract
The invention discloses a receiving terminal and a receiving terminal method for an air-ground narrow-band communication system of an unmanned aerial vehicle. The air-ground narrow-band communication system comprises a radio frequency receiving module, an intermediate-frequency filtering module, an ADC and an FPGA, the radio frequency receiving module receives communication signals from the outside and control signals from the FPGA, the output of the radio frequency receiving module is connected with the intermediate-frequency filtering module, the output of the intermediate-frequency filtering module is connected with the ADC, the output of the ADC is connected with the FPGA, the gain control output of the FPGA is connected with the radio frequency receiving module, and the FPGA outputs demodulating data through an internal port. The receiving terminal and receiving terminal method for the air-ground narrow-band communication system of the unmanned aerial vehicle can perfect an air-ground narrow-band signal communication sub-system and method of a system and method for the unmanned aerial vehicle capable of realizing remote measurement, remote control and data transmission; the receiving terminal and receiving terminal method for the air-ground narrow-band communication system of the unmanned aerial vehicle are suitable for an aerial unmanned aerial vehicle receiving terminal and method, and the receiving terminal and receiving terminal method have advantages of low resource consumption, precise data treatment and the like.
Description
Technical field
The present invention relates to a kind of receiving terminal for the air-ground narrow-band communication system of unmanned plane and method thereof.
Background technology
Unmanned plane has that cost effectiveness is low, zero injures and deaths and dispose the advantages such as flexible, can help or even replace the mankind to play a role in a lot of scene, as personnel's search and rescue, infrastructure supervision etc. after calamity.No matter in civilian or military domain, unmanned plane all has wide application and development prospect.
The system of unmanned plane that passes of remote measurement, remote control, number can comprise Air-Ground two-way communication and ground-ground two-way communication two parts, divide according to wire data type, wideband signal communication can be divided into communicate with narrow band signal two types, wherein broadband signal is unmanned plane reconnaissance image data transmission service and unmanned plane telemetry service, narrow band signal is underwater acoustic remote control business between handheld terminal and unmanned plane, communication service between handheld terminal and car-mounted terminal.And a link very important in narrow band communication is exactly its receiving terminal and method thereof, receiving terminal comprises unmanned plane terminal.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide that a kind of resource loss is low, data processing is accurately for receiving terminal and the method thereof of the air-ground narrow-band communication system of unmanned plane.
The object of the invention is to be achieved through the following technical solutions: a kind of receiving terminal for the air-ground narrow-band communication system of unmanned plane, it comprises Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the signal of communication from outside and the control signal from FPGA, the output of Receiver Module and intermediate frequency filtering model calling, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control of FPGA exports and is connected with ADC, the gain of FPGA controls to export and is connected with Receiver Module, FPGA is also by internal interface demodulated output data,
Described FPGA comprises down conversion module, decimal abstraction module, thick frequency offset correction module, narrow-band filtering module, bit synchronization module, essence frequency deviation synchronization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module, the input of down conversion module is connected with ADC, the output of down conversion module is connected with decimal abstraction module, the output of decimal abstraction module and thick frequency offset correction model calling, the output of thick frequency offset correction module and narrow-band filtering model calling, the output of narrow-band filtering module and bit synchronization model calling, the output of bit synchronization module is connected with smart frequency deviation synchronization module, the output of essence frequency deviation synchronization module is connected with decoding/judging module, the output of decoding/judging module is connected with de-interleaving block, the output of de-interleaving block is connected with at the uniform velocity buffer module, at the uniform velocity the output of buffer module exports demodulation gain by internal interface.
Described down conversion module comprises quadrature downconvert circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of quadrature downconvert circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, quadrature downconvert circuit exports I, Q two paths of signals to low-pass filter circuit, and low-pass filter circuit exports I, Q two paths of signals to decimal abstraction module.Described digital controlled oscillation circuit uses cordic algorithm, and only consume a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible.
Described decimal abstraction module carries out little several times extraction to the baseband signal that down conversion module obtains, and output signal sample value is to thick frequency offset correction module.
Because after despreading, signal bandwidth only has about 180kHz, and most high-doppler frequency deviation reaches 3kHz, at certain interference situations., frequency deviation may be caught outside band by transnormal phase-locked loop, so carrier synchronization partial resolution is become " thick frequency offset correction " and " smart frequency deviation is synchronous " two links here.
Described thick frequency offset correction module comprises quadrature downconvert circuit, eliminate modulation intelligence circuit, fft circuit, spectral line peak search circuit, calculate frequency deviation circuit and digital controlled oscillation circuit, quadrature downconvert circuit receives the signal exported from decimal abstraction module, the output of quadrature downconvert circuit is respectively with narrow-band filtering module with eliminate modulation intelligence circuit and be connected, the output eliminating modulation intelligence circuit is connected with fft circuit, the output of fft circuit is connected with spectral line peak search circuit, the output of spectral line peak search circuit is connected with calculating frequency deviation circuit, the output calculating frequency deviation circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with quadrature downconvert circuit.
Input signal is 4 times of symbol sampler rates, enters 4 power computing modules, eliminates the modulation intelligence of QPSK, obtains single audio frequency dot information.Through FFT and spectral line peak value searching, thick frequency deviation information can be obtained.Wherein use 2048 point of counting of FFT, can obtain enough low residual frequency deviation, ensure normally catching of smart frequency deviation synchronization module.Correct once, the thick frequency deviation information that follow-up FFT several times obtains is close, and peak value is enough, then think stable, without the need to correcting again; Otherwise think and system step-out re-start thick frequency offset correction.
Because frequency deviation is comparatively large, DDC, enforcement be the filtering in broadband a little, ensure that signal spectra is not damaged; After thick frequency offset correction completes, then carry out a narrow-band filtering, the out-of-band noise of further filtering remnants.Described narrow-band filtering module is used for the out-of-band noise of further filtering remnants.
Because the signal bandwidth of narrow band signal is less, do not use the balancing techniques such as SCFDE.
Synchronous use Gardner algorithm, to a small amount of residual frequency deviation insensitive (according to 3kHz maximum frequency deviation, about 4.5Mbaud/s baud rate is calculated, and residual frequency deviation is approximately about 0.1% of chip rate), before can being positioned at frequency synchronization module.After input data carry out the interpolation/extraction of little several times, obtain the signal of 4 times of symbol sampler rates; Carry out gardner bit timing estimation error to 4 times of sample value signals, obtain instantaneous error value, after loop filter filter away high frequency noise, driving N CO produces the enable and interpolated parameter of timing interpolation; " Farrow timing interpolation " module uses farrow structure, and interpolation obtains bit decision point accurately, eventually through output Buffer output; Described Farrow structure is a kind of polynomial interpolation implementation structure efficiently.
Described bit synchronization module comprises input buffer module, reg module, Timing error estimate module, loop filter, digital controlled oscillation circuit, timing interpose module, export buffer module and two shift registers, the input of input buffer module and narrow-band filtering model calling, the output of input buffer module and reg model calling, the output of reg module is connected with one of them shift register, the output of this shift register is connected with timing interpose module, one tunnel of timing interpose module exports and is connected with another shift register, the output of this shift register and timing error model calling, the output of Timing error estimate module is connected with loop filter, the output of loop filter is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with timing interpose module, another road of timing interpose module exports and exports data by exporting buffer module,
Described smart frequency deviation synchronization module comprises quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way and bit synchronization model calling, the output of quadrature downconvert circuit is connected with phase error estimation and phase error circuit and decoding/judging module respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with quadrature downconvert circuit.The realization of described digital controlled oscillation circuit uses DDS algorithm, instead of cordic algorithm, because the sequential amount of delay of cordic logic is larger in FPGA, cause loop delay large, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, the performance of loop capturing behavior and tracking behavior can be ensured.
Described decoding/judging module uses Viterbi soft-decision algorithm, and described de-interleaving block simply cushions read-write for realizing.
Described at the uniform velocity buffer module comprises data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel of data buffering module exports and is connected with buffering capacity monitoring modular, another road of data buffering module exports data, the output of buffering capacity monitoring modular and loop filtering model calling, the output of loop filtering module is connected with numerical control oscillation module, one tunnel of numerical control oscillation module exports and data buffering model calling, another road clock signal of numerical control oscillation module.
Described Receiver Module comprises duplexer, transmitting terminal processing module, receiving terminal processing module and driver module, described duplexer for receive and send data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, and the output of driver module is connected with transmitting terminal processing module and receiving terminal processing module respectively;
Described driver module comprises crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way of merit sub-module export respectively with two drive amplification model calling, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes;
Described transmitting terminal processing module comprises frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel of frequency mixing module is input as intermediate-freuqncy signal, the input of another road and one of them the drive amplification model calling in driver module of frequency mixing module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driver module all with numerical control attenuation model calling, the output of numerical control attenuation module with drive amplification module and be connected, the output of driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer,
Described receiving terminal processing module comprises low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of amplification module is all connected with frequency mixing module with the output of another drive amplification module of driver module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, and amplification module outputs signal.
For a receiving terminal method for the air-ground narrow-band communication system of unmanned plane, it is characterized in that: it comprises the following steps:
S1: Receiver Module accepts the signal of communication from outside and the gain control signal from FPGA, sends to intermediate frequency filtering module after conversion;
S2: intermediate frequency filtering module carries out intermediate frequency filtering to the signal inputted from Receiver Module, and sends to ADC;
S3:ADC receives the signal exported from intermediate frequency filtering module, after conversion, send to FPGA;
S4:FPGA exports condition data by internal interface after processing signal, and FPGA is also to Receiver Module outputing gain control signal.
Described step S4 comprises following sub-step:
Down conversion module in S41:FPGA carries out down-converted to the input from ADC, and exports decimal abstraction module to;
S42: decimal abstraction module carries out little several times extraction to the baseband signal received, output signal sample value is to thick frequency offset correction module;
S43: the thick input signal of frequency offset correction module to many times of symbol sampler rates obtains thick frequency deviation information process, and output information is to narrow-band filtering module;
S44: the out-of-band noise of narrow-band filtering module filtering remnants, exports bit synchronization module to;
S45: bit synchronization module carries out bit synchronization process to input signal, outputs signal to smart frequency deviation synchronization module;
S46: smart frequency deviation synchronization module uses digital phase-locked loop to carry out carrier synchronization, completes basic synchronous demodulation, outputs signal to decoding/judging module;
S47: decoding/judging module Received signal strength carries out folding coding, ensures overall demodulation signal to noise ratio, and exports de-interleaving block to; Described folding coding uses Viterbi soft-decision algorithm.
S48: de-interleaving block carries out buffering read-write, exports signal at the uniform velocity buffer module afterwards;
S49: at the uniform velocity demodulating data is at the uniform velocity exported by internal interface by buffer module.
Described step S41 comprises following sub-step:
S411: quadrature downconvert circuit receives from the input of ADC and the input of digital controlled oscillation circuit, export I, Q two paths of signals to low-pass filter circuit, described digital controlled oscillation circuit adopts cordic algorithm;
S412: low-pass filtering module exports decimal abstraction module to after carrying out low-pass filtering to input signal.
Described step S43 comprises following sub-step:
S431: quadrature downconvert circuit receives the many times of symbol sampler rate signals from the input of decimal abstraction module, and export elimination modulation intelligence module to;
S432: eliminate modulation intelligence module and eliminate modulation intelligence, obtain single audio frequency dot information;
S433:FFT module carries out fast fourier transform to single audio frequency dot information, and exports spectral line peak value searching module to;
S434: spectral line peak value searching module carries out peak value searching, obtains thick frequency deviation information, and export calculating frequency deviation module to;
S435: calculate frequency deviation module and calculate thick frequency deviation information, judges whether that needs proceed to correct:
(1) if the thick frequency deviation message that obtains of follow-up FFT is several times close, peak value is enough, then, after result being exported successively to numerical control oscillation module and quadrature downconvert module, directly export narrow-band filtering module to;
(2), in other situation, think and system step-out return step S432 after result being exported successively to numerical control oscillation module, quadrature downconvert module and eliminating modulation intelligence module.
Described step S45 comprises following sub-step:
S451: gardner bit timing estimation error will be carried out from narrow-band filtering module input data, and obtain instantaneous error value;
S452: loop filter filter away high frequency noise;
S453: drive digital controlled oscillation circuit to produce the enable and interpolated parameter of timing interpolation;
S454: carry out timing interpolation to data, obtains bit decision point accurately;
S455: by output buffer Output rusults to frequency deviation synchronization module.
Described step S46 comprises following sub-step:
S461: quadrature downconvert circuit carries out quadrature downconvert to from bit synchronization module input signal, outputs signal to phase error estimation and phase error circuit;
S462: phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit;
S463: loop filter circuit carries out filtering, exports digital controlled oscillation circuit to;
S464: digital controlled oscillation circuit outputs signal to quadrature downconvert circuit, described digital controlled oscillation circuit adopts DDS algorithm;
S465: quadrature downconvert circuit output signal is to decoding/judging module.
Described step S49 comprises following sub-step:
S491: data buffering module receives the data and clock that input from de-interleaving block, outputs signal to buffering capacity detection module;
S492: the buffering capacity of buffering capacity detection module to data buffer module is monitored, and outputs signal to loop filtering module simultaneously;
S493: after loop filtering module carries out filtering, outputs signal to numerical control oscillation module;
S494: numerical control oscillation module has two-way to export, a road output clock, a road output signal control data buffer module;
S495: data buffering module exports data.
The invention has the beneficial effects as follows: the signal that (1) ADC inputs obtains baseband signal through down-conversion, digital controlled oscillation circuit in down-conversion uses cordic algorithm to realize, only consume a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible; (2) baseband signal carries out little several times extraction, obtains the signal sample of 4 times of chip rates, then carries out matched filtering, and the benefit done like this is the calculating being beneficial to matched filtering coefficient; (3) because signal bandwidth after despreading only has about 180kHz, and most high-doppler frequency deviation reaches 3kHz, at certain interference situations., frequency deviation may be caught outside band by transnormal phase-locked loop, so carrier synchronization partial resolution is become " thick frequency offset correction " and " smart frequency deviation is synchronous " two links here; (4) because frequency deviation is comparatively large, DDC, enforcement be the filtering in broadband a little, ensure that signal spectra is not damaged; (5) after thick frequency offset correction completes, then a narrow-band filtering is carried out, the out-of-band noise of further filtering remnants; (6) signal bandwidth of narrow band signal is less, does not re-use the balancing techniques such as SCFDE, cost-saving; (7) bit information after judgement is through channel decoding, and obtain the result after error correction, in order to support the precise time label of remote measurement, demodulating data will at the uniform velocity export; (8) due to above some, the present invention be just applicable to a kind of can the receiving terminal of air-ground narrow-band communication system of unmanned plane that passes of remote measurement, remote control, number and method thereof, receiving terminal comprises unmanned plane terminal.
Accompanying drawing explanation
Fig. 1 is block diagram of the present invention;
Fig. 2 is FPGA function module structure chart;
Fig. 3 is down conversion module structure chart;
Fig. 4 is thick frequency offset correction function structure chart;
Fig. 5 is bit synchronization function structure chart;
Fig. 6 is Farrow structured flowchart;
Fig. 7 is smart frequency deviation synchronization structure figure;
Fig. 8 is at the uniform velocity buffer module structure chart;
Fig. 9 is radio frequency receiving block structural diagram;
Figure 10 is the inventive method flow chart.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail: as shown in Figure 1, a kind of receiving terminal for the air-ground narrow-band communication system of unmanned plane, it comprises Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the signal of communication from outside and the control signal from FPGA, the output of Receiver Module and intermediate frequency filtering model calling, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control of FPGA exports and is connected with ADC, the gain of FPGA controls to export and is connected with Receiver Module, FPGA is also by internal interface demodulated output data,
As shown in Figure 2, described FPGA comprises down conversion module, decimal abstraction module, thick frequency offset correction module, narrow-band filtering module, bit synchronization module, essence frequency deviation synchronization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module, the input of down conversion module is connected with ADC, the output of down conversion module is connected with decimal abstraction module, the output of decimal abstraction module and thick frequency offset correction model calling, the output of thick frequency offset correction module and narrow-band filtering model calling, the output of narrow-band filtering module and bit synchronization model calling, the output of bit synchronization module is connected with smart frequency deviation synchronization module, the output of essence frequency deviation synchronization module is connected with decoding/judging module, the output of decoding/judging module is connected with de-interleaving block, the output of de-interleaving block is connected with at the uniform velocity buffer module, at the uniform velocity the output of buffer module exports demodulation gain by internal interface.
As shown in Figure 3, described down conversion module comprises quadrature downconvert circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of quadrature downconvert circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, quadrature downconvert circuit exports I, Q two paths of signals to low-pass filter circuit, and low-pass filter circuit exports I, Q two paths of signals to decimal abstraction module.Described digital controlled oscillation circuit uses cordic algorithm, and only consume a small amount of register and adder resource, do not consume RAM, resource loss is substantially negligible.
Described decimal abstraction module carries out little several times extraction to the baseband signal that down conversion module obtains, and output signal sample value is to thick frequency offset correction module.
Because after despreading, signal bandwidth only has about 180kHz, and most high-doppler frequency deviation reaches 3kHz, at certain interference situations., frequency deviation may be caught outside band by transnormal phase-locked loop, so carrier synchronization partial resolution is become " thick frequency offset correction " and " smart frequency deviation is synchronous " two links here.
As shown in Figure 4, described thick frequency offset correction module comprises quadrature downconvert circuit, eliminate modulation intelligence circuit, fft circuit, spectral line peak search circuit, calculate frequency deviation circuit and digital controlled oscillation circuit, quadrature downconvert circuit receives the signal exported from decimal abstraction module, the output of quadrature downconvert circuit is respectively with narrow-band filtering module with eliminate modulation intelligence circuit and be connected, the output eliminating modulation intelligence circuit is connected with fft circuit, the output of fft circuit is connected with spectral line peak search circuit, the output of spectral line peak search circuit is connected with calculating frequency deviation circuit, the output calculating frequency deviation circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with quadrature downconvert circuit.
Input signal is 4 times of symbol sampler rates, enters 4 power computing modules, eliminates the modulation intelligence of QPSK, obtains single audio frequency dot information.Through FFT and spectral line peak value searching, thick frequency deviation information can be obtained.Wherein use 2048 point of counting of FFT, can obtain enough low residual frequency deviation, ensure normally catching of smart frequency deviation synchronization module.Correct once, the thick frequency deviation information that follow-up FFT several times obtains is close, and peak value is enough, then think stable, without the need to correcting again; Otherwise think and system step-out re-start thick frequency offset correction.
Because frequency deviation is comparatively large, DDC, enforcement be the filtering in broadband a little, ensure that signal spectra is not damaged; After thick frequency offset correction completes, then carry out a narrow-band filtering, the out-of-band noise of further filtering remnants.Described narrow-band filtering module is used for the out-of-band noise of further filtering remnants.
Because the signal bandwidth of narrow band signal is less, do not use the balancing techniques such as SCFDE.
Synchronous use Gardner algorithm, to a small amount of residual frequency deviation insensitive (according to 3kHz maximum frequency deviation, about 4.5Mbaud/s baud rate is calculated, and residual frequency deviation is approximately about 0.1% of chip rate), before can being positioned at frequency synchronization module.After input data carry out the interpolation/extraction of little several times, obtain the signal of 4 times of symbol sampler rates; Carry out gardner bit timing estimation error to 4 times of sample value signals, obtain instantaneous error value, after loop filter filter away high frequency noise, driving N CO produces the enable and interpolated parameter of timing interpolation; " Farrow timing interpolation " module uses farrow structure, and interpolation obtains bit decision point accurately, eventually through output Buffer output; As shown in Figure 6, described Farrow structure is a kind of polynomial interpolation implementation structure efficiently.
As shown in Figure 5, described bit synchronization module comprises input buffer module, reg module, Timing error estimate module, loop filter, digital controlled oscillation circuit, timing interpose module, export buffer module and two shift registers, the input of input buffer module and narrow-band filtering model calling, the output of input buffer module and reg model calling, the output of reg module is connected with one of them shift register, the output of this shift register is connected with timing interpose module, one tunnel of timing interpose module exports and is connected with another shift register, the output of this shift register and timing error model calling, the output of Timing error estimate module is connected with loop filter, the output of loop filter is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with timing interpose module, another road of timing interpose module exports and exports data by exporting buffer module,
As shown in Figure 7, described smart frequency deviation synchronization module comprises quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way and bit synchronization model calling, the output of quadrature downconvert circuit is connected with phase error estimation and phase error circuit and decoding/judging module respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with quadrature downconvert circuit.The realization of described digital controlled oscillation circuit uses DDS algorithm, instead of cordic algorithm, because the sequential amount of delay of cordic logic is larger in FPGA, cause loop delay large, affect capturing frequency deviation ability, and DDS only has the time delay of 1 to 3 clk, the performance of loop capturing behavior and tracking behavior can be ensured.
Described decoding/judging module uses Viterbi soft-decision algorithm, and described de-interleaving block simply cushions read-write for realizing.
As shown in Figure 8, described at the uniform velocity buffer module comprises data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel of data buffering module exports and is connected with buffering capacity monitoring modular, another road of data buffering module exports data, the output of buffering capacity monitoring modular and loop filtering model calling, the output of loop filtering module is connected with numerical control oscillation module, one tunnel of numerical control oscillation module exports and data buffering model calling, another road clock signal of numerical control oscillation module.
As shown in Figure 9, described Receiver Module comprises duplexer, transmitting terminal processing module, receiving terminal processing module and driver module, described duplexer for receive and send data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, and the output of driver module is connected with transmitting terminal processing module and receiving terminal processing module respectively;
Described driver module comprises crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way of merit sub-module export respectively with two drive amplification model calling, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes;
Described transmitting terminal processing module comprises frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel of frequency mixing module is input as intermediate-freuqncy signal, the input of another road and one of them the drive amplification model calling in driver module of frequency mixing module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driver module all with numerical control attenuation model calling, the output of numerical control attenuation module with drive amplification module and be connected, the output of driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer,
Described receiving terminal processing module comprises low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of amplification module is all connected with frequency mixing module with the output of another drive amplification module of driver module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, and amplification module outputs signal.
As shown in Figure 10, a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane, is characterized in that: it comprises the following steps:
S1: Receiver Module accepts the signal of communication from outside and the gain control signal from FPGA, sends to intermediate frequency filtering module after conversion;
S2: intermediate frequency filtering module carries out intermediate frequency filtering to the signal inputted from Receiver Module, and sends to ADC;
S3:ADC receives the signal exported from intermediate frequency filtering module, after conversion, send to FPGA;
S4:FPGA exports condition data by internal interface after processing signal, and FPGA is also to Receiver Module outputing gain control signal.
Described step S4 comprises following sub-step:
Down conversion module in S41:FPGA carries out down-converted to the input from ADC, and exports decimal abstraction module to;
S42: decimal abstraction module carries out little several times extraction to the baseband signal received, output signal sample value is to thick frequency offset correction module;
S43: the thick input signal of frequency offset correction module to many times of symbol sampler rates obtains thick frequency deviation information process, and output information is to narrow-band filtering module;
S44: the out-of-band noise of narrow-band filtering module filtering remnants, exports bit synchronization module to;
S45: bit synchronization module carries out bit synchronization process to input signal, outputs signal to smart frequency deviation synchronization module;
S46: smart frequency deviation synchronization module uses digital phase-locked loop to carry out carrier synchronization, completes basic synchronous demodulation, outputs signal to decoding/judging module;
S47: decoding/judging module Received signal strength carries out folding coding, ensures overall demodulation signal to noise ratio, and exports de-interleaving block to; Described folding coding uses Viterbi soft-decision algorithm.
S48: de-interleaving block carries out buffering read-write, exports signal at the uniform velocity buffer module afterwards;
S49: at the uniform velocity demodulating data is at the uniform velocity exported by internal interface by buffer module.
Described step S41 comprises following sub-step:
S411: quadrature downconvert circuit receives from the input of ADC and the input of digital controlled oscillation circuit, export I, Q two paths of signals to low-pass filter circuit, described digital controlled oscillation circuit adopts cordic algorithm;
S412: low-pass filtering module exports decimal abstraction module to after carrying out low-pass filtering to input signal.
Described step S43 comprises following sub-step:
S431: quadrature downconvert circuit receives the many times of symbol sampler rate signals from the input of decimal abstraction module, and export elimination modulation intelligence module to;
S432: eliminate modulation intelligence module and eliminate modulation intelligence, obtain single audio frequency dot information;
S433:FFT module carries out fast fourier transform to single audio frequency dot information, and exports spectral line peak value searching module to;
S434: spectral line peak value searching module carries out peak value searching, obtains thick frequency deviation information, and export calculating frequency deviation module to;
S435: calculate frequency deviation module and calculate thick frequency deviation information, judges whether that needs proceed to correct:
(1) if the thick frequency deviation message that obtains of follow-up FFT is several times close, peak value is enough, then, after result being exported successively to numerical control oscillation module and quadrature downconvert module, directly export narrow-band filtering module to;
(2), in other situation, think and system step-out return step S432 after result being exported successively to numerical control oscillation module, quadrature downconvert module and eliminating modulation intelligence module.
Described step S45 comprises following sub-step:
S451: gardner bit timing estimation error will be carried out from narrow-band filtering module input data, and obtain instantaneous error value;
S452: loop filter filter away high frequency noise;
S453: drive digital controlled oscillation circuit to produce the enable and interpolated parameter of timing interpolation;
S454: carry out timing interpolation to data, obtains bit decision point accurately;
S455: by output buffer Output rusults to frequency deviation synchronization module.
Described step S46 comprises following sub-step:
S461: quadrature downconvert circuit carries out quadrature downconvert to from bit synchronization module input signal, outputs signal to phase error estimation and phase error circuit;
S462: phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit;
S463: loop filter circuit carries out filtering, exports digital controlled oscillation circuit to;
S464: digital controlled oscillation circuit outputs signal to quadrature downconvert circuit, described digital controlled oscillation circuit adopts DDS algorithm;
S465: quadrature downconvert circuit output signal is to decoding/judging module.
Described step S49 comprises following sub-step:
S491: data buffering module receives the data and clock that input from de-interleaving block, outputs signal to buffering capacity detection module;
S492: the buffering capacity of buffering capacity detection module to data buffer module is monitored, and outputs signal to loop filtering module simultaneously;
S493: after loop filtering module carries out filtering, outputs signal to numerical control oscillation module;
S494: numerical control oscillation module has two-way to export, a road output clock, a road output signal control data buffer module;
S495: data buffering module exports data.
Claims (10)
1. the receiving terminal for the air-ground narrow-band communication system of unmanned plane, it is characterized in that: it comprises Receiver Module, intermediate frequency filtering module, ADC and FPGA, Receiver Module receives the signal of communication from outside and the control signal from FPGA, the output of Receiver Module and intermediate frequency filtering model calling, the output of intermediate frequency filtering module is connected with ADC, the output of ADC is connected with FPGA, the clock control of FPGA exports and is connected with ADC, the gain of FPGA controls to export and is connected with Receiver Module, and FPGA is also by internal interface demodulated output data;
Described FPGA comprises down conversion module, decimal abstraction module, thick frequency offset correction module, narrow-band filtering module, bit synchronization module, essence frequency deviation synchronization module, decoding/judging module, de-interleaving block and at the uniform velocity buffer module, the input of down conversion module is connected with ADC, the output of down conversion module is connected with decimal abstraction module, the output of decimal abstraction module and thick frequency offset correction model calling, the output of thick frequency offset correction module and narrow-band filtering model calling, the output of narrow-band filtering module and bit synchronization model calling, the output of bit synchronization module is connected with smart frequency deviation synchronization module, the output of essence frequency deviation synchronization module is connected with decoding/judging module, the output of decoding/judging module is connected with de-interleaving block, the output of de-interleaving block is connected with at the uniform velocity buffer module, at the uniform velocity the output of buffer module exports demodulation gain by internal interface.
2. a kind of receiving terminal for the air-ground narrow-band communication system of unmanned plane according to claim 1, it is characterized in that: described down conversion module comprises quadrature downconvert circuit, low-pass filter circuit and digital controlled oscillation circuit, the input of quadrature downconvert circuit is connected with ADC input signal and digital controlled oscillation circuit respectively, quadrature downconvert circuit exports I, Q two paths of signals to low-pass filter circuit, low-pass filter circuit exports I, Q two paths of signals to decimal abstraction module, and described digital controlled oscillation circuit uses cordic algorithm;
Described thick frequency offset correction module comprises quadrature downconvert circuit, eliminate modulation intelligence circuit, fft circuit, spectral line peak search circuit, calculate frequency deviation circuit and digital controlled oscillation circuit, quadrature downconvert circuit receives the signal exported from decimal abstraction module, the output of quadrature downconvert circuit is respectively with narrow-band filtering module with eliminate modulation intelligence circuit and be connected, the output eliminating modulation intelligence circuit is connected with fft circuit, the output of fft circuit is connected with spectral line peak search circuit, the output of spectral line peak search circuit is connected with calculating frequency deviation circuit, the output calculating frequency deviation circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with quadrature downconvert circuit,
Described bit synchronization module comprises input buffer module, reg module, Timing error estimate module, loop filter, digital controlled oscillation circuit, timing interpose module, export buffer module and two shift registers, the input of input buffer module and narrow-band filtering model calling, the output of input buffer module and reg model calling, the output of reg module is connected with one of them shift register, the output of this shift register is connected with timing interpose module, one tunnel of timing interpose module exports and is connected with another shift register, the output of this shift register and timing error model calling, the output of Timing error estimate module is connected with loop filter, the output of loop filter is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with timing interpose module, another road of timing interpose module exports and exports data by exporting buffer module,
Described smart frequency deviation synchronization module comprises quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit, quadrature downconvert circuit, digital controlled oscillation circuit, phase error estimation and phase error circuit and loop filter circuit composition digital phase-locked loop, exterior I, the input of Q two-way and bit synchronization model calling, the output of quadrature downconvert circuit is connected with phase error estimation and phase error circuit and decoding/judging module respectively, the output of phase error estimation and phase error circuit is connected with loop filter circuit, the output of loop filter circuit is connected with digital controlled oscillation circuit, the output of digital controlled oscillation circuit is connected with quadrature downconvert circuit, the practical DDS algorithm of described digital controlled oscillation circuit,
Described at the uniform velocity buffer module comprises data buffering module, buffering capacity monitoring modular, loop filtering module and numerical control oscillation module, data buffering module receives input data and input clock, one tunnel of data buffering module exports and is connected with buffering capacity monitoring modular, another road of data buffering module exports data, the output of buffering capacity monitoring modular and loop filtering model calling, the output of loop filtering module is connected with numerical control oscillation module, one tunnel of numerical control oscillation module exports and data buffering model calling, another road clock signal of numerical control oscillation module.
3. a kind of receiving terminal for the air-ground narrow-band communication system of unmanned plane according to claim 1, it is characterized in that: described Receiver Module comprises duplexer, transmitting terminal processing module, receiving terminal processing module and driver module, described duplexer for receive and send data, the output of described transmitting terminal processing module is connected with duplexer, the input of receiving terminal processing module is connected with duplexer, and the output of driver module is connected with transmitting terminal processing module and receiving terminal processing module respectively;
Described driver module comprises crystal oscillator, local oscillator, merit sub-module, two drive amplification modules and driver, the two-way input of local oscillator is connected with crystal oscillator and SPI code respectively, the output of local oscillator is connected with merit sub-module, the two-way of merit sub-module export respectively with two drive amplification model calling, the output of two drive amplification modules is connected with transmitting terminal processing module and receiving terminal processing module respectively, the output of driver is connected with transmitting terminal processing module, and described driver exports 5 parallel-by-bit control codes;
Described transmitting terminal processing module comprises frequency mixing module, filtration module, amplification module, numerical control attenuation module, drive amplification module and power amplifier module, one tunnel of frequency mixing module is input as intermediate-freuqncy signal, the input of another road and one of them the drive amplification model calling in driver module of frequency mixing module, the output of frequency mixing module is connected with filtration module, the output of filtration module is connected with amplification module, the output of the output of amplification module and the driver of driver module all with numerical control attenuation model calling, the output of numerical control attenuation module with drive amplification module and be connected, the output of driving amplification module is connected with power amplifier module, the output of power amplifier module is connected with duplexer,
Described receiving terminal processing module comprises low noise amplification module, filtration module, amplification module, frequency mixing module, filtration module and amplification module, the input of low noise amplification module is connected with duplexer, the output of low noise amplification module is connected with filtration module, the output of filtration module is connected with amplification module, the output of amplification module is all connected with frequency mixing module with the output of another drive amplification module of driver module, the output of frequency mixing module is connected with filtration module, filtration module is connected with amplification module, and amplification module outputs signal.
4., for a receiving terminal method for the air-ground narrow-band communication system of unmanned plane, it is characterized in that: it comprises the following steps:
S1: Receiver Module accepts the signal of communication from outside and the gain control signal from FPGA, sends to intermediate frequency filtering module after conversion;
S2: intermediate frequency filtering module carries out intermediate frequency filtering to the signal inputted from Receiver Module, and sends to ADC;
S3:ADC receives the signal exported from intermediate frequency filtering module, after conversion, send to FPGA;
S4:FPGA exports condition data by internal interface after processing signal, and FPGA is also to Receiver Module outputing gain control signal.
5. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 4, is characterized in that: described step S4 comprises following sub-step:
Down conversion module in S41:FPGA carries out down-converted to the input from ADC, and exports decimal abstraction module to;
S42: decimal abstraction module carries out little several times extraction to the baseband signal received, output signal sample value is to thick frequency offset correction module;
S43: the thick input signal of frequency offset correction module to many times of symbol sampler rates obtains thick frequency deviation information process, and output information is to narrow-band filtering module;
S44: the out-of-band noise of narrow-band filtering module filtering remnants, exports bit synchronization module to;
S45: bit synchronization module carries out bit synchronization process to input signal, outputs signal to smart frequency deviation synchronization module;
S46: smart frequency deviation synchronization module uses digital phase-locked loop to carry out carrier synchronization, completes basic synchronous demodulation, outputs signal to decoding/judging module;
S47: decoding/judging module Received signal strength carries out folding coding, ensures overall demodulation signal to noise ratio, and exports de-interleaving block to; Described folding coding uses Viterbi soft-decision algorithm;
S48: de-interleaving block carries out buffering read-write, exports signal at the uniform velocity buffer module afterwards;
S49: at the uniform velocity demodulating data is at the uniform velocity exported by internal interface by buffer module.
6. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 5, is characterized in that: described step S41 comprises following sub-step:
S411: quadrature downconvert circuit receives from the input of ADC and the input of digital controlled oscillation circuit, export I, Q two paths of signals to low-pass filter circuit, described digital controlled oscillation circuit adopts cordic algorithm;
S412: low-pass filtering module exports decimal abstraction module to after carrying out low-pass filtering to input signal.
7. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 5, is characterized in that: described step S43 comprises following sub-step:
S431: quadrature downconvert circuit receives the many times of symbol sampler rate signals from the input of decimal abstraction module, and export elimination modulation intelligence module to;
S432: eliminate modulation intelligence module and eliminate modulation intelligence, obtain single audio frequency dot information;
S433:FFT module carries out fast fourier transform to single audio frequency dot information, and exports spectral line peak value searching module to;
S434: spectral line peak value searching module carries out peak value searching, obtains thick frequency deviation information, and export calculating frequency deviation module to;
S435: calculate frequency deviation module and calculate thick frequency deviation information, judges whether that needs proceed to correct:
(1) if the thick frequency deviation message that obtains of follow-up FFT is several times close, peak value is enough, then, after result being exported successively to numerical control oscillation module and quadrature downconvert module, directly export narrow-band filtering module to;
(2), in other situation, think and system step-out return step S432 after result being exported successively to numerical control oscillation module, quadrature downconvert module and eliminating modulation intelligence module.
8. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 5, is characterized in that: described step S45 comprises following sub-step:
S451: gardner bit timing estimation error will be carried out from narrow-band filtering module input data, and obtain instantaneous error value;
S452: loop filter filter away high frequency noise;
S453: drive digital controlled oscillation circuit to produce the enable and interpolated parameter of timing interpolation;
S454: carry out timing interpolation to data, obtains bit decision point accurately;
S455: by output buffer Output rusults to frequency deviation synchronization module.
9. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 5, is characterized in that: described step S46 comprises following sub-step:
S461: quadrature downconvert circuit carries out quadrature downconvert to from bit synchronization module input signal, outputs signal to phase error estimation and phase error circuit;
S462: phase error estimation and phase error circuit carries out phase estimation, outputs signal to loop filter circuit;
S463: loop filter circuit carries out filtering, exports digital controlled oscillation circuit to;
S464: digital controlled oscillation circuit outputs signal to quadrature downconvert circuit, described digital controlled oscillation circuit adopts DDS algorithm;
S465: quadrature downconvert circuit output signal is to decoding/judging module.
10. a kind of receiving terminal method for the air-ground narrow-band communication system of unmanned plane according to claim 5, is characterized in that: described step S49 comprises following sub-step:
S491: data buffering module receives the data and clock that input from de-interleaving block, outputs signal to buffering capacity detection module;
S492: the buffering capacity of buffering capacity detection module to data buffer module is monitored, and outputs signal to loop filtering module simultaneously;
S493: after loop filtering module carries out filtering, outputs signal to numerical control oscillation module;
S494: numerical control oscillation module has two-way to export, a road output clock, a road output signal control data buffer module;
S495: data buffering module exports data.
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