CN115911083A

CN115911083A - Semiconductor structure and insulated gate bipolar transistor

Info

Publication number: CN115911083A
Application number: CN202110968562.5A
Authority: CN
Inventors: 刘利书
Original assignee: Meiken Semiconductor Technology Co ltd
Current assignee: Meiken Semiconductor Technology Co ltd
Priority date: 2021-08-23
Filing date: 2021-08-23
Publication date: 2023-04-04

Abstract

The embodiment of the application discloses a semiconductor structure and an insulated gate bipolar transistor, the semiconductor structure comprises a blocking region, an emitter, a first ohmic contact region, a first voltage clamping structure and a first isolation dielectric region, wherein the emitter is located above the blocking region, the first ohmic contact region and the emitter are arranged above the blocking region at intervals, the first ohmic contact region is in contact with the blocking region, the first voltage clamping structure is arranged between the emitter and the first ohmic contact region, the first voltage clamping structure comprises a first doping region and a second doping region which are in contact with each other, the first doping region is in contact with the emitter, the second doping region is in contact with the first ohmic contact region, the charge types of majority carriers of the first doping region and the second doping region are different, the charge types of majority carriers of the second doping region and the blocking region are the same, and the first isolation dielectric region is arranged between the first voltage clamping structure and the blocking region.

Description

Semiconductor structure and insulated gate bipolar transistor

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and an insulated gate bipolar transistor.

Background

Insulated Gate Bipolar Transistors (IGBTs) are a very important power device, are key components for realizing variable-frequency intelligent control, have the advantages of simple driving circuit, high input impedance, high current density, low on-resistance and the like, and are widely applied to the commercial fields of white home appliances, high-speed rails, photovoltaic inverters and the like. With the continuous development of system miniaturization and high power, the application system puts more stringent requirements on the reliability of the insulated gate bipolar transistor.

The short-circuit tolerance (also called short-circuit tolerance time) refers to the duration time that the insulated gate bipolar transistor can withstand the short-circuit condition, is one of important parameters for measuring the reliability of the insulated gate bipolar transistor, indicates the capability of the insulated gate bipolar transistor to simultaneously withstand large current and voltage under the short-circuit condition, is influenced by the saturation current density of the device, and is improved along with the reduction of the saturation current density. Along with the high-voltage and large-current increase of devices, higher requirements are put on the short-circuit tolerance of the insulated gate bipolar transistor so as to prevent the thermal collapse effect under the condition of accidental short circuit.

Disclosure of Invention

In view of the foregoing, embodiments of the present application provide a semiconductor structure and an insulated gate bipolar transistor.

According to an aspect of the present application, there is provided a semiconductor structure comprising:

a blocking region;

an emitter located above the blocking region;

the first ohmic contact region and the emitter are arranged above the barrier region at intervals, and the first ohmic contact region is in contact with the barrier region;

a first voltage clamp structure disposed between the emitter and the first ohmic contact region, the first voltage clamp structure comprising: the first doping area is contacted with the emitter, and the second doping area is contacted with the first ohmic contact area; the charge types of majority carriers of the first doped region and the second doped region are different, and the charge types of majority carriers of the second doped region and the blocking region are the same;

a first isolation dielectric region disposed between the first voltage clamp structure and the blocking region.

In some embodiments, the first voltage clamp structure includes a plurality of first doped regions and a plurality of second doped regions, the plurality of first doped regions and the plurality of second doped regions are alternately disposed between the emitter and the first ohmic contact region, and two adjacent first doped regions and two adjacent second doped regions are in contact.

In some embodiments, the semiconductor structure further comprises:

the first grid structure is arranged between the blocking region and the first isolation medium region and comprises a first grid and a first grid medium layer; the first grid dielectric layer is arranged around the side wall and the bottom of the first grid and used for electrically isolating the first grid from the blocking area;

the second grid structure is arranged above the blocking region and positioned on one side of the emitter, which is far away from the first ohmic contact region, and comprises a second grid and a second grid dielectric layer; and the second gate dielectric layer is arranged around the side wall and the bottom wall of the second gate and used for electrically isolating the second gate from the blocking region.

In some embodiments, an end of the first gate structure near the blocking region extends into the blocking region;

one end, close to the blocking region, of the second gate structure extends into the blocking region;

the semiconductor structure further comprises a base region, wherein the base region is arranged above the blocking region and located between the first gate structure and the second gate structure, and the base region is respectively in contact with the emitter, the blocking region, the first gate structure and the second gate structure.

In some embodiments, the semiconductor structure further comprises:

the second voltage clamping structure is arranged on one side, far away from the first voltage clamping structure, of the emitter and is positioned above the second gate structure, the second voltage clamping structure comprises a third doped region and a fourth doped region which are in contact with each other, the third doped region is in contact with the emitter, the third doped region and the first doped region have the same charge type of majority carriers, and the fourth doped region and the second doped region have the same charge type of majority carriers;

the second ohmic contact region is arranged on one side, away from the emitter, of the second voltage clamping structure and is positioned above the blocking region, and the second ohmic contact region is in contact with the fourth doped region and the blocking region;

a second isolation dielectric region disposed between the second voltage clamp structure and the second gate structure.

In some embodiments, the second voltage clamp structure includes a plurality of the third doped regions and a plurality of the fourth doped regions, the plurality of the third doped regions and the plurality of the fourth doped regions are alternately disposed between the emitter and the second ohmic contact region, and two adjacent third doped regions and the fourth doped regions are in contact.

In some embodiments, the third doped region and the first doped region have the same doping concentration of majority carriers, and the fourth doped region and the second doped region have the same doping concentration of majority carriers.

In some embodiments, the semiconductor structure further comprises:

the third ohmic contact region is arranged above the second grid electrode and is in contact with the second grid electrode;

the fourth ohmic contact region is arranged on one side, far away from the emitter, of the third ohmic contact region and is in contact with the blocking region;

the drain structure is arranged between the third ohmic contact region and the fourth ohmic contact region and is positioned above the second grid structure, the drain structure comprises a fifth doping region, a sixth doping region and an adjusting doping region which are sequentially contacted, the fifth doping region is contacted with the third ohmic contact region, the adjusting doping region is contacted with the fourth ohmic contact region, the charge types of majority carriers of the fifth doping region and the adjusting doping region are the same, and the charge types of majority carriers of the fifth doping region and the sixth doping region are different;

the third isolation medium region is arranged between the drain structure and the second grid structure;

and the fourth isolation medium region is arranged between the third ohmic contact region and the emitter.

In some embodiments, the drain structure includes a plurality of the fifth doping regions and a plurality of the sixth doping regions, the plurality of the fifth doping regions and the plurality of the sixth doping regions are alternately disposed between the third ohmic contact region and the adjustment doping region, and two adjacent fifth doping regions and two adjacent sixth doping regions are in contact.

According to a second aspect of the present application, there is provided an insulated gate bipolar transistor comprising:

a blocking region;

an emitter located above the blocking region;

The embodiment of the application provides a semiconductor structure and an insulated gate bipolar transistor, wherein a first doped region and a second doped region are arranged on one side of an emitter in the semiconductor structure, and the charge types of majority carriers in the first doped region and the second doped region are different, so that a diode is formed between the emitter and a blocking region. When the device is conducted, the diode formed by the first doping area and the second doping area is in a reverse connection state, so that the potential of the blocking area is clamped at the breakdown voltage of the diode, the blocking area is maintained at a low potential, the saturation current density is reduced, and the short circuit tolerance of the device is improved.

Drawings

FIG. 1 is a schematic diagram of an IGBT in related art;

fig. 2 is an equivalent circuit diagram of the insulated gate bipolar transistor shown in fig. 1;

fig. 3 is a schematic structural diagram of an igbt according to an embodiment of the present application;

fig. 4 is an equivalent circuit diagram of the insulated gate bipolar transistor shown in fig. 3;

fig. 5 is a schematic structural diagram of another igbt according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of another igbt according to the embodiment of the present application;

fig. 7 is a schematic structural diagram of another igbt according to the embodiment of the present application;

fig. 8 is an equivalent circuit diagram of the insulated gate bipolar transistor shown in fig. 7;

fig. 9 is a schematic structural diagram of another igbt according to the embodiment of the present application;

fig. 10 is a graph comparing output characteristics of the igbt shown in fig. 1 and fig. 3, respectively;

fig. 11 is a graph comparing output characteristics of the igbt shown in fig. 1, 3, and 7;

FIG. 12 is a graph comparing ESD voltages of the IGBT of FIGS. 1, 3 and 7, respectively;

description of reference numerals:

101: blocking region, 102: emitter, 103: first gate structure, 1031: first gate, 1032: first gate dielectric layer, 104: second gate structure, 1041: second gate, 1042: second gate dielectric layer, 105: base region, 106: emitter region, 107: drift region, 108: buffer, 109: collector region, 110: collector, 111: a base heavily doped region;

200: first voltage clamp structure, 201: first doped region, 202: second doped region, 203: first ohmic contact region, 204: first insulating dielectric region, 210: second voltage clamp structure, 211: third doped region, 212: fourth doped region, 213: second insulating dielectric region, 214: a second ohmic contact region;

300: drainage structure, 301: fifth doped region, 302: sixth doped region, 303: adjusting doping region, 304: third ohmic contact region, 305: third insulating medium region, 306: fourth ohmic contact region, 307: and a fourth insulating medium region.

Detailed Description

The technical solution of the present application is further described in detail with reference to the drawings and specific embodiments of the specification.

In the description of the present application, it is to be understood that the terms "length," "width," "depth," "upper," "lower," "outer," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Fig. 1 is a schematic structural diagram of an insulated gate bipolar transistor in the related art, and referring to fig. 1, the insulated gate bipolar transistor includes a Collector (Collector), a P Collector region (P Collector), an N buffer region (N buffer), an N drift region (N drift), an N barrier region (N layer), and a P base region (P base) that are sequentially arranged from bottom to top; the N-type semiconductor device also comprises two N emitter regions (N +), wherein the two N emitter regions are arranged on the P base region at intervals, and a P heavily doped region (P +) is also arranged between the two N emitter regions; an Emitter (Emitter) is located above the N Emitter region and the P heavily doped region; two grid electrodes are respectively arranged on two sides of the N emitter region, and each grid electrode is contacted with one N emitter region, the P base region and the N blocking region; an oxide dielectric layer is arranged between the grid and the emitter to electrically isolate the grid and the emitter.

FIG. 2 is a view of FIG. 1An equivalent circuit diagram of the insulated gate bipolar transistor of (1). As can be seen from fig. 1 and fig. 2, the igbt can be regarded as a darlington transistor including an MOSFET and a PNP, and has the same turn-on characteristic as the MOSFET and the same output characteristic as the PNP bipolar transistor. When the gate-emitter voltage V _GE Exceeds the threshold voltage V of the IGBT _th And a collector-emitter voltage V _CE When the conduction voltage drop of the PN junction is exceeded, the insulated gate bipolar transistor is conducted, the collector injects holes to the N drift region, and the concentration of the holes is reduced in sequence along the direction from the collector to the emitter. However, such uneven hole distribution can result in saturated on-state voltage drop V of the device _cesat And is increased. For this purpose, an N-blocking region may be provided between the P base region and the N drift region, the N-blocking region having a higher doping concentration than the N drift region. As shown in fig. 1, according to the band alignment theory, a hole barrier exists at the interface between the N-blocking region and the N-drift region, which causes holes to gather at the interface, and the hole concentration near the emitter increases, thereby reducing the voltage drop when the device is turned on.

However, the provision of the N-blocking region also brings disadvantages, such as accumulation of holes at the interface between the N-blocking region and the N-drift region, raising the potential of the N-blocking region, and equivalent drain-source voltage V of the MOSFET _DS If the saturation current density is increased, the saturation current density of the device is increased, and the short-circuit tolerance is lowered.

In view of the above problems, the embodiments of the present application provide an igbt that clamps the potential of the blocking region to adjust the equivalent MOSFET drain-source voltage V _DS And the voltage is kept at a low voltage level, so that the saturation current density of the device is reduced, and the short-circuit tolerance is improved.

Fig. 3 is a schematic structural diagram of an igbt according to an embodiment of the application. Referring to fig. 3, the insulated gate bipolar transistor includes a semiconductor structure including:

the semiconductor device comprises a barrier region 101, an emitter 102, a first ohmic contact region 203, a first voltage clamp structure 200 and a first isolation dielectric region 204, wherein the emitter 102 is located above the barrier region 101, the first ohmic contact region 203 and the emitter 102 are arranged above the barrier region 101 at intervals, the first ohmic contact region 203203 is in contact with the barrier region 101, the first voltage clamp structure 200 is arranged between a conductor of the emitter 102 and the first ohmic contact region 203, the first voltage clamp structure 200 comprises a first doped region 201 and a second doped region 202 which are in contact with each other, the first doped region 201 is in contact with the emitter 102, and the second doped region 202 is in contact with the first ohmic contact region 203; the charge types of the majority carriers of the first doped region 201 and the second doped region 202 are different, and the charge types of the majority carriers of the second doped region 202 and the blocking region 101 are the same; a first isolation dielectric region 204 is disposed between the first voltage clamp structure 200 and the barrier region 101.

In the semiconductor structure provided by the embodiment of the present application, the first doped region 201 and the second doped region 202 are disposed on one side of the emitter 102, and the charge types of the majority carriers of the first doped region 201 and the second doped region 202 are different, so that a diode is formed between the emitter 102 and the blocking region 101. When the device is turned on, the diode formed by the first doped region 201 and the second doped region 202 is in a reverse connection state, so that the potential of the blocking region 101 is clamped to the breakdown voltage of the diode, thereby maintaining a lower potential, reducing the saturation current density and improving the short circuit tolerance of the device.

It should be noted that, in the embodiment of the present application, the charge type of the majority carriers of the first doping region 201, the second doping region 202 and the blocking region 101 in the semiconductor structure is not limited.

In the present embodiment, the majority carriers of the blocking region 101 are electrons (i.e., N-blocking region), the majority carriers of the second doped region 202 are electrons (i.e., N-type second doped region), and the majority carriers of the first doped region 201 are holes (i.e., P-type first doped region). It is easily understood that, in the insulated gate bipolar transistor, when the barrier region 101 is an N barrier region, the other regions are a P collector region 109, an N buffer region 108, an N drift region 107, a P base region 105, and an N emitter region 106, respectively (the positional relationship of these regions is explained later).

After the insulated gate bipolar transistor is turned on, holes are injected into the N blocking region 101 from the P collector region 109, the holes are accumulated near the N blocking region 101, and the turn-on voltage drop is reduced; after the holes are accumulated to a certain degree, the potential of the N-blocking region 101 exceeds the reverse breakdown voltage of the diode formed by the N-type second doping region 202 and the P-type first doping region 201, and then the redundant holes leak through the first ohmic contact region 203, the N-type second doping region 202 and the P-type first doping region 201, so that the lower potential of the N-blocking region 101 is maintained, the saturation current density of the device is reduced, and the short circuit tolerance of the device is improved.

Fig. 4 is an equivalent circuit diagram of the insulated gate bipolar transistor shown in fig. 3. It can also be seen from fig. 4 that a diode is connected between the source and drain of the equivalent MOSFET, so that the drain-source voltage V of the equivalent MOSFET is _DS Is clamped at the reverse breakdown voltage of the diode and thereby reduces the saturation current density of the device.

In some embodiments, the majority carriers of the blocking region are holes (i.e., P-blocking region), the majority carriers of the second doped region are holes (i.e., P-type second doped region), and the majority carriers of the first doped region are electrons (i.e., N-type first doped region). It is easily understood that, in the insulated gate bipolar transistor, when the barrier region is a P barrier region, correspondingly, the other regions are an N collector region, a P buffer region, a P drift region, an N base region, and a P emitter region, respectively.

After the insulated gate bipolar transistor is conducted, electrons are injected into the P blocking region from the N collector region and are accumulated near the P blocking region, and after the electrons are accumulated to a certain degree, the potential of the emitter exceeds the reverse breakdown voltage of a diode formed by the N type first doping region/the P type second doping region, redundant electrons leak through the first ohmic contact region/the P type second doping region/the N type first doping region, so that the lower potential of the P blocking region is maintained, the saturation current density is reduced, and the short circuit tolerance of the device is improved.

Here, it should be noted that the semiconductor structure provided in the embodiments of the present application is not only applicable to an insulated gate bipolar transistor, but also applicable to other power devices having a power MOSFET structure, such as a MOSFET, a VD-MOSFET, and the like.

It should be noted that the material of the first ohmic contact region 203 includes, but is not limited to, tungsten, cobalt, copper, aluminum, heavily doped polysilicon, etc. In addition, as for the way of contacting the first ohmic contact region 203 with the barrier region 101, the lower end surface of the first ohmic contact region 203 may contact with the barrier region 101, or the lower end portion of the first ohmic contact region 203 may extend into the barrier region 101, so that the lower end surface and the side wall surface of the first ohmic contact region 203 contact with the barrier region 101.

The material of the first doped region includes, but is not limited to, P-type polysilicon, N-type polysilicon, etc., and the material of the second doped region includes, but is not limited to, N-type polysilicon, P-type polysilicon, etc.

The number of the first doped region 201 and the second doped region 202 in the first voltage clamp structure 200 is not limited in the embodiments of the present application. In this embodiment, the first voltage clamping structure 200 includes a first doped region 201 and a second doped region 202, i.e., includes a diode. In some embodiments, referring to fig. 5, the first voltage clamping structure 200 includes a plurality of diodes connected in series. Specifically, the first voltage clamping structure 200 includes a plurality of first doped regions 201 and a plurality of second doped regions 202, the plurality of first doped regions 201 and the plurality of second doped regions 202 are alternately disposed between the emitter 102 and the first ohmic contact region 203, and two adjacent first doped regions 201 are in contact with the second doped regions 202.

In practical use, 1 to 3 diodes, i.e., one first doped region 201 and one second doped region 202, or 3 first doped regions 201 and 3 second doped regions 202, may be arranged in series in the first voltage clamp structure 200 according to the withstand voltage level of the device. Also, the higher the withstand voltage level of the device, the greater the number of diodes connected in series, and the higher the clamping voltage of the blocking region 101.

Referring further to fig. 3, the semiconductor structure provided in this embodiment further includes a first gate structure 103 and a second gate structure 104, where the first gate structure 103 is disposed between the blocking region 101 and the first isolation dielectric region 204, and the first gate structure 103 includes a first gate 1031 and a first gate dielectric layer 1032; a first gate dielectric layer 1032 surrounds the sidewall and the bottom of the first gate 1031, and is used for electrically isolating the first gate 1031 from the blocking region 101; the second gate structure 104 is disposed above the blocking region 101 and located on a side of the emitter 102 away from the first ohmic contact region 203203, the second gate structure 104 includes a second gate 1041 and a second gate dielectric layer 1042; the second gate dielectric layer 1042 surrounds the sidewall and the bottom wall of the second gate 1041, and is used for electrically isolating the second gate 1041 from the blocking region 101.

In addition, the semiconductor structure provided by this embodiment may further include a drift region 107 disposed below the blocking region 101, a buffer region 108 disposed below the drift region 107, a collector region 109 disposed below the buffer region 108, and a collector 110 disposed below the collector region 109.

In order to further improve the current draining capability of the voltage clamp structure in a semiconductor structure provided with two gate structures, a second voltage clamp structure 210 is provided above the second gate structure 104.

Specifically, referring to fig. 3, the semiconductor structure further includes a second voltage clamp structure 210, a second ohmic contact region 214, and a second isolation dielectric region 213.

A second voltage clamping structure 210 disposed on a side of the emitter 102 away from the first voltage clamping structure 200 and above the second gate structure 104, the second voltage clamping structure 210 including a third doped region 211 and a fourth doped region 212 in contact;

the third doped region 211 is in contact with the emitter 102, and the third doped region 211 and the first doped region 201 have the same charge type of majority carriers;

the charge type of the majority carriers of the fourth doped region 212 and the second doped region 202 are the same;

the second ohmic contact region 214 is disposed on a side of the second voltage clamping structure 210 away from the emitter 102 and above the blocking region 101, and the second ohmic contact region 214 is in contact with the fourth doped region 212 and the blocking region 101;

a second isolation dielectric region 213 is disposed between the second voltage clamping structure 210 and the second gate structure 104.

In this embodiment, the majority carriers of the blocking region 101 are electrons (i.e., N-type blocking region), correspondingly, the majority carriers of the first doped region 201 are holes (i.e., P-type first doped region), the majority carriers of the second doped region 202 are electrons (i.e., N-type second doped region), the majority carriers of the third doped region 211 are holes (i.e., P-type third doped region), and the majority carriers of the fourth doped region 212 are electrons (i.e., N-type fourth doped region), so that two diodes connected in parallel are formed between the emitter 102 and the blocking region 101, and the leakage current path is increased.

When the insulated gate bipolar transistor shown in this embodiment is turned on, the P collector region 109 injects holes into the N blocking region 101; after the holes are accumulated to a certain degree, and the potential of the N-blocking region 101 exceeds the reverse breakdown voltage of the two diodes, the redundant holes leak through the first ohmic contact region 203202/the N-type second doping region 202/the P-type first doping region 201, and leak through the second ohmic contact region 214/the N-type fourth doping region 212/the P-type third doping region 211, so that the lower potential of the N-blocking region 101 is maintained, the saturation current density of the device is reduced, the leakage path is increased, and the short circuit tolerance of the device is further improved.

It should be noted that, in the embodiment of the present application, the number of the third doped regions 211 and the fourth doped regions 212 in the second voltage clamping structure 210 is not limited. In the present embodiment, the second voltage clamping structure 210 includes a third doped region 211 and a fourth doped region 212, i.e., includes a diode. In some embodiments, referring to fig. 5, the second voltage clamping structure 210 includes a plurality of diodes connected in series. Specifically, the second voltage clamp structure 210 includes a plurality of third doped regions 211 and a plurality of fourth doped regions 212, the plurality of third doped regions 211 and the plurality of fourth doped regions 212 are alternately disposed between the emitter 102 and the second ohmic contact region 214, and two adjacent third doped regions 211 and fourth doped regions 212 are in contact.

In practical use, 1 to 3 diodes can be arranged in the second voltage clamping structure 210 in series according to the withstand voltage level of the device; also, the higher the withstand voltage level of the device, the greater the number of diodes connected in series, and the higher the clamping voltage of the blocking region 101.

It should be further noted that, preferably, the number of the third doped regions 211 is the same as that of the first doped regions 201, and the number of the fourth doped regions 212 is the same as that of the second doped regions 202, so that the clamping voltage of the first voltage clamping structure 200 is equal to that of the second voltage clamping structure 210, and the first voltage clamping structure 200 and the second voltage clamping structure 210 participate in carrier leakage at the same time, thereby increasing a leakage path and improving short-circuit tolerance of the device.

Preferably, the doping concentration of majority carriers of the third doping region 211 and the first doping region 201 is the same, and the doping concentration of majority carriers of the fourth doping region 212 and the second doping region 202 is the same, so that the reverse breakdown voltage of the diode in the first voltage clamping structure 200 is the same as the reverse breakdown voltage of the diode in the second voltage clamping structure 210, and when the first voltage clamping structure 200 and the second voltage clamping structure 210 include the same number of diodes, the first voltage clamping structure 200 and the second voltage clamping structure 210 can participate in carrier leakage at the same time, so that the leakage path is increased, and the short circuit tolerance of the device is improved.

It is further noted that the material of the second ohmic contact region 214 includes, but is not limited to, tungsten, cobalt, copper, aluminum, heavily doped polysilicon, etc. In addition, as for the way of contacting the second ohmic contact region 314 with the barrier region 101, the lower end surface of the second ohmic contact region 214 may contact with the barrier region 101, or the lower end portion of the second ohmic contact region 214 may extend into the barrier region 101, so that the lower end surface and the side wall surface of the second ohmic contact region 214 contact with the barrier region 101.

The third doped region is made of, but not limited to, P-type polysilicon, N-type polysilicon, etc., and the fourth doped region is made of, but not limited to, N-type polysilicon, P-type polysilicon, etc.

In addition, in the semiconductor structure provided by the embodiment of the present application, the gate structure may include a trench gate, as shown in fig. 3; in other embodiments, the gate structure may also include a planar gate, as shown in fig. 6.

Referring to fig. 3, the first gate structure 103 and the second gate structure 104 are both trench gates. Specifically, one end of the first gate structure 103 close to the blocking region 101 extends into the blocking region 101; one end of the second gate structure 104 close to the blocking region 101 extends into the blocking region 101; the semiconductor structure further comprises a base region 105, the base region 105 is disposed above the blocking region 101 and between the first gate structure 103 and the second gate structure 104, and the base region 105 is in contact with the emitter 102, the blocking region 101, and the first gate structure 103, respectively.

In addition, the semiconductor structure of the present embodiment further includes two emitter regions 106, the two emitter regions 106 are spaced apart from each other in the base region 105, one of the emitter regions 106 is in contact with the base region 105, the emitter 102, and the first gate structure 103, and the other emitter region 106 is in contact with the base region 105, the emitter 102, and the second gate structure 104.

In some embodiments, the base region (105) includes a base region body and a base heavily doped region (111), the base heavily doped region (111) is located above the base region body and between the two emitter regions 106, and the base heavily doped region (111) is in contact with the two emitter regions 106, the emitter 102, and the base region 105. The heavily doped base region 111 is used to improve the latch-up resistance of the igbt.

In fig. 3, the blocking region 101 surrounds the entire trench gate, and the base region 105 and the first ohmic contact region 203 are respectively disposed at two sides of the first gate structure 103, and the base region 105 and the second ohmic contact region 214 are respectively disposed at two sides of the second gate structure 104. When the insulated gate bipolar transistor is turned off, the withstand voltage of the device is mainly born by the base region 105/the blocking region 101/the drift region 107, and the trench gate can prevent the depletion region (space charge region) from extending to the first ohmic contact region 203 and the second ohmic contact region 214, so that the withstand voltage level of the device is prevented from being obviously reduced after the depletion region is conducted with the first ohmic contact region 203 and the second ohmic contact region 214.

Referring to fig. 6, the first gate structure 103 and the second gate structure 104 are both planar gates. Specifically, the semiconductor structure further includes a base region 105 and two emitter regions 106, wherein the base region 105 is disposed within the barrier region 101, and the base region 105 is in contact with the emitter 102 and the barrier region 101; two emitter regions 106 are arranged in the base region 105 at intervals, and each emitter region 106 is respectively in contact with the base region 105 and the emitter 102; the first gate structure 103 and the second gate structure 104 are disposed on two sides of the emitter 102 and are both located above the barrier region 101, the first gate structure 103 is in contact with the barrier region 101, the base region 105 and one of the emitter regions 106, and the second gate structure 104 is in contact with the barrier region 101, the base region 105 and the other emitter region 106. The first and second

ohmic contact regions

203, 214 may be located as far away from the base region 105 as possible in order to avoid that the depletion layer (space charge region) extends towards the ohmic contact regions when the igbt is turned off.

Anti-electrostatic discharge (ESD) is also one of the important parameters for measuring the reliability of the igbt. The insulated gate bipolar transistor is required to have high anti-static discharge level, especially for single-tube package, PIM package and the like with the grid exposed outside. As can be seen from the above description of the present application, the blocking region 101 can provide a drain path for the charges flowing out of the emitter 102. In yet another embodiment provided by the present application, the drain path is utilized to increase the ESD rating of the device.

Fig. 7 is a schematic structural diagram of another igbt according to an embodiment of the present application. Referring to fig. 7, the semiconductor structure further includes: a third ohmic contact region 304, a fourth ohmic contact region 306, a bleed structure 300, a third isolating dielectric region 305, and a fourth isolating dielectric region 307, wherein,

the third ohmic contact region 304 is disposed above the second gate 1042 and contacts the second gate 1042;

the fourth ohmic contact region 306 is disposed on a side of the third ohmic contact region 304 away from the emitter 102, and the fourth ohmic contact region 306 is in contact with the barrier region 101;

the drain structure 300 is disposed between the third ohmic contact region 304 and the fourth ohmic contact region 306, and is located above the second gate 1042 structure, the drain structure 300 includes a fifth doping region 301, a sixth doping region 302, and a tuning doping region 303, which are sequentially disposed in contact with each other;

the fifth doping region 301 is in contact with the third ohmic contact region 304, the adjusting doping region 303 is in contact with the fourth ohmic contact region 306, the charge types of the majority carriers of the fifth doping region 301 and the adjusting doping region 303 are the same, and the charge types of the majority carriers of the sixth doping region 302 and the fifth doping region 301 are different;

the third isolation dielectric region 305 is disposed between the drain structure 300 and the second gate 1042 structure;

a fourth insulating dielectric region 307 is provided between the third ohmic contact region 304 and the emitter 102.

In this embodiment, a fifth doping region 301, a sixth doping region 302 and a modifying doping region 303 are disposed on the second gate 1042 structure, wherein the charge types of the fifth doping region 301 and the modifying doping region 303 are the same, and the charge types of the fifth doping region 301 and the sixth doping region 302 are different, so as to form a diode group connected in series and in reverse; the diode group and the first voltage clamp structure 200 together form a charge draining path consisting of the second gate 1042/draining structure 300/blocking region 101/first voltage clamp structure 200/emitter 102.

It should be noted that, the application does not limit the charge type of the majority carriers in the blocking region 101, the first doping region 201, the second doping region 202, the fifth doping region 301, the sixth doping region 302 and the adjusting doping region 303 in the semiconductor structure.

In this embodiment, when the majority carrier of the blocking region 101 is an electron (i.e., an N-blocking region), correspondingly, the majority carrier of the first doped region 201 is a hole (i.e., a P-type first doped region), the majority carrier of the second doped region 202 is an electron (i.e., an N-type second doped region), the majority carrier of the fifth doped region 301 is an electron (i.e., an N-type fifth doped region), the majority carrier of the sixth doped region 302 is a hole (i.e., a P-type sixth doped region), and the majority carrier type of the adjusting doped region 303 is an electron (i.e., an N-type adjusting doped region). In this manner, an NPN-type series-reverse diode group is formed in the drain structure 300.

When the igbt is normally turned on, the series-connected diode group in the drain structure 300 makes the second gate 1042 and the blocking region 101 not be turned on; when electrostatic charge is accumulated in the second gate 1042 to make the potential of the second gate 1042 exceed the reverse breakdown voltage of the diode formed by the fifth doped region 301 and the sixth doped region 302, the electrostatic charge leaks through the third ohmic contact region 304/the fifth doped region 301/the sixth doped region 302/the fourth ohmic contact region 306/the blocking region 101/the first ohmic contact region 203/the second doped region 202/the first doped region 201/the emitter 102, so as to prevent the electrostatic charge accumulation from breaking through the isolation dielectric layer and damaging the device, thereby improving the ESD rating of the device.

Fig. 8 is an equivalent circuit diagram of the insulated gate bipolar transistor shown in fig. 7. As can also be seen from fig. 8, a charge leakage path composed of the leakage structure 300/the blocking region 101/the first voltage clamp structure 200 is formed between the gate and the emitter 102 to improve the ESD rating of the device.

It should be noted that, in some embodiments, when the majority carriers of the blocking region 101 are electrons (i.e., an N-blocking region), the majority carriers of the first doped region 201 are holes (i.e., a P-type first doped region), and the majority carriers of the second doped region 202 are electrons (i.e., an N-type second doped region), the majority carriers doped in the fifth doped region 301 in the drain structure may also be holes (i.e., a P-type fifth doped region), the majority carriers of the sixth doped region 302 are electrons (i.e., an N-type sixth doped region), and the majority carriers of the adjusting doped region 303 are holes (i.e., a P-type adjusting doped region). In this manner, a PNP-type series-reverse diode group is formed in the drain structure 300.

In addition, the number of the fifth doping region 301 and the sixth doping region 302 in the drain structure 300 is not limited in the embodiments of the present application. In some embodiments, the bleeder structure 300 comprises a plurality of fifth doped regions 301 and a plurality of sixth doped regions 302, and the number of fifth doped regions 301 and sixth doped regions 302. Specifically, referring to fig. 9, the bleeder structure 300 includes a plurality of fifth doping regions 301 and a plurality of sixth doping regions 302, the plurality of fifth doping regions 301 and the plurality of sixth doping regions 302 are alternately disposed between the third ohmic contact region 304 and the adjustment doping region 303, and two adjacent fifth doping regions 301 and sixth doping regions 302 are in contact.

In practical use, 3 to 7 groups of the fifth doped region 301 and the sixth doped region 302 may be arranged according to the ESD protection level requirement, the package of the igbt, and the like, that is, 3 fifth doped regions 301 and 3 sixth doped regions 302, or 5 fifth doped regions 301 and 5 sixth doped regions 302, or 7 fifth doped regions 301 and 7 sixth doped regions 302 are arranged.

As an example, when the majority carriers of the fifth doped region 301 are electrons (N-type doping), the majority carriers of the sixth doped region 302 are holes (P-type doping), and the majority carriers of the adjusting doped region 303 are electrons (N-type doping), a series-connected reverse diode set of NPNPN type is formed in the drain structure 300 shown in fig. 9.

It should be noted that the materials of the third ohmic contact region 304 and the fourth ohmic contact region 306 include, but are not limited to, tungsten, cobalt, copper, aluminum, heavily doped polysilicon, etc. In addition, as for the contact manner between the third ohmic contact region 304 and the blocking region 101, the lower end surfaces of the third ohmic contact region 304 and the fourth ohmic contact region 306 may be respectively contacted with the blocking region 101, or the lower end portions of the third ohmic contact region 304 and the fourth ohmic contact region 306 may respectively extend into the blocking region 101, so that the lower end surfaces and the side wall surfaces of the third ohmic contact region 304 and the fourth ohmic contact region 306 are contacted with the blocking region 101.

The fifth doped region is made of, but not limited to, P-type polysilicon, N-type polysilicon, etc., the sixth doped region is made of, but not limited to, N-type polysilicon, P-type polysilicon, etc., and the adjustment doped region is made of, but not limited to, N-type polysilicon, P-type polysilicon, etc.

In addition, the present application also performs comparative analysis on the saturation current density and the ESD voltage of the insulated gate bipolar transistor shown in fig. 3, the insulated gate bipolar transistor shown in fig. 7, and the insulated gate bipolar transistor shown in fig. 1 by using a software tool. Part of the parameters of three insulated gate bipolar transistors are designed as follows: the implantation dose of the P collector region is 9E12 cm ^-2 (ii) a The implantation dose of the N buffer region is 2E13cm ^-2 (ii) a The doping concentration of the N drift region is 1E14cm ^-3 (ii) a The doping concentration of the P base region is 5E16cm ^-3 (ii) a The doping concentration of the N emitter 102 region is 1E20cm ^-3 (ii) a The thickness of the gate dielectric layer is 100nm. The analytical results were as follows:

fig. 10 is an output characteristic curve of the insulated gate bipolar transistor shown in fig. 3 and 1, respectively. The output characteristic curve is the gate-emitter 102 voltage V _GE Set to 15V by scanning collector 110-emitter 102 voltage V _CE And (4) obtaining the product. In fig. 10, the conventional IGBT is the insulated gate bipolar transistor shown in fig. 1The transistor, the novel IGBT, is an insulated gate bipolar transistor shown in fig. 3. As shown in fig. 10, the saturation current density of the novel IGBT is significantly lower than that of the conventional IGBT. When taking the bus voltage V _CE =300V, the saturation current density J of the conventional IGBT is 509A/cm ² And the novel IGBT is 245A/cm ² The current value is reduced by 51.8%, the current value of the device during short circuit is greatly reduced, and the reliability of the device is improved.

More quantitatively analyzing the saturation current I of the device _C Can be expressed as:

wherein alpha is _PNP ，μ，C _ox And W/L is the gain factor of PNP tube, the mobility of carrier, the gate oxide capacitance per unit area and the width-length ratio of device. V _GE ，V _th ，V _CE And V _A Respectively, the gate-emitter 102 Voltage, the threshold Voltage of the device, the collector 110-emitter 102 Voltage, and Early Voltage (Early Voltage). For an ideal device, early voltage V _A Approaching infinity, the last term of the above equation approaches 0, and thus the saturation current I _C And V _CE Independently, a horizontal line is arranged on the curve. In fact, the early voltage V _A Is of finite value, and therefore, the saturation current I _C Following V _CE Monotonically increases until the device breaks down.

For a conventional IGBT, when V _CE When increased, e.g. to the usual bus voltage V _CE =300V, the saturation current increases significantly, and the heat generation increases sharply. In the novel IGBT structure, when V is _CE When increased, the drain-source voltage V applied to the equivalent MOSFET _DS Is clamped, corresponding to V in equation (1) _CE The clamping voltage is always maintained, and can be 0.7V at the lowest, so that the lower current density is ensured. The above analysis is consistent with the curves in fig. 10.

Fig. 11 is an output characteristic curve of the edge gate bipolar transistor shown in fig. 3, 7 and 1. The output characteristic curve is a gatePole-emitter 102 voltage V _GE Set to 15V, by sweeping the collector 110-emitter 102 voltage V _CE And (4) obtaining the product. Fig. 12 is a voltage comparison diagram of the edge gate bipolar transistor shown in fig. 3, 7 and 1. In fig. 10 and 11, the conventional IGBT refers to the insulated gate bipolar transistor shown in fig. 1, the new IGBT refers to the insulated gate bipolar transistor shown in fig. 3, and the ESD-IGBT refers to the insulated gate bipolar transistor shown in fig. 7.

As shown in fig. 10 and 11, in the ESD-IGBT, since the clamp design of the N-blocking region 101 is adopted, the saturation current density of the ESD-IGBT remains low. In addition, the design of the ESD leakage flow channel enables the Human Body discharge mode (HBM) to be increased from 1.5kV of the traditional structure to 3.7kV of the novel structure, and the performance is obviously improved. Note that the saturation current density of the ESD-IGBT structure is increased compared to the new IGBT shown in fig. 3, which is related to the reduction of the number of clamp paths of the N-blocking region 101.

To sum up, the insulated gate bipolar transistor provided by the embodiment of the present application reduces the saturation current density of the device based on the clamp voltage setting of the blocking region, thereby reducing the current value when the device is short-circuited and improving the short-circuit tolerance of the device. In addition, the embodiment of the application also provides an electrostatic charge leakage path formed by the grid electrode, the leakage structure, the blocking area, the first voltage clamping structure and the emitter, so that the ESD grade of the device is improved, and the reliability of the device is comprehensively improved.

The scope of the present disclosure is not limited to the specific embodiments described herein, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, comprising:

a blocking region;

an emitter located above the blocking region;

a first voltage clamp structure disposed between the emitter and the first ohmic contact region, the first voltage clamp structure comprising: the first doping area and the second doping area are in contact with each other, the first doping area is in contact with the emitter, and the second doping area is in contact with the first ohmic contact area; the charge types of majority carriers of the first doped region and the second doped region are different, and the charge types of majority carriers of the second doped region and the blocking region are the same;

2. The semiconductor structure of claim 1, wherein the first voltage clamp structure comprises a plurality of first doped regions and a plurality of second doped regions, wherein the plurality of first doped regions and the plurality of second doped regions are alternately disposed between the emitter and the first ohmic contact region, and two adjacent first doped regions and two adjacent second doped regions are in contact.

3. The semiconductor structure of claim 1, further comprising:

the first grid structure is arranged between the blocking area and the first isolation medium area and comprises a first grid and a first grid medium layer; the first grid dielectric layer is arranged around the side wall and the bottom of the first grid and used for electrically isolating the first grid from the blocking area;

the second grid structure is arranged above the blocking region and positioned on one side of the emitter, which is far away from the first ohmic contact region, and the second grid structure comprises a second grid and a second grid dielectric layer; the second grid dielectric layer is arranged around the side wall and the bottom wall of the second grid and used for electrically isolating the second grid from the blocking area.

4. The semiconductor structure of claim 3,

one end of the first grid structure close to the blocking region extends into the blocking region;

one end of the second gate structure close to the blocking region extends into the blocking region;

the semiconductor structure further comprises a base region, wherein the base region is arranged above the blocking region and is positioned between the first gate structure and the second gate structure, and the base region is respectively contacted with the emitter, the blocking region, the first gate structure and the second gate structure.

5. The semiconductor structure of claim 3, further comprising:

the second ohmic contact region is arranged on one side, far away from the emitter, of the second voltage clamping structure and is positioned above the blocking region, and the second ohmic contact region is in contact with the fourth doping region and the blocking region;

6. The semiconductor structure of claim 5, wherein the second voltage clamp structure comprises a plurality of the third doped regions and a plurality of the fourth doped regions, wherein the plurality of third doped regions and the plurality of fourth doped regions are alternately disposed between the emitter and the second ohmic contact regions, and wherein two adjacent third doped regions and fourth doped regions are in contact.

7. The semiconductor structure of claim 5, wherein the third doped region and the first doped region have the same doping concentration of majority carriers, and wherein the fourth doped region and the second doped region have the same doping concentration of majority carriers.

8. The semiconductor structure of claim 3, further comprising

9. The semiconductor structure of claim 8, wherein the drain structure comprises a plurality of the fifth doped regions and a plurality of the sixth doped regions, the plurality of the fifth doped regions and the plurality of the sixth doped regions are alternately disposed between the third ohmic contact region and the adjustment doped region, and two adjacent fifth doped regions and the sixth doped regions are in contact.

10. An insulated gate bipolar transistor comprising a semiconductor structure according to any of claims 1 to 9.