CN115910985B - Power semiconductor module - Google Patents
Power semiconductor module Download PDFInfo
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- CN115910985B CN115910985B CN202211405522.0A CN202211405522A CN115910985B CN 115910985 B CN115910985 B CN 115910985B CN 202211405522 A CN202211405522 A CN 202211405522A CN 115910985 B CN115910985 B CN 115910985B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 239000000741 silica gel Substances 0.000 claims description 5
- 229910002027 silica gel Inorganic materials 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 description 8
- NMWSKOLWZZWHPL-UHFFFAOYSA-N 3-chlorobiphenyl Chemical compound ClC1=CC=CC(C=2C=CC=CC=2)=C1 NMWSKOLWZZWHPL-UHFFFAOYSA-N 0.000 description 4
- 101001082832 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) Pyruvate carboxylase 2 Proteins 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000005493 welding type Methods 0.000 description 1
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Abstract
The invention discloses a power semiconductor module, comprising: the grid PCB comprises a drive connection unit, and one end of the grid lead-out end is connected with the grid of the semiconductor chip; the grid electrode PCB is provided with a plurality of grid electrode contacts electrically connected with the other ends of the grid electrode leading-out ends, the grid electrode contacts are connected with the driving connection unit through a plurality of first wiring layers, and current paths flowing through the first wiring layers are consistent. By implementing the invention, the current paths from the driving end to each grid contact are consistent, and the balance of parasitic parameters of the grid is realized, so that the current sharing capability between modules connected in parallel in the module is effectively improved, and the integral safe working area of the module is improved. And the current sharing capability is improved, so that the safety and reliability of the parallel sub-modules can be improved while the parallel sub-modules are increased.
Description
Technical Field
The invention relates to the technical field of high-power semiconductors, in particular to a power semiconductor module.
Background
In recent years, with the acceleration of the commercialization process of silicon carbide power semiconductor devices, a good market prospect promotes the continuous development of technology. In order to meet the increasingly-growing high-power application demands, a multi-chip parallel packaging structure is generally adopted to improve the rated current of the module. However, larger transient unbalanced current can occur among the parallel chips, and suppression of the common source stray inductance of each chip gate driving loop is more difficult, which brings about a small challenge for safety and stability of the power semiconductor module.
Disclosure of Invention
In view of the above, the embodiment of the invention provides a power semiconductor module to solve the technical problem that the parallel chips in the prior art can cause larger transient unbalanced current.
The technical scheme provided by the embodiment of the invention is as follows:
a first aspect of an embodiment of the present invention provides a power semiconductor module, including: the grid PCB comprises a drive connection unit, and one end of the grid lead-out end is connected with a grid of the semiconductor chip; the grid electrode PCB is provided with a plurality of grid electrode contacts electrically connected with the other end of the grid electrode leading-out end, the grid electrode contacts are connected with the driving connection unit through a plurality of first wiring layers, and current paths flowing through the first wiring layers are consistent.
Optionally, the sub-module further comprises: an auxiliary emitter lead-out terminal, one end of which is connected with the emitter of the semiconductor chip; and a plurality of auxiliary emitter contacts electrically connected with the other end of the auxiliary emitter lead-out end are arranged on the grid PCB, the auxiliary emitter contacts are connected with the driving connection unit through a plurality of second wiring layers, and current paths flowing through the second wiring layers are consistent.
Optionally, the gate PCB includes: the first layer and the second layer, the gate contact, the auxiliary emitter contact and the first wiring layer are arranged on the first layer, the second wiring layer is arranged on the second layer, the auxiliary emitter contact is not contacted with the first wiring layer, and the auxiliary emitter contact is connected with the second wiring layer through a through hole.
Optionally, the sub-module further comprises: and one end of the emitter lead-out end is connected with the emitter of the semiconductor chip, and the other end of the emitter lead-out end is connected with an external power negative electrode.
Optionally, the gate PCB further includes: and one end of each grid resistor is connected with the grid contact, the other end of each grid resistor is connected with the driving connection unit, and the resistance value of the grid resistors is adjustable.
Optionally, the gate terminal, the auxiliary emitter terminal and the emitter terminal are formed by elastic components, the heights of the gate terminal, the auxiliary emitter terminal and the emitter terminal are greater than the height of the semiconductor chip, the height of the emitter terminal is greater than the height of the auxiliary emitter terminal, and the difference between the height of the emitter terminal and the height of the auxiliary emitter terminal is the thickness of the gate PCB.
Optionally, the power semiconductor module further comprises: the positions of the holes of the tube shell with the holes are corresponding to those of the sub-modules, and the tube shell and the sub-modules are matched to realize pressure balance control.
Optionally, the sub-module further comprises: and the bottom plate is arranged on the back surface of the semiconductor chip and is connected with the semiconductor chip.
Optionally, the sub-module further comprises: and the height of the insulating shell is matched with the heights of the grid electrode leading-out end, the auxiliary emitter leading-out end and the emitter leading-out end.
Optionally, the sub-module further comprises: and the silica gel is filled in the sub-module.
The technical scheme of the invention has the following advantages:
according to the power semiconductor module provided by the embodiment of the invention, the plurality of sub-modules are connected in parallel, so that the current grade of the power semiconductor module is improved; the grid PCB is arranged outside the sub-module, the first wiring layer is arranged on the grid PCB and is connected with the grid of the sub-module through the grid contacts and the grid leading-out terminals on the plate, and the current paths flowing through the first wiring layers are consistent and symmetrically distributed, so that the current paths from the driving end to each grid contact are consistent, the balance of parasitic parameters of the grid is realized, the current equalizing capacity of the parallel modules inside the module is effectively improved, and the integral safe working area of the module is improved. And the current sharing capability is improved, so that the safety and reliability of the parallel sub-modules can be improved while the parallel sub-modules are increased, and the current level of the device is greatly improved. In addition, through setting up grid PCB board in the module, can be under the condition that size, shape etc. inject, can realize the parallelly connected flow equalizing of a plurality of submodules through adjusting structure, the wiring mode of grid PCB board, effectively reduce research and development cost.
According to the power semiconductor module provided by the embodiment of the invention, the emitter of the semiconductor chip with the auxiliary emitter lead-out end is connected, the auxiliary emitter lead-out end and the grid lead-out end are connected with different circuits in different layers of the grid PCB, namely, the drive connection units are connected through the first wiring layer and the second wiring layer respectively, so that decoupling of a drive loop and the power loop is realized, parasitic inductance of a common source is reduced, meanwhile, current imbalance among parallel chips is reduced, the switching speed of the module is improved, the switching loss of the module is reduced, and therefore, the safe working area of the module is effectively improved, and the switching performance of the module is improved.
The power semiconductor module provided by the embodiment of the invention has the advantages that the current paths flowing through the second wiring layers are consistent; the lengths of the current paths from the driving connection unit to the auxiliary emitter contacts are consistent, the consistency of parasitic parameters of the emitters in a driving loop is realized, and the balance degree of currents among parallel chips is effectively improved.
According to the power semiconductor module provided by the embodiment of the invention, the plurality of grid resistors with adjustable resistance values are arranged, and the current sharing capability among the parallel chips can be further improved by changing the resistance values of the grid resistors. By providing the bottom plate on the back side of the semiconductor chip, the thermal resistance of the heat dissipation channel on the back side of the chip can be reduced. The insulation materials such as silica gel are filled in the sub-modules, so that the insulation capacity and reliability of the whole module can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a top view of a power semiconductor module according to an embodiment of the invention;
fig. 2 is a cross-sectional view of a power semiconductor module according to an embodiment of the invention;
FIG. 3 is a top view of a first layer of a grid PCB in an embodiment of the invention;
fig. 4 is a top view of a first layer of a gate PCB in an embodiment of the invention.
Detailed Description
As described in the background art, when the chips are connected in parallel, larger transient unbalanced current can occur between the parallel chips, and the current distribution is unbalanced, so that a certain chip can pass through too large current, and the sub-module formed by the chips is locally invalid; and may even cause power module failure or explosion. Thus, current imbalance can cause problems with reduced device safe operating area.
In view of the above, the embodiment of the invention provides a power semiconductor module, which enables parasitic parameters of a grid electrode to have consistency through consistency of current paths among a plurality of parallel chips, thereby effectively improving the balance degree of currents among the parallel chips and improving the integral safety working area of the module.
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
An embodiment of the present invention provides a power semiconductor module, as shown in fig. 1, fig. 2, and fig. 3, including: the grid PCB 2 and a plurality of sub-modules 1 connected in parallel, each sub-module 1 comprises a semiconductor chip and a grid leading-out terminal 3, the grid PCB 2 comprises a driving connection unit 6, and one end of the grid leading-out terminal 3 is connected with the grid of the semiconductor chip; the gate PCB 2 is provided with a plurality of gate contacts 8 electrically connected to the other end of the gate lead-out terminal 3, the plurality of gate contacts 8 are connected to the driving connection unit 6 through a plurality of first wiring layers, and current paths flowing through the plurality of first wiring layers are identical.
The driving connection unit is connected with an external driving unit, and the external driving unit adopts a grid driver and is used for applying voltage to the grid of the semiconductor chip and providing driving current. The material of the current flow path of the first wiring layer is a metal material such as copper, and the rest is made of an insulating material. The current paths flowing through the plurality of first wiring layers are uniform, specifically, the lengths of the current paths are uniform, and the widths are adjustable. The semiconductor chip can be a compression joint type chip or a welding type chip, and the embodiment of the invention is not limited to the specific type of the chip.
According to the power semiconductor module provided by the embodiment of the invention, the plurality of sub-modules are connected in parallel, so that the current grade of the power semiconductor module is improved; the grid PCB is arranged outside the sub-module, the first wiring layer is arranged on the grid PCB and is connected with the grid of the sub-module through the grid contacts and the grid leading-out terminals on the plate, and the current paths flowing through the first wiring layers are consistent and symmetrically distributed, so that the current paths from the driving end to each grid contact are consistent, the balance of parasitic parameters of the grid is realized, the current equalizing capacity of the parallel modules inside the module is effectively improved, and the integral safe working area of the module is improved. And current sharing capability
The parallel sub-modules can be increased, and meanwhile, the safety and the reliability of the parallel sub-modules can be improved, so that the parallel sub-modules are greatly helpful for increasing the current level of the device. In addition, through setting up grid PCB board in the module, can be under the condition that size, shape etc. inject, can realize the parallelly connected flow equalizing of a plurality of submodules through adjusting structure, the wiring mode of grid PCB board, effectively reduce research and development cost.
In one embodiment, as shown in fig. 2 and 3, the sub-module further includes: an auxiliary emitter lead-out terminal 4, wherein one end of the auxiliary emitter lead-out terminal 4 is connected with an emitter of the semiconductor chip; the gate PCB 2 is provided with a plurality of auxiliary emitter contacts 9 electrically connected to the other end of the auxiliary emitter lead-out terminal 4, the plurality of auxiliary emitter contacts 9 are connected to the driving connection unit 6 through a plurality of second wiring layers, and current paths flowing through the plurality of second wiring layers are identical. As shown in fig. 2, the sub-module further includes: an emitter lead-out terminal 5, wherein one end of the emitter lead-out terminal 5 is connected with an emitter of the semiconductor chip, and the other end of the emitter lead-out terminal is connected with an external power negative electrode. Specifically, the material of the current flow path of the second wiring layer is a metal material such as copper or the like, and the remaining portion is made of an insulating material. As shown in fig. 3, a plurality of holes 10 may be provided on the gate PCB such that the emitter terminal can be connected to the negative electrode of the external power supply through the holes without contacting the gate PCB.
In one embodiment, the currents flowing through the plurality of first wiring layers may be symmetrically distributed in addition to the uniform paths, and the currents flowing through the plurality of second wiring layers may be symmetrically distributed in addition to the uniform paths. Thereby, the uniformity of the parasitic emitter parameters in the drive circuit can be further improved.
The gate PCB includes: the first layer and the second layer, specifically, fig. 3 is a first layer top view of the gate PCB board, and fig. 4 is a second layer top view of the gate PCB board, wherein the gate PCB board is divided into a driving connection unit 6 and a main body portion 7. The gate contact 9, the auxiliary emitter contact 9 and the first wiring layer are arranged on the first layer, the second wiring layer is arranged on the second layer, the auxiliary emitter contact 9 is not in contact with the first wiring layer, and the auxiliary emitter contact 9 is connected with the second wiring layer through a through hole 11 as shown in fig. 3.
In addition, the gate terminal, the auxiliary emitter terminal and the emitter terminal are formed by elastic components, the heights of the gate terminal, the auxiliary emitter terminal and the emitter terminal are larger than the height of the semiconductor chip, the height of the emitter terminal is larger than the height of the auxiliary emitter terminal, and the difference between the height of the emitter terminal and the height of the auxiliary emitter terminal is the thickness of the gate PCB.
Specifically, the gate terminal, the auxiliary emitter terminal, and the emitter terminal are connected with the gate or the emitter, respectively, through bonding wires, an elastic assembly is used as the terminal, and the height of the elastic assembly is greater than that of the semiconductor chip, so that the spring assembly can be used for bearing pressure without bearing pressure of the semiconductor chip, thereby realizing a pressure welding package and a short circuit failure mode.
According to the power semiconductor module provided by the embodiment of the invention, the emitter of the semiconductor chip with the auxiliary emitter lead-out end is connected, the auxiliary emitter lead-out end and the grid lead-out end are connected with different circuits in different layers of the grid PCB, namely, the drive connection units are connected through the first wiring layer and the second wiring layer respectively, so that decoupling of a drive loop and the power loop is realized, parasitic inductance of a common source is reduced, meanwhile, current imbalance among parallel chips is reduced, the switching speed of the module is improved, the switching loss of the module is reduced, and therefore, the safe working area of the module is effectively improved, and the switching performance of the module is improved.
The power semiconductor module provided by the embodiment of the invention has the advantages that the current paths flowing through the second wiring layers are consistent; the lengths of the current paths from the driving connection unit to the auxiliary emitter contacts are consistent, the consistency of parasitic parameters of the emitters in a driving loop is realized, and the balance degree of currents among parallel chips is effectively improved.
In an embodiment, the gate PCB further includes: and one end of each grid resistor is connected with the grid contact, the other end of each grid resistor is connected with the driving connection unit, and the resistance value of the grid resistors is adjustable. Specifically, the setting of the grid resistor can be adjusted through a plurality of resistance values, and the current sharing capability among the parallel chips can be further improved through changing the resistance value of the grid resistor.
In an embodiment, the power semiconductor module further includes: the positions of the holes of the tube shell with the holes are corresponding to those of the sub-modules, and the tube shell and the sub-modules are matched to realize pressure balance control. The sub-module further comprises: and the bottom plate is arranged on the back surface of the semiconductor chip and is connected with the semiconductor chip. The sub-module further comprises: and the height of the insulating shell is matched with the heights of the grid electrode leading-out end, the auxiliary emitter leading-out end and the emitter leading-out end. The sub-module further comprises: and the silica gel is filled in the sub-module. Wherein the height of the insulating housing is specifically set to match the insulation requirements of the module.
According to the power semiconductor module provided by the embodiment of the invention, the bottom plate is arranged on the back of the semiconductor chip, so that the heat resistance of the heat dissipation channel on the back of the chip can be reduced. The insulation materials such as silica gel are filled in the sub-modules, so that the insulation capacity and reliability of the whole module can be improved.
Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art may make various changes, substitutions and alterations to these embodiments without departing from the spirit of the invention and the scope of protection as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while remaining within the scope of the present invention.
Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. From the present disclosure, it will be readily understood by those of ordinary skill in the art that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (9)
1. A power semiconductor module, comprising: the grid PCB comprises a drive connection unit, and one end of the grid lead-out end is connected with a grid of the semiconductor chip;
the grid electrode PCB is provided with a plurality of grid electrode contacts electrically connected with the other end of the grid electrode leading-out end, the grid electrode contacts are connected with the driving connection unit through a plurality of first wiring layers, and current paths flowing through the first wiring layers are consistent;
the sub-module further comprises: an auxiliary emitter lead-out terminal, one end of which is connected with the emitter of the semiconductor chip;
and a plurality of auxiliary emitter contacts electrically connected with the other end of the auxiliary emitter lead-out end are arranged on the grid PCB, the auxiliary emitter contacts are connected with the driving connection unit through a plurality of second wiring layers, and current paths flowing through the second wiring layers are consistent.
2. The power semiconductor module of claim 1, wherein the gate PCB board comprises: the first layer and the second layer, the gate contact, the auxiliary emitter contact and the first wiring layer are arranged on the first layer, the second wiring layer is arranged on the second layer, the auxiliary emitter contact is not contacted with the first wiring layer, and the auxiliary emitter contact is connected with the second wiring layer through a through hole.
3. The power semiconductor module of claim 1, wherein the sub-module further comprises: and one end of the emitter lead-out end is connected with the emitter of the semiconductor chip, and the other end of the emitter lead-out end is connected with an external power negative electrode.
4. The power semiconductor module of claim 1, wherein the gate PCB further comprises: and one end of each grid resistor is connected with the grid contact, the other end of each grid resistor is connected with the driving connection unit, and the resistance value of the grid resistors is adjustable.
5. A power semiconductor module according to claim 3, wherein the gate terminal, the auxiliary emitter terminal and the emitter terminal are formed using elastic members, the heights of the gate terminal, the auxiliary emitter terminal and the emitter terminal are greater than the height of the semiconductor chip, the height of the emitter terminal is greater than the height of the auxiliary emitter terminal, and the difference between the height of the emitter terminal and the height of the auxiliary emitter terminal is the thickness of the gate PCB.
6. The power semiconductor module of claim 1, further comprising: the positions of the holes of the tube shell with the holes are corresponding to those of the sub-modules, and the tube shell and the sub-modules are matched to realize pressure balance control.
7. The power semiconductor module of claim 1, wherein the sub-module further comprises: and the bottom plate is arranged on the back surface of the semiconductor chip and is connected with the semiconductor chip.
8. A power semiconductor module according to claim 3, wherein the sub-module further comprises: and the height of the insulating shell is matched with the heights of the grid electrode leading-out end, the auxiliary emitter leading-out end and the emitter leading-out end.
9. The power semiconductor module of claim 1, wherein the sub-module further comprises: and the silica gel is filled in the sub-module.
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| CN202211405522.0A CN115910985B (en) | 2022-11-10 | 2022-11-10 | Power semiconductor module |
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| CN202211405522.0A CN115910985B (en) | 2022-11-10 | 2022-11-10 | Power semiconductor module |
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| CN115910985A CN115910985A (en) | 2023-04-04 |
| CN115910985B true CN115910985B (en) | 2023-10-27 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08191239A (en) * | 1995-01-11 | 1996-07-23 | Hitachi Ltd | Power semiconductor module |
| JP2009105454A (en) * | 2009-02-10 | 2009-05-14 | Mitsubishi Electric Corp | Power semiconductor module |
| CN107240571A (en) * | 2017-05-10 | 2017-10-10 | 株洲中车时代电气股份有限公司 | Power semiconductor chip, includes the submodule group and compression joint type package module of the chip |
| CN109817612A (en) * | 2019-03-14 | 2019-05-28 | 华北电力大学 | A kind of encapsulating structure improving solder type silicon carbide power module electric heating property |
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| CN112234054A (en) * | 2020-10-28 | 2021-01-15 | 南瑞联研半导体有限责任公司 | Multi-chip parallel half-bridge IGBT module |
| CN113711351A (en) * | 2019-04-18 | 2021-11-26 | 日立能源瑞士股份公司 | Power semiconductor module with laser-welded lead frame |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7172326B2 (en) * | 2018-09-14 | 2022-11-16 | 富士電機株式会社 | Semiconductor units, semiconductor modules and semiconductor devices |
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2022
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08191239A (en) * | 1995-01-11 | 1996-07-23 | Hitachi Ltd | Power semiconductor module |
| JP2009105454A (en) * | 2009-02-10 | 2009-05-14 | Mitsubishi Electric Corp | Power semiconductor module |
| CN110050339A (en) * | 2016-12-16 | 2019-07-23 | Abb瑞士股份有限公司 | Power semiconductor modular with low gate vias inductance |
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