CN115881652B - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN115881652B CN115881652B CN202211562316.0A CN202211562316A CN115881652B CN 115881652 B CN115881652 B CN 115881652B CN 202211562316 A CN202211562316 A CN 202211562316A CN 115881652 B CN115881652 B CN 115881652B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 160
- 239000010410 layer Substances 0.000 claims description 86
- 239000002184 metal Substances 0.000 claims description 52
- 229910052751 metal Inorganic materials 0.000 claims description 52
- 239000004033 plastic Substances 0.000 claims description 36
- 229910000679 solder Inorganic materials 0.000 claims description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 24
- 239000010949 copper Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 15
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 230000010354 integration Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 9
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- 230000000903 blocking effect Effects 0.000 description 4
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- 230000002093 peripheral effect Effects 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000007822 coupling agent Substances 0.000 description 1
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- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Abstract
The invention discloses a chip packaging structure and a manufacturing method thereof, wherein the chip packaging structure comprises a light-transmitting substrate, a light-transmitting substrate and a packaging substrate, wherein the light-transmitting substrate is provided with an upper surface and a lower surface opposite to the upper surface; the fan-out substrate is arranged on the lower surface of the light-transmitting substrate, and at least one opening is arranged in a partial area of the fan-out substrate; the upper surface of the first chip is provided with a photosensitive area, is arranged on the lower surface of the fan-out substrate towards the light-transmitting substrate, is electrically connected with the fan-out substrate, and is exposed by the opening; the second chip comprises a functional surface provided with a bonding pad and a nonfunctional surface opposite to the functional surface, and the nonfunctional surface of the second chip faces the first chip and is arranged on the lower surface of the first chip; the fan-out substrate and the second chip are arranged above the circuit board and are respectively and electrically connected with the circuit board. The invention realizes the packaging structure of stacking a plurality of chips, improves the integration level of chip packaging and effectively reduces the size of the packaging body.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a manufacturing method thereof.
Background
An image sensor chip is an electronic device capable of sensing external light and converting it into an electrical signal, and is generally manufactured by a semiconductor manufacturing process. After the image sensor chip is manufactured, a series of packaging processes are performed on the image sensor chip to form a packaged packaging structure, so that the image sensor chip is used for various electronic devices such as digital cameras, digital video cameras and the like.
As shown in fig. 1, in a chip packaging structure in the prior art, at least one image sensing chip 2 'and at least one optical chip or electrical chip 3' are disposed on a substrate 1', the upper surface of the image sensing chip 2' is provided with a photosensitive area and an electrical bonding pad, and the photosensitive area and the electrical bonding pad are connected with the electrical bonding pad on the upper surface of the image sensing chip 2 'and the electrical bonding pad on the upper surface of the substrate 1' through metal bonding wires, so as to realize electrical connection between the image sensing chip 2 'and the substrate 1'; fixing the light-transmitting glass 4 'on the image sensing chip 2' through an adhesive film or glue so as to form a light-transmitting area; the optical chip or the electric chip 3 'is arranged on the upper surface of the substrate 1' through a flip-chip bonding process; finally, covering the unshielded upper surface of the substrate 1 'by using a plastic packaging material to form a plastic packaging body 5', wherein the upper surface of the plastic packaging body 5 'and the upper surface of the light-transmitting glass 4' are positioned at the same horizontal plane; finally, the substrate 1 'is soldered to the external circuit board 6'.
However, the multiple chips in the existing package structure are often disposed on the same side of the substrate, so that the integration level is poor, and the size of the packaged product is large, which is not beneficial to the miniaturization development of the electronic product.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a manufacturing method thereof, which improve the integration level of chip packaging and effectively reduce the size of a packaging body.
In order to achieve the above object, the present invention provides a chip package structure, comprising:
a transparent substrate having an upper surface and a lower surface opposite to the upper surface;
The fan-out substrate is arranged on the lower surface of the light-transmitting substrate, and at least one opening is arranged in a part of the area of the fan-out substrate;
the upper surface of the first chip is provided with a photosensitive area, the upper surface of the first chip faces the light-transmitting substrate and is arranged on the lower surface of the fan-out substrate and is electrically connected with the fan-out substrate, and the opening exposes the photosensitive area;
the second chip comprises a functional surface provided with a bonding pad and a nonfunctional surface opposite to the functional surface, and the nonfunctional surface of the second chip faces the first chip and is arranged on the lower surface of the first chip;
The fan-out substrate and the second chip are arranged above the circuit board and are respectively and electrically connected with the circuit board.
As a further improvement of an embodiment of the present invention, a plurality of first conductive connectors are disposed on the lower surface of the fan-out substrate, and the fan-out substrate is electrically connected to the circuit board through the first conductive connectors.
As a further improvement of an embodiment of the present invention, a plurality of second conductive connectors are disposed between the second chip and the circuit board, and the second conductive connectors connect the bonding pads on the lower surface of the second chip and the bonding pads on the upper surface of the circuit board.
As a further improvement of an embodiment of the present invention, a heat conducting glue layer is disposed between the first chip and the second chip.
As a further improvement of an embodiment of the present invention, the fan-out device further includes a plastic package body, wherein the plastic package body covers the lower surface of the fan-out substrate, the side surface of the first conductive connecting piece, the side surface of the first chip, and the side surfaces of the light-transmitting substrate and the fan-out substrate, and the lower surface of the plastic package body and the lower surface of the first chip are located at the same horizontal plane; the first conductive connecting piece comprises a copper column and a metal solder ball which are connected with each other, wherein the copper column is arranged in the plastic package body and is electrically connected with the fan-out substrate, and the metal solder ball is electrically connected with a bonding pad on the upper surface of the circuit board.
As a further improvement of an embodiment of the invention, the fan-out substrate is a rewiring layer and sequentially comprises an insulating layer, a metal layer and a solder mask layer, wherein the insulating layer, the metal layer and the solder mask layer are arranged on the lower surface of the light-transmitting substrate, a plurality of grooves exposing the metal layer are formed in the lower surface of the plastic package body, and the copper columns are arranged in the grooves and connected with the metal layer.
The invention also provides a manufacturing method of the chip packaging structure, which comprises the following steps:
Providing a light-transmitting substrate;
A fan-out substrate is arranged on the lower surface of the light-transmitting substrate, and at least one opening is formed in a part of the area of the fan-out substrate;
providing at least one first chip, wherein a photosensitive area is arranged on the upper surface of the first chip, the upper surface of the first chip is arranged on the lower surface of the fan-out substrate towards the light-transmitting substrate and is electrically connected with the fan-out substrate, and the opening exposes the photosensitive area;
Providing at least one second chip, wherein the second chip comprises a functional surface provided with a bonding pad and a nonfunctional surface opposite to the functional surface, and the nonfunctional surface of the second chip faces the first chip and is arranged on the lower surface of the first chip;
Providing a circuit board, arranging the fan-out substrate and the second chip above the circuit board, and realizing the electric connection between the fan-out substrate and the second chip and the circuit board respectively.
As a further improvement of an embodiment of the present invention, the step of disposing a fan-out substrate on the lower surface of the light-transmitting substrate and forming at least one opening in a partial region of the fan-out substrate specifically includes:
manufacturing a rewiring layer on the lower surface of the light-transmitting substrate, wherein the rewiring layer sequentially comprises an insulating layer, a metal layer and a solder mask layer which are formed on the lower surface of the light-transmitting substrate;
And forming at least one opening in a partial area of the rewiring layer, wherein the opening is communicated with the upper surface and the lower surface of the rewiring layer.
As a further improvement of an embodiment of the present invention, before providing at least one second chip, the method further comprises the steps of:
Providing a plastic package material, covering the lower surface of the rewiring layer, the side surface of the first chip, the light-transmitting substrate and the side surface of the rewiring layer with the plastic package material to form a plastic package body, and enabling the plastic package body and the lower surface of the first chip to be positioned on the same horizontal plane;
a plurality of grooves are formed on the lower surface of the plastic package body in an inward concave manner, and the grooves expose the metal layer;
And manufacturing copper columns in the grooves.
As a further improvement of an embodiment of the present invention, the disposing the fan-out substrate and the second chip above the circuit board, and implementing electrical connection between the fan-out substrate and the second chip and the circuit board, specifically includes:
Manufacturing a metal solder ball on the lower surface of the copper column, wherein the metal solder ball and the copper column are provided with a first conductive connecting piece, so that the fan-out substrate is arranged above the circuit board through the first conductive connecting piece, and the fan-out substrate is electrically connected with the circuit board;
Manufacturing a second conductive connecting piece at a bonding pad on the functional surface of a second chip, wherein the second chip is arranged above the circuit board through the second conductive connecting piece, and realizes the electrical connection between the second chip and the circuit board;
the lower surface of the formed metal solder ball and the lower surface of the second conductive connecting piece are positioned on the same plane.
The invention has the beneficial effects that: compared with the prior art that all chips are integrated on one side surface of the substrate, the package structure with multiple chips stacked is realized through the fan-out substrate, the integration level of chip package is improved, and the size of the package body is effectively reduced.
Drawings
Fig. 1 is a schematic structural diagram of a chip package structure in the prior art.
Fig. 2 is a schematic structural diagram of a chip package structure according to an embodiment of the invention.
Fig. 3 is a flow chart illustrating a method for manufacturing a chip package structure according to an embodiment of the invention.
Fig. 4 to 11 are process step diagrams of a method for manufacturing a corresponding chip package structure according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below in conjunction with the detailed description of the present invention and the corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
For purposes of illustration, terms such as "upper," "lower," "rear," "front," and the like, are used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may include different orientations of the device in use or operation than that illustrated in the figures. For example, if the device in the figures is turned over, elements described as "below" or "over" other elements or features would then be oriented "below" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
As shown in fig. 2, the present embodiment provides a chip package structure, which includes a light-transmitting substrate 1, a fan-out substrate 2, at least one first chip 3, at least one second chip 4, and a circuit board 5.
The light-transmitting substrate 1 is a light-transmitting glass substrate having an upper surface and a lower surface opposite to the upper surface.
In other embodiments of the present invention, the transparent substrate 1 may be another transparent substrate with high transmittance, such as a transparent PI substrate, a high-transmittance pc board, and the like. The size of the light-transmitting substrate 1 is not limited in the present invention, and the vertical projection of the light-transmitting substrate on the first chip 3 can completely cover the photosensitive area on the first chip 3.
The fan-out substrate 2 is disposed on the lower surface of the light-transmitting substrate 1, and at least one opening 21 is disposed in a partial area thereof, wherein the opening 21 is completely disposed on the upper surface of the first chip 3.
The first chip 3 is an optical chip, specifically, the first chip 3 is an image sensing chip, the upper surface of the image sensing chip is provided with a photosensitive area 31, the upper surface of the first chip 3 is arranged on the lower surface of the fan-out substrate 2 towards the light-transmitting substrate 1 and is electrically connected with the fan-out substrate 2, and the opening 21 of the fan-out substrate 2 completely exposes the photosensitive area 31 on the upper surface of the first chip 3.
Illustratively, in the present embodiment, a first chip 3 is disposed, and the fan-out substrate 2 is provided with an opening 21 in a region opposite to the first chip 3 in a vertical direction with respect to the first chip 3, and the opening 21 completely exposes the photosensitive region 31 on the upper surface of the first chip 3.
Of course, in other embodiments of the present invention, a plurality of first chips 3 having photosensitive areas 31 may be provided, and a corresponding number of openings 21 are provided at positions of the fan-out substrate 2 corresponding to the photosensitive areas 31, so as to achieve different requirements corresponding to products.
In the embodiment of the present invention, the fan-out substrate 2 is a rewiring layer, and sequentially includes an insulating layer 22, a metal layer 23 and a solder mask layer 24, which are disposed on the lower surface of the light-transmitting substrate 1.
The first chip 3 is disposed on the lower surface of the solder mask layer 24 and electrically connected to the fan-out substrate 2. Specifically, the upper surface of the first chip 3 is further provided with a plurality of electrical bonding pads, the metal layer 23 is exposed in a part of the rewiring layer area close to the electrical bonding pads on the upper surface of the first chip 3, balls can be planted in the electrical bonding pads on the upper surface of the first chip 3, and the electrical bonding pads on the upper surface of the first chip 3 are connected with the metal layer 23 through the planted balls, so that the electrical connection between the first chip 3 and the rewiring layer is realized. Preferably, the implant balls are solder balls.
Of course, the manner of implementing the electrical connection between the first chip 3 and the rewiring layer is not limited thereto, and other solder balls or pillars for conducting electricity can be disposed between the electrical pads on the upper surface of the first chip 3 and the metal layer 23, and the invention is not limited thereto, and can be selected according to the actual manufacturing process or product requirements.
In other embodiments of the present invention, the fan-out substrate 2 may be a copper-clad plate with a plurality of metal electrodes disposed on the lower surface, and may be electrically connected to the first chip 3 and the circuit board 5 at the same time.
Further, a blocking layer 6 is further disposed on the peripheral side of the ball-planting portion at the electrical bonding pad on the upper surface of the first chip 3, and the blocking layer 6 is disposed around the peripheral side of the first chip 3 and connects the first chip 3 with the rewiring layer, so as to block the plastic package material from entering the space enclosed by the first chip 3 and the opening 21 of the fan-out substrate 2 in the subsequent injection molding process, thereby polluting the photosensitive area 31 and affecting the light receiving performance of the packaged product.
The second chip 4 includes a functional surface provided with a bonding pad and a nonfunctional surface opposite to the functional surface, and the nonfunctional surface of the second chip 4 faces the first chip 3 and is disposed on the lower surface of the first chip 3. That is, in fig. 2, the lower surface of the second chip 4 is a functional surface provided with bonding pads, and the upper surface of the second chip 4 is a nonfunctional surface.
The second chip 4 can be an optical chip or an electrical chip, the invention does not limit the variety of functions of the second chip 4 and the number of the second chip 4 integrated on the lower surface of the first chip 3, and the design can be adjusted according to the application requirements of actual products.
The circuit board 5 is specifically a PCB board, and a plurality of pads are disposed on an upper surface of the circuit board 5, and the fan-out substrate 2 and the second chip 4 are disposed above the circuit board 5 and are electrically connected with the circuit board 5 respectively. That is, the external light directly reaches the photosensitive area 31 of the first chip 3 through the light-transmitting substrate 1, and then the first chip 3 transmits the acquired signal to the fan-out substrate 2, and the acquired signal is transmitted to the circuit board 5 through the fan-out substrate 2, and the signal is processed by the circuit board 5; or the circuit board 5 receives the signal of the first chip 3, and then transmits the signal to the second chip 4, and the second chip 4 performs calculation processing; or other optical signals or electrical signals received by the second chip 4 are transmitted to the circuit board 5, and the circuit board 5 performs signal processing.
Specifically, a plurality of first conductive connectors 7 are disposed on the lower surface of the fan-out substrate 2, and the fan-out substrate 2 is electrically connected to the circuit board 5 through the first conductive connectors 7.
Further, the packaging structure further comprises a plastic packaging body 8, the plastic packaging body 8 covers the lower surface of the fan-out substrate 2, part of the side surface of the first conductive connecting piece 7, the side surface of the first chip 3, and the side surfaces of the light-transmitting substrate 1 and the fan-out substrate 2, and the lower surface of the plastic packaging body 7 and the lower surface of the first chip 3 are located on the same horizontal plane. The plastic package body 8 uses epoxy resin as a matrix, and is added with additives such as a curing agent, a coupling agent and the like, so as to play roles of sealing protection and mechanical support on the light-transmitting substrate 1, the fan-out substrate 2 and the first chip 3.
The first conductive connection piece 7 includes a copper pillar 71 and a metal solder ball 72 that are connected to each other, the copper pillar 71 is disposed in the plastic package 8 and electrically connected to the fan-out substrate 2, and the metal solder ball 72 is electrically connected to a bonding pad on the upper surface of the circuit board 5.
The lower surface of the plastic package body 8 is provided with a plurality of grooves exposing the metal layer 23, the copper pillars 71 are arranged in the grooves, and the upper surfaces of the copper pillars 71 are connected with the metal layer 23. I.e. the fan-out substrate 2 is electrically connected to the circuit board 5 via copper pillars 71 and metal solder balls 72.
Of course, the material and specific shape of the first conductive connecting piece 7 formed by the present invention are not limited, and the first conductive connecting piece is not limited to a copper pillar, and the first conductive connecting piece may be made of other conductive materials, and the metal solder ball 72 may be a tin ball, a copper ball, or a sphere or a cylinder made of other conductive materials.
A plurality of second conductive connecting pieces 9 are arranged between the second chip 4 and the circuit board 5, and the second conductive connecting pieces 9 are connected with a bonding pad on the lower surface of the second chip 4 and a bonding pad on the upper surface of the circuit board 5, so that the electrical connection between the second chip 4 and the circuit board 5 is realized.
In the embodiment of the invention, the second conductive connecting piece 9 is a metal column, preferably a copper column, so that the second conductive connecting piece 9 can also play a certain supporting role on the first chip 3 and the second chip 4 while the electric connection function can be realized, the stability of the packaging structure is further enhanced, and the risk of lowering the product performance caused by tilting or vibration of the first chip 3 and the second chip 4 in the packaging process or in the working process is prevented.
Of course, in other embodiments of the present invention, the material of the second conductive connection member 9 is not limited to metal, but may be other materials that can be used for electrical conduction, and the shape of the second conductive connection member 9 is not limited to a cylinder, and may be a metal solder ball, such as a solder ball.
Further, a rewiring layer may be further disposed on the lower surface of the second chip 4 and electrically connected to the rewiring layer, and a second conductive connector 9 is disposed between the rewiring layer and the circuit board 5, so as to electrically connect the rewiring layer and the circuit board 5. The arrangement of the rewiring layer on the lower surface of the second chip 4 can enlarge the area of the bonding pad of the second chip 4, and corresponds to the functions required to be realized by different products.
Furthermore, a thermal conductive adhesive layer 10 is disposed between the first chip 3 and the second chip 4, and the thermal conductive adhesive layer 10 is made of a glue material with thermal conductivity and adhesion.
Meanwhile, the second conductive connecting piece 9 is a metal column, which not only plays a role in realizing the electrical connection between the second chip 4 and the circuit board 5, but also can transfer the heat generated by the first chip 3 and the second chip 4 to the circuit board 5 through the second conductive connecting piece 7, and then the heat is transferred to the outside air through the circuit board 5.
It should be noted that, in the direction perpendicular to the upper surface of the light-transmitting substrate 1, the forming height of the metal solder balls 72, the thickness of the heat conductive adhesive layer 10, and the height of the second conductive connecting piece 9 are not limited in the present invention, and may be adjusted according to the actual manufacturing process or product requirement, only by ensuring that the lower surfaces of the metal solder balls 72 and the lower surfaces of the second conductive connecting pieces 9 are at the same horizontal plane.
The invention also provides a manufacturing method of the chip packaging structure, as shown in fig. 3, the manufacturing method comprises the following steps:
s1: a transparent substrate is provided.
S2: a fan-out substrate is arranged on the lower surface of the light-transmitting substrate, and at least one opening is formed in a part of the area of the fan-out substrate.
S3: at least one first chip is provided, a photosensitive area is arranged on the upper surface of the first chip, the upper surface of the first chip faces the light-transmitting substrate and is arranged on the lower surface of the fan-out substrate and is electrically connected with the fan-out substrate, and the photosensitive area is exposed through the opening.
S4: at least one second chip is provided, the second chip comprises a functional surface provided with a bonding pad and a nonfunctional surface opposite to the functional surface, and the nonfunctional surface of the second chip faces the first chip and is arranged on the lower surface of the first chip.
S5: and providing a circuit board, arranging the fan-out substrate and the second chip above the circuit board, and realizing the electric connection between the fan-out substrate and the second chip and the circuit board respectively.
As shown in fig. 4, a transparent substrate 1 is provided, and in particular, the transparent substrate 1 is a transparent glass substrate, which has an upper surface and a lower surface opposite to the upper surface.
In other embodiments of the present invention, the transparent substrate 1 may be another transparent substrate with high transmittance, such as a transparent PI substrate, a high-transmittance pc board, and the like. The size of the light-transmitting substrate 1 is not limited in the present invention, and the vertical projection of the light-transmitting substrate on the first chip 3 can completely cover the photosensitive area 31 on the upper surface of the first chip 3.
In step S2, a fan-out substrate 2 is disposed on the lower surface of the light-transmitting substrate 1, and at least one opening 21 is formed in a partial area of the fan-out substrate 2, which specifically includes:
as shown in fig. 5, a rewiring layer is formed on the lower surface of the light-transmitting substrate 1, and the rewiring layer sequentially includes an insulating layer 22, a metal layer 23, and a solder resist layer 24 formed on the lower surface of the light-transmitting substrate 1.
At least one opening 21 is formed in a partial region of the rewiring layer, the opening 21 communicating with the upper and lower surfaces of the rewiring layer.
In step S3, at least one first chip 3 is provided, the upper surface of the first chip 3 is provided with a photosensitive area 31, the upper surface of the first chip 3 is disposed on the lower surface of the fan-out substrate 2 towards the light-transmitting substrate 1 and is electrically connected with the fan-out substrate 2, and the opening 21 exposes the photosensitive area 31, which specifically includes:
As shown in fig. 6, an exemplary first chip 3 is provided, the first chip 3 is an optical chip, preferably an image sensing chip, a surface with a photosensitive area 31 is disposed on the lower surface of the rewiring layer towards the light-transmitting substrate 1, specifically, the upper surface of the first chip 3 is further provided with a plurality of electrical bonding pads, a part of the rewiring layer area near the electrical bonding pads on the upper surface of the first chip 3 is formed with a recess to expose the metal layer 23, balls can be planted on the electrical bonding pads on the upper surface of the first chip 3, and the electrical bonding pads on the upper surface of the first chip 3 are connected with the metal layer 23 through the planted balls, so that the electrical connection between the first chip 3 and the rewiring layer is realized. Preferably, the implant balls are solder balls.
Of course, the manner of implementing the electrical connection between the first chip 3 and the rewiring layer is not limited thereto, and other solder balls or pillars for conducting electricity can be disposed between the electrical pads on the upper surface of the first chip 3 and the metal layer 23, and the invention is not limited thereto, and can be selected according to the actual manufacturing process or product requirements.
In other embodiments of the present invention, in step S3, a plurality of first chips 3 having photosensitive areas 31 may be provided, and a plurality of through holes 21 are formed corresponding to the fan-out substrate 2 areas to meet different requirements of the packaged product.
Further, after step S3, the method further includes the steps of: a blocking layer 6 is formed on the peripheral side of the ball-planting part at the electrical bonding pad on the upper surface of the first chip 3, the blocking layer 6 surrounds the peripheral side of the first chip 3 and connects the first chip 3 with the rewiring layer so as to prevent the plastic package material from entering the space surrounded by the first chip 3 and the opening 21 of the fan-out substrate 2 in the subsequent injection molding process, thereby polluting the photosensitive area 31 and affecting the light receiving performance of the packaged product.
Before step S4, the method further comprises the steps of:
Sa: providing a plastic package material, covering the lower surface of the rewiring layer, the side surface of the first chip 3, and the side surfaces of the light-transmitting substrate 1 and the rewiring layer with the plastic package material to form a plastic package body 8, and enabling the plastic package body 8 and the lower surface of the first chip 3 to be located on the same horizontal plane, as shown in fig. 7.
Sb: a plurality of grooves 81 are formed on the lower surface of the plastic package 8 by recessing inwards, and the grooves 81 expose the metal layer 23, as shown in fig. 8.
Sc: copper pillars 71 are formed in the grooves 81 as shown in fig. 9.
As shown in fig. 10, corresponding to step S4, a second chip 4 is provided, the second chip 4 includes a functional surface provided with a bonding pad and a non-functional surface opposite to the functional surface, the non-functional surface of the second chip 4 faces the first chip 3, and a thermal conductive adhesive layer 10 is disposed on the lower surface of the first chip 3, and the thermal conductive adhesive layer 10 is made of a glue material having thermal conductivity and adhesiveness.
The second chip 4 can be an optical chip or an electrical chip, the invention does not limit the variety of functions of the second chip 4 and the number of the second chip 4 integrated on the lower surface of the first chip 3, and the design can be adjusted according to the application requirements of actual products.
In step S5, a circuit board 5 is provided, the fan-out substrate 2 and the second chip 4 are disposed above the circuit board 5, and the fan-out substrate 2 and the second chip 4 are electrically connected to the circuit board 5 respectively, which specifically includes:
The circuit board 5 is specifically a PCB board, the upper surface of which is provided with a plurality of pads, as shown in fig. 11, a metal solder ball 72 is fabricated on the lower surface of the copper pillar 71, and the metal solder ball 72 is connected with the copper pillar 71 to form the first conductive connection piece 7 in the present invention, so that the fan-out substrate 2 is disposed above the circuit board 5 through the first conductive connection piece 7, and the electrical connection between the fan-out substrate 2 and the circuit board 5 is achieved.
Further, a second conductive connecting piece 9 is fabricated at a bonding pad on the functional surface of the second chip 4, and the second chip 4 is disposed above the circuit board 5 through the second conductive connecting piece 9, and electrical connection between the second chip 4 and the circuit board 5 is achieved.
In the embodiment of the invention, the second conductive connecting piece 9 is made of a metal column, preferably a copper column, so that the second conductive connecting piece 9 can play a certain supporting role on the first chip 3 and the second chip 4 while the electric connection function can be realized, the stability of the packaging structure is further enhanced, and the risk of lowering the product performance caused by tilting or vibration of the first chip 3 and the second chip 4 in the packaging process or in the working process is prevented.
Of course, in other embodiments of the present invention, the material of the second conductive connection member 9 is not limited to metal, but may be other materials that can be used for electrical conduction, and the shape of the second conductive connection member 9 is not limited to a cylinder, and may be a metal solder ball, such as a solder ball.
The fan-out substrate 2 and the second chip 4 are disposed above the circuit board 5 through the first conductive connection 7 and the second conductive connection 9, and the package structure shown in fig. 2 is fabricated and formed.
Further, a rewiring layer may be formed on the lower surface of the second chip 4, and electrically connected to the rewiring layer, and a second conductive connector 9 is further disposed between the rewiring layer and the circuit board 5, so as to electrically connect the rewiring layer and the circuit board 5. The arrangement of the rewiring layer on the lower surface of the second chip 4 can enlarge the area of the bonding pad of the second chip 4, and corresponds to the functions required to be realized by different products.
Of course, the lower surfaces of the first conductive connecting member 7 and the second conductive connecting member 9 are connected to different pads on the upper surface of the circuit board 5, and it should be noted that the lower surfaces of the metal solder balls 72 formed by the manufacturing process and the lower surfaces of the second conductive connecting members 9 are required to be in the same plane, so as to ensure the solderability and stability of the whole package structure.
In summary, the fan-out substrate is used to realize the package structure with multiple stacked chips, and compared with the prior art that all chips are integrated on one side of the substrate, the invention improves the integration level of chip package and effectively reduces the size of the package body. In addition, the second conductive connecting piece is arranged to be a metal column, so that the stability of the packaging structure can be improved, and meanwhile, heat generated by the first chip and the second chip can be transferred to the circuit board, and the heat dissipation performance of the packaging structure is improved.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (3)
1. A chip package structure, comprising:
a transparent substrate having an upper surface and a lower surface opposite to the upper surface;
The fan-out substrate is arranged on the lower surface of the light-transmitting substrate, and at least one opening is arranged in a part of the area of the fan-out substrate;
the upper surface of the first chip is provided with a photosensitive area, the upper surface of the first chip faces the light-transmitting substrate and is arranged on the lower surface of the fan-out substrate and is electrically connected with the fan-out substrate, and the opening exposes the photosensitive area;
the second chip comprises a functional surface provided with a bonding pad and a nonfunctional surface opposite to the functional surface, and the nonfunctional surface of the second chip faces the first chip and is arranged on the lower surface of the first chip;
The fan-out substrate and the second chip are arranged above the circuit board and are respectively and electrically connected with the circuit board;
The fan-out substrate is electrically connected with the circuit board through the first conductive connecting pieces; a heat conducting adhesive layer is arranged between the first chip and the second chip, a plurality of second conductive connecting pieces are arranged between the second chip and the circuit board, and the second conductive connecting pieces are connected with a bonding pad on the lower surface of the second chip and a bonding pad on the upper surface of the circuit board;
The fan-out substrate comprises a fan-out substrate, a first conductive connecting piece, a first chip, a light-transmitting substrate, a fan-out substrate, a first chip, a second chip, a first conductive connecting piece, a second conductive connecting piece, a first chip and a second conductive connecting piece, and further comprises a plastic package body, wherein the plastic package body covers the lower surface of the fan-out substrate, the side surface of the first conductive connecting piece, the side surface of the first chip, the light-transmitting substrate and the side surface of the fan-out substrate, and the lower surface of the plastic package body and the lower surface of the first chip are located at the same horizontal plane; the first conductive connecting piece comprises a copper column and a metal solder ball which are connected with each other, wherein the copper column is arranged in the plastic package body and is electrically connected with the fan-out substrate, and the metal solder ball is electrically connected with a bonding pad on the upper surface of the circuit board.
2. The chip package structure of claim 1, wherein the fan-out substrate is a rewiring layer, the rewiring layer sequentially comprises an insulating layer, a metal layer and a solder mask layer, the insulating layer, the metal layer and the solder mask layer are arranged on the lower surface of the light-transmitting substrate, a plurality of grooves exposing the metal layer are formed in the lower surface of the plastic package body, and the copper columns are arranged in the grooves and connected with the metal layer.
3. The manufacturing method of the chip packaging structure is characterized by comprising the following steps:
Providing a light-transmitting substrate;
a fan-out substrate is disposed on the lower surface of the light-transmitting substrate, and at least one opening is formed in a partial region of the fan-out substrate, which specifically includes:
manufacturing a rewiring layer on the lower surface of the light-transmitting substrate, wherein the rewiring layer sequentially comprises an insulating layer, a metal layer and a solder mask layer which are formed on the lower surface of the light-transmitting substrate;
forming at least one opening in a partial area of the rewiring layer, wherein the opening is communicated with the upper surface and the lower surface of the rewiring layer;
providing at least one first chip, wherein a photosensitive area is arranged on the upper surface of the first chip, the upper surface of the first chip is arranged on the lower surface of the fan-out substrate towards the light-transmitting substrate and is electrically connected with the fan-out substrate, and the opening exposes the photosensitive area;
Providing a plastic package material, covering the lower surface of the rewiring layer, the side surface of the first chip, the light-transmitting substrate and the side surface of the rewiring layer with the plastic package material to form a plastic package body, and enabling the plastic package body and the lower surface of the first chip to be positioned on the same horizontal plane;
a plurality of grooves are formed on the lower surface of the plastic package body in an inward concave manner, and the grooves expose the metal layer;
manufacturing a copper column in the groove;
Providing at least one second chip, wherein the second chip comprises a functional surface provided with a bonding pad and a non-functional surface opposite to the functional surface, the non-functional surface of the second chip faces the first chip, and the second chip is arranged on the lower surface of the first chip through a heat conducting adhesive layer;
providing a circuit board, arranging the fan-out substrate and the second chip above the circuit board, and realizing the electrical connection between the fan-out substrate and the second chip and the circuit board respectively, specifically comprising:
Manufacturing a metal solder ball on the lower surface of the copper column, wherein the metal solder ball and the copper column are provided with a first conductive connecting piece, so that the fan-out substrate is arranged above the circuit board through the first conductive connecting piece, and the fan-out substrate is electrically connected with the circuit board;
Manufacturing a second conductive connecting piece at a bonding pad on the functional surface of the second chip, wherein the second chip is arranged above the circuit board through the second conductive connecting piece, and realizes the electrical connection between the second chip and the circuit board;
the lower surface of the metal solder ball formed by manufacturing is in the same plane with the lower surface of the second conductive connecting piece.
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| CN202211562316.0A CN115881652B (en) | 2022-12-07 | 2022-12-07 | Chip packaging structure and manufacturing method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112166504A (en) * | 2018-06-13 | 2021-01-01 | 索尼半导体解决方案公司 | Image pickup apparatus |
| CN115000104A (en) * | 2022-05-27 | 2022-09-02 | 长电科技管理有限公司 | Light-permeable chip packaging structure and manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2009267122A (en) * | 2008-04-25 | 2009-11-12 | Oki Semiconductor Co Ltd | Semiconductor device |
| KR20220070766A (en) * | 2020-11-23 | 2022-05-31 | 삼성전자주식회사 | Image sensor package including glass substrate |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112166504A (en) * | 2018-06-13 | 2021-01-01 | 索尼半导体解决方案公司 | Image pickup apparatus |
| CN115000104A (en) * | 2022-05-27 | 2022-09-02 | 长电科技管理有限公司 | Light-permeable chip packaging structure and manufacturing method |
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