CN115000104A - Light-permeable chip packaging structure and manufacturing method - Google Patents
Light-permeable chip packaging structure and manufacturing method Download PDFInfo
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- CN115000104A CN115000104A CN202210588545.3A CN202210588545A CN115000104A CN 115000104 A CN115000104 A CN 115000104A CN 202210588545 A CN202210588545 A CN 202210588545A CN 115000104 A CN115000104 A CN 115000104A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
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Abstract
The invention relates to the technical field of chip packaging, in particular to a light-permeable chip packaging structure and a manufacturing method thereof, wherein the light-permeable chip packaging structure forms a first rewiring layer on the surface of a transparent carrier plate, the first rewiring layer is provided with a chip packaging window exposing the transparent carrier plate, a chip structure is arranged on the corresponding chip packaging window, the front surface of the chip structure faces the transparent carrier plate, and packaging material layers are formed on the back surface of the chip structure and the surface of the first rewiring layer; and forming a second rewiring layer on the surface of the packaging material layer, wherein the second rewiring layer is used as a substrate of the chip packaging structure. The external solder balls formed on the surface of the second re-wiring layer can cover the back of the whole chip packaging structure, so that the number of I/O supported by the chip is greatly increased. Meanwhile, the chip packaging structure is suitable for a wafer level packaging process, the UPH is high, and the manufacturing cost of the packaging structure is low.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a light-permeable chip packaging structure and a manufacturing method thereof.
Background
At present, the traditional light sensor and image sensor package is generally packaged in a wire bonding mode, and a transparent cover is arranged above a sensor chip to realize light transmission and sealing protection of the sensor chip. However, the above structure has some problems, such as poor heat dissipation performance of the formed chip packaging structure, which affects the imaging performance of the sensor chip, and complicated process in the traditional light sensor packaging process.
With the demand for miniaturization of devices, flip chips are becoming a trend, but in conventional flip chip packaging structures, the functional surface of the chip faces downward, and due to the blocking of the substrate, light cannot be transmitted, and the flip chip packaging structures are not suitable for light sensors and image sensor chips.
To this end, a package structure based on a flip-chip image sensor chip has been proposed, and referring to fig. 1, the package structure includes: the device comprises a substrate 1, wherein a through window 3 is formed in the substrate 1, and wiring structures 2 are arranged on the front surface and the back surface of the substrate 1 and are electrically connected with each other; the inverted image sensor chip 4 is attached to the back surface of the substrate 1, and the functional surface of the image sensor chip 4 faces the transparent window 3; the image sensor chip 4 is electrically connected to the wiring structure 6 on the surface; the glass 5 is fixed on the front surface of the substrate 1 and completely covers the through window 3; the heat sink 10 is bonded to the back of the image sensor chip 4 by a heat dissipating adhesive; the passive device 7 and the image sensor driving chip 8 are attached to the part of the substrate 1 except the front transparent window 3 and are electrically connected with the wiring structure 2 on the front side; BGA solder balls 9 are implanted in the area where the wiring structure 2 is located on the back surface of the substrate 1, and the BGA solder balls 9 are electrically connected to the wiring structure 2.
However, the above structure has the following three problems: 1. the back of the image sensor chip 4 is exposed, which is not favorable for the reliability of the chip and the connection; 2. the structure is not suitable for wafer level packaging, only can be used for packaging singly, and has low UPH and high cost; 3. since the BGA solder balls 9 can be attached only to the periphery of the image sensor chip 4, the number of supported I/os is small.
Disclosure of Invention
The invention provides a light-permeable chip packaging structure and a manufacturing method thereof, aiming at overcoming the defects of the prior art.
In order to achieve the above object, a light-transmittable chip package structure includes:
a transparent carrier plate;
a first redistribution layer located on the surface of the transparent carrier plate, the first redistribution layer having a chip packaging window exposing the transparent carrier plate, the first redistribution layer having a chip connection structure and a first conductive pillar formed on the surface thereof;
the chip structure is arranged on the surface of the first rewiring layer, the front surface of the chip structure penetrates through the chip packaging window to face the transparent carrier plate, and the chip structure is electrically connected with the first rewiring layer through the chip connecting structure;
the packaging material layer is positioned on the back surface of the chip structure and the surface of the first rewiring layer;
and the second rewiring layer is positioned on the surface of the packaging material layer and is used as a substrate of the chip packaging structure, and the second rewiring layer is electrically connected with the first rewiring layer through the first conductive columns.
Optionally, the chip structure is an image sensor chip or a light sensor chip.
Optionally, the number of the chip structures is one or more, and correspondingly, the number of the chip packaging windows is one or more.
Optionally, an external solder ball is formed on the surface of the second redistribution layer.
Optionally, the chip structure includes a front surface and a back surface, the front surface of the chip structure includes a functional region and an electrical connection region located at a periphery of the functional region, the functional region corresponds to the chip packaging window of the first redistribution layer, and the electrical connection region of the chip structure is connected to the chip connection structure of the first redistribution layer, so as to electrically connect the chip structure to the first redistribution layer.
Optionally, the size of the chip package window is smaller than the size of the chip structure, and the amount of light entering is freely adjusted by controlling the size of the chip package window.
The embodiment of the invention provides a manufacturing method of a light-permeable chip packaging structure, which comprises the following steps:
providing a transparent carrier plate, and forming a first rewiring layer on the surface of the transparent carrier plate, wherein the first rewiring layer is provided with a chip packaging window exposing the transparent carrier plate, and a first conductive column and a chip connecting structure are formed on the surface of the first rewiring layer;
providing a chip structure, mounting the chip structure on the surface of the first rewiring layer, and electrically connecting the chip structure with the first rewiring layer through the chip connection structure, wherein the front surface of the chip structure faces the transparent carrier plate through a chip packaging window;
forming a packaging material layer on the surface of the first rewiring layer and the surface of the back face of the chip structure, and grinding the packaging material layer to expose the first conductive columns;
and forming a second re-wiring layer on the surface of the packaging material layer, wherein the second re-wiring layer is used as a substrate of the chip packaging structure, and the second re-wiring layer is electrically connected with the first re-wiring layer through the first conductive pillars.
Optionally, an external solder ball is formed on the surface of the second redistribution layer.
Optionally, a wafer level packaging process is adopted, and the formed chip packaging structure is cut after the external solder balls are formed, so that a single chip packaging structure is formed.
Optionally, the chip structure includes a front surface and a back surface, the front surface of the chip structure includes a functional region and an electrical connection region located at a periphery of the functional region, the functional region corresponds to the chip package window of the first redistribution layer, and the electrical connection region of the chip structure is connected to the chip connection structure of the first redistribution layer, so as to electrically connect the chip structure to the first redistribution layer.
Optionally, when the first redistribution layer is formed, the size of the chip packaging window is smaller than that of the chip structure, and the light inlet amount is freely adjusted by controlling the size of the chip packaging window.
Optionally, the number of the chip structures is one or more, and correspondingly, the number of the chip packaging windows is one or more.
In conclusion, the invention has the beneficial effects that:
the light-permeable chip packaging structure forms a first rewiring layer on the surface of a transparent carrier plate, the first rewiring layer is provided with a chip packaging window exposing the transparent carrier plate, a chip structure is arranged on the corresponding chip packaging window, the front surface of the chip structure faces the transparent carrier plate, and packaging material layers are formed on the back surface of the chip structure and the surface of the first rewiring layer; and forming a second rewiring layer on the surface of the packaging material layer, wherein the second rewiring layer is used as a substrate of the chip packaging structure. Because the second rewiring layer is used as a substrate of the chip packaging structure, the external solder balls formed on the surface of the second rewiring layer can cover the back of the whole chip packaging structure, so that the number of I/O supported by the chip is greatly increased. Meanwhile, the chip packaging structure is suitable for a wafer level packaging process, the UPH is high, and the manufacturing cost of the packaging structure is low. In addition, the packaging material layer is formed and ground, so that a flat surface is provided for the subsequent formation of the second rewiring layer, and the chip structure is packaged inside through the packaging material layer, the upper and lower first rewiring layers and the second rewiring layer, so that the chip structure is not influenced by external extrusion, water vapor and the like, and the stability and reliability of the chip and connection are improved.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic cross-sectional view of a package structure based on a flip-chip image sensor chip in the prior art;
fig. 2 is a schematic flowchart illustrating a method for manufacturing a light-transmissive chip package structure according to an embodiment of the invention;
fig. 3 to 7 are schematic cross-sectional views illustrating a manufacturing process of a light-transmissive chip package structure according to an embodiment of the invention;
fig. 8 is a schematic cross-sectional view of a light-transmissive chip package structure according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail below with reference to specific examples in order to facilitate understanding by those skilled in the art.
The embodiment of the present invention first provides a method for manufacturing a light-permeable chip package structure, please refer to fig. 2, which is a schematic flow chart of the manufacturing method, including:
step S100, providing a transparent carrier plate, and forming a first rewiring layer on the surface of the transparent carrier plate, wherein the first rewiring layer is provided with a chip packaging window exposing the transparent carrier plate, and a first conductive pillar and a chip connecting structure are formed on the surface of the first rewiring layer;
step S200, providing a chip structure, installing the chip structure on the surface of the first rewiring layer, and electrically connecting the chip structure with the first rewiring layer through the chip connecting structure, wherein the front surface of the chip structure faces to the transparent carrier plate through the chip packaging window;
step S300, forming a packaging material layer on the surface of the first redistribution layer and the surface of the back surface of the chip structure, and grinding the packaging material layer to expose the first conductive pillar;
step S400 is to form a second redistribution layer on the surface of the packaging material layer, where the second redistribution layer is used as a substrate of a chip packaging structure, and the second redistribution layer is electrically connected to the first redistribution layer through the first conductive pillar.
Specifically, step 100 is executed, please refer to fig. 3, and a transparent carrier 10 is provided. The transparent carrier plate can be a glass carrier plate or other transparent hard carrier plates, and a first rewiring layer is formed on the surface of the transparent carrier plate subsequently.
Because the wafer-level packaging process is adopted in the embodiment, the transparent carrier plate is firstly utilized to form a plurality of chip packaging structures on the surface of the transparent carrier plate, and the formed chip packaging structures are cut to form single chip packaging structures, the whole packaging process has high UPH and low cost.
In this embodiment, a first redistribution layer 20 is formed on the surface of the transparent carrier 10, the first redistribution layer 20 includes a plurality of redistribution layers (not shown) corresponding to a plurality of chip package structures, and a chip package window 21 is formed in the first redistribution layer 20 corresponding to each chip package structure and exposes the bottom of the transparent carrier 10.
In other embodiments, the first redistribution layer may also be only a redistribution layer corresponding to a single chip package structure.
The size of the chip packaging window 21 is smaller than that of a chip structure to be packaged subsequently, so that the chip structure can be fixed on the first rewiring layer 20 around the chip packaging window 21, the light incoming amount can be freely adjusted by reasonably adjusting the size of the chip packaging window, and the light sensing performance of the chip structure is optimized.
In this embodiment, the number of the chip package windows 21 is 1, and the chip package windows are located in the middle of the first redistribution layer 20 corresponding to one chip package structure. In other embodiments, the first redistribution layer corresponding to one chip package structure has a plurality of chip package windows, and the positions of the chip package windows can be adjusted according to design requirements correspondingly for packaging a plurality of chip structures.
In this embodiment, the first redistribution layer 20 is further formed with first conductive pillars 23 and chip connection structures 22 on the surface.
The chip connection structure 22 is used for fixing and electrically connecting with a chip structure to be packaged subsequently. The chip connection structure 22 is a pad, a solder ball, or a metal post.
The chip connection structure 22 is located at a position of the first redistribution layer 20 close to the chip package window 21, and the first conductive pillar 23 is located at the periphery of the chip connection structure 22, so that the chip structure can be fixedly mounted at a position corresponding to the chip package window. The number of the chip connection structures 22 can be adjusted according to the number of the I/os of the chip. In the packaging structure based on the flip image sensor chip in the prior art, the total size of the packaging structure consists of three parts, namely a functional area of the image sensor chip, a connecting area at the edge of the image sensor chip and a BGA solder ball area.
However, in the embodiment of the present invention, the total size of the package structure is composed of the functional area of the image sensor chip, the connection area (i.e., the chip connection structure) at the edge of the image sensor chip, and the first conductive pillar, and the area occupied by the chip connection structure and the first conductive pillar is small, so that the total size of the entire package structure is small and controllable, and subsequently, an external solder ball may be formed on the surface of the entire second redistribution layer, which is not limited to the size of the package structure, so that the supported I/O number can be greatly increased.
The first conductive pillar 23 is used to electrically connect to a second redistribution layer formed later. In this embodiment, the first conductive pillars 23 are copper pillars, and in other embodiments, the first conductive pillars 23 may also be other interconnect structures. The height of the first conductive pillar 23 is greater than the thickness of the chip structure to be packaged. In this embodiment, the first conductive pillars are formed before the chip structure is mounted, and in other embodiments, the first conductive pillars may also be formed after the chip structure is mounted, or after the packaging material layer is formed, the first conductive pillars are formed in the packaging material layer.
Step 200 is executed, please refer to fig. 4, in which a chip structure 30 is provided, the chip structure 30 is mounted on the surface of the first redistribution layer 20 and electrically connected to the first redistribution layer 20 through the chip connection structure 22, and a front surface of the chip structure 30 faces the transparent carrier 10 through the chip package window 21.
The chip structure 30 is an image sensor chip or a light sensor chip, and the light sensor may be one of a transmission type optical sensor, an optical measurement sensor, an optical mouse sensor, a reflection type optical sensor, and the like.
The chip structure 30 includes a front side and a back side, the front side of the chip structure includes a functional region and an electrical connection region located at the periphery of the functional region, and the electrical connection region of the chip structure is connected to the chip connection structure 22 of the first redistribution layer 20 to fix and electrically connect the chip structure 30 and the first redistribution layer 20.
The functional area on the front side of the chip structure corresponds to the chip package window 21 and faces the transparent carrier 10, and the functional area on the front side of the chip structure has a light sensing unit for converting an optical signal into an electrical signal, so that external light can directly irradiate the surface of the functional area of the chip structure 30 through the transparent carrier 10 to form an electrical signal.
Step S300 is executed, please refer to fig. 5 and fig. 6, a packaging material layer 40 is formed on the surface of the first redistribution layer 20 and the back surface of the chip structure 30, and a thickness of the packaging material layer 40 is greater than a height of the first conductive pillars 23. The encapsulating material layer 40 is ground to expose the first conductive pillars 23.
The packaging material layer 40 is a packaging resin material, such as one of epoxy resin, polyimide, benzocyclobutene, and polybenzoxazine short.
The invention provides a flat surface for the subsequent formation of a second redistribution layer by forming and grinding the encapsulation material layer 40.
According to the invention, the chip structure 30 is packaged in the packaging material layer 40 and the upper and lower first rewiring layers 20 and second rewiring layers 40, so that the chip structure is not influenced by external extrusion, water vapor and the like, and the stability and reliability of the chip and connection are improved.
Step S400 is executed, referring to fig. 7, a second redistribution layer 50 is formed on the surface of the packaging material layer 40, an external solder ball 55 is formed on the surface of the second redistribution layer 50, and the second redistribution layer 50 is used as a substrate of a chip packaging structure.
In this embodiment, the first redistribution layer 20 and the second redistribution layer 50 are electrically connected through the first conductive pillar 23, and the two redistribution layers are used for routing, so that the I/O setting of the chip can be more flexible.
Since the external solder balls 55 may be disposed on the entire surface of the second redistribution layer 50, that is, on the entire back surface of the light-transmissive chip package structure, the number of I/os supported by the chip package structure may be greatly increased, and the chip package structure may be suitable for more types of image sensor chips or light sensor chips.
In this embodiment, by providing the second redistribution layer 50, on one hand, the second redistribution layer is used as a substrate of the chip packaging structure, and no carrier plate needs to be additionally formed, and the two surfaces of the chip packaging structure respectively adopt the transparent carrier plate and the second redistribution layer, so that the overall mechanical strength can meet the packaging requirement, and on the other hand, the two redistribution layers are used for wiring, so that the number of the external solder balls 55 can be greatly increased, and the I/O number of the chip is increased.
Since the wafer level packaging process is adopted in the embodiment, after the processes are formed, the formed chip packaging structures are cut to form a single chip packaging structure.
In other embodiments, when the chip package structure is packaged separately, the chip package structure is completed after external solder balls are formed.
Based on the above manufacturing method, an embodiment of the present invention further provides a light-transmissive chip package structure, please refer to fig. 8, which includes: a transparent carrier plate 10; a first redistribution layer 20 on the surface of the transparent carrier 10, the first redistribution layer 20 having a chip package window 21 exposing the transparent carrier 20, the first redistribution layer 20 having a first conductive pillar 23 and a chip connection structure 22 formed on the surface thereof;
a chip structure 30 mounted on the surface of the first redistribution layer 20, wherein a front surface of the chip structure 30 faces the transparent carrier 10 through the chip package window 21, and the chip structure 30 is electrically connected to the first redistribution layer 20 through the chip connection structure 22;
an encapsulation material layer 40 located on the back surface of the chip structure 30 and the surface of the first redistribution layer 20;
a second redistribution layer 50 on the surface of the packaging material layer 40, where the second redistribution layer 50 serves as a substrate of a chip packaging structure, and the second redistribution layer 50 is electrically connected to the first redistribution layer 20 through the first conductive pillars 23;
and the external solder balls 55 are positioned on the surface of the second re-wiring layer 50.
The chip structure 30 is an image sensor chip or a light sensor chip, and the light sensor may be one of a transmission type optical sensor, an optical measurement sensor, an optical mouse sensor, a reflection type optical sensor, and the like.
The chip structure 30 includes a front surface and a back surface, the front surface of the chip structure includes a functional region and an electrical connection region located at the periphery of the functional region, the functional region corresponds to the chip packaging window 21 of the first redistribution layer, and the electrical connection region of the chip structure is connected to the chip connection structure 22 of the first redistribution layer 20, so as to fix and electrically connect the chip structure 30 and the first redistribution layer 20.
The size of the chip package window 21 of the first redistribution layer 20 is smaller than that of the chip structure 20, and the amount of light entering can be freely adjusted by controlling the size of the chip package window 21 to adapt to different chip structures 20.
The number of the chip structures arranged on the surface of the first rewiring layer is one or more, and correspondingly, the number of the chip packaging windows is one or more.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (12)
1. A light-permeable chip packaging structure, comprising:
a transparent carrier plate;
a first redistribution layer located on the surface of the transparent carrier plate, the first redistribution layer having a chip packaging window exposing the transparent carrier plate, the first redistribution layer having a chip connection structure and a first conductive pillar formed on the surface thereof;
the chip structure is arranged on the surface of the first rewiring layer, the front surface of the chip structure penetrates through the chip packaging window to face the transparent carrier plate, and the chip structure is electrically connected with the first rewiring layer through the chip connecting structure;
the packaging material layer is positioned on the back surface of the chip structure and the surface of the first rewiring layer;
and the second rewiring layer is positioned on the surface of the packaging material layer and is used as a substrate of the chip packaging structure, and the second rewiring layer is electrically connected with the first rewiring layer through the first conductive columns.
2. The light permeable chip package structure of claim 1, wherein the chip structure is an image sensor chip or a light sensor chip.
3. The light permeable chip package structure according to claim 1, wherein the number of the chip structures is one or more, and correspondingly, the number of the chip package windows is one or more.
4. The light-permeable chip package structure according to claim 1, wherein an external solder ball is formed on the surface of the second redistribution layer.
5. The light permeable chip package structure according to claim 1, wherein the chip structure comprises a front surface and a back surface, the front surface of the chip structure comprises a functional region and an electrical connection region located at a periphery of the functional region, the functional region corresponds to the chip package window of the first redistribution layer, and the electrical connection region of the chip structure is connected to the chip connection structure of the first redistribution layer to electrically connect the chip structure to the first redistribution layer.
6. The light-permeable chip package structure according to claim 1, wherein the size of the chip package window is smaller than the size of the chip structure, and the amount of incident light is freely adjusted by controlling the size of the chip package window.
7. A method for manufacturing a light-permeable chip packaging structure is characterized by comprising the following steps:
providing a transparent carrier plate, and forming a first rewiring layer on the surface of the transparent carrier plate, wherein the first rewiring layer is provided with a chip packaging window exposing the transparent carrier plate, and a first conductive column and a chip connecting structure are formed on the surface of the first rewiring layer;
providing a chip structure, mounting the chip structure on the surface of the first rewiring layer, and electrically connecting the chip structure with the first rewiring layer through the chip connection structure, wherein the front surface of the chip structure faces the transparent carrier plate through a chip packaging window;
forming a packaging material layer on the surface of the first rewiring layer and the surface of the back face of the chip structure, and grinding the packaging material layer to expose the first conductive columns;
and forming a second re-wiring layer on the surface of the packaging material layer, wherein the second re-wiring layer is used as a substrate of the chip packaging structure, and the second re-wiring layer is electrically connected with the first re-wiring layer through the first conductive pillars.
8. The method as claimed in claim 7, further comprising forming external solder balls on the surface of the second redistribution layer.
9. The method as claimed in claim 8, wherein a wafer level package process is used to form the external solder balls and then cut the chip package structure to form a single chip package structure.
10. The method as claimed in claim 7, wherein the chip structure includes a front surface and a back surface, the front surface of the chip structure includes a functional region and an electrical connection region located at a periphery of the functional region, the functional region corresponds to the chip package window of the first redistribution layer, and the electrical connection region of the chip structure is connected to the chip connection structure of the first redistribution layer, so as to electrically connect the chip structure to the first redistribution layer.
11. The method as claimed in claim 7, wherein the size of the chip package window is smaller than the size of the chip structure when the first redistribution layer is formed, and the amount of light entering is freely adjusted by controlling the size of the chip package window.
12. The method as claimed in claim 7, wherein the number of the chip structures is one or more, and correspondingly, the number of the chip package windows is one or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210588545.3A CN115000104A (en) | 2022-05-27 | 2022-05-27 | Light-permeable chip packaging structure and manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210588545.3A CN115000104A (en) | 2022-05-27 | 2022-05-27 | Light-permeable chip packaging structure and manufacturing method |
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| CN115000104A true CN115000104A (en) | 2022-09-02 |
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| CN202210588545.3A Pending CN115000104A (en) | 2022-05-27 | 2022-05-27 | Light-permeable chip packaging structure and manufacturing method |
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| CN115881652B (en) * | 2022-12-07 | 2024-04-26 | 苏州思萃车规半导体产业技术研究所有限公司 | Chip packaging structure and manufacturing method thereof |
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