CN115881622A - Wafer bonding method - Google Patents
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- CN115881622A CN115881622A CN202310043080.8A CN202310043080A CN115881622A CN 115881622 A CN115881622 A CN 115881622A CN 202310043080 A CN202310043080 A CN 202310043080A CN 115881622 A CN115881622 A CN 115881622A
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Abstract
The invention provides a wafer bonding method, which belongs to the technical field of semiconductor manufacturing and at least comprises the following steps: providing a substrate, wherein the substrate comprises a device area and a non-device area; forming a first oxidation layer on the substrate, wherein the first oxidation layer covers the device region and extends to a part of the non-device region; forming a step on the substrate in the non-device region; forming a second oxide layer on the substrate, wherein the second oxide layer covers the first oxide layer, the surface and the side wall of the step; forming a bonding interface layer on the second oxide layer; and bonding the bonding interface layer with a bearing substrate. The wafer bonding method provided by the invention can effectively improve the bonding quality of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer bonding method.
Background
With the emergence of Silicon-On-Insulator (SOI), micro-Electro-Mechanical System (MEMS), and three-dimensional device manufacturing technologies, a new solution is provided for the integrated development of semiconductor and microelectronic technologies, and simultaneously, the wafer bonding technology becomes a key technology for the integrated development and the practicability of the microelectronic technology at present. With wafer bonding technology, two or more chips with the same or different functions can be fabricated separately and then bonded together, which provides more design freedom, improves integration, and reduces interconnections between chips, thereby reducing power consumption and delay.
However, in the wafer bonding process, a large number of bubbles or holes with different sizes are formed on the bonding interface due to the fact that particles remain on the surface or gas generated in the wafer bonding process cannot be released in time, so that the bonding quality of the wafer is reduced, and the yield and reliability of the device are affected.
Disclosure of Invention
The invention provides a wafer bonding method, which can effectively reduce bubbles on a wafer bonding interface and improve the wafer bonding quality, thereby improving the yield of devices.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a wafer bonding method, which at least comprises the following steps:
providing a substrate, wherein the substrate comprises a device region and a non-device region;
forming a first oxidation layer on the substrate, wherein the first oxidation layer covers the device region and extends to a part of the non-device region;
forming a step on the substrate in the non-device region;
forming a second oxide layer on the substrate, wherein the second oxide layer covers the first oxide layer, the surface and the side wall of the step;
forming a bonding interface layer on the second oxide layer; and
and bonding the bonding interface layer with a bearing substrate.
In an embodiment of the invention, the step of forming the second oxide layer includes:
placing the substrate with the step in a chamber;
introducing tetraethoxysilane and oxygen into the chamber; and
under the radio frequency condition, the tetraethoxysilane and the oxygen are dissociated in the chamber, and the second oxidation layer is formed on the surface of the first oxidation layer, the surface of the step and the side wall.
In an embodiment of the present invention, the step of forming the bonding interface layer includes:
subjecting the substrate including the second oxide layer to a pre-heating process; and
and forming a bonding interface layer on the second oxide layer after the preheating treatment under the radio frequency power of 100W-200W.
In an embodiment of the invention, a chemical mechanical polishing process is used to perform a first trimming process on the substrate in the non-device region to form the step.
In one embodiment of the invention, the first deburring process comprises a face grinding and edge cutting process.
In another embodiment of the present invention, an etching process is used to etch the substrate in the non-device region to form the step.
In an embodiment of the present invention, the width of the step is 1.3mm to 1.5mm.
In an embodiment of the present invention, the method further includes:
forming a third oxide layer on the second oxide layer;
annealing the substrate containing the third oxide layer; and
and carrying out secondary trimming treatment on the annealed substrate, and removing the third oxide layer and the second oxide layer with partial thickness.
In an embodiment of the invention, a total thickness of the second oxide layer and the third oxide layer is 2500nm to 2700nm.
In an embodiment of the invention, the bonding interface layer is formed by adopting a low-deposition tetraethyl orthosilicate film process, and the thickness of the bonding interface layer is 45nm-55nm.
The invention provides a wafer bonding method which can simplify the process flow, greatly reduce the process time and improve the production efficiency. And the formed film layer at the wafer bonding interface has high uniformity, good compactness and optimal bending degree, reduces the generation of bubbles in the wafer bonding process, and improves the wafer bonding quality, thereby improving the reliability and the yield of devices.
Drawings
Fig. 1 is a schematic structural diagram of a first oxide layer in an embodiment.
FIG. 2 is a schematic diagram of a first patterned photoresist layer according to an embodiment.
Fig. 3 is a schematic structural diagram of a first oxide layer in an embodiment.
FIG. 4 is a diagram illustrating a structure of a second patterned photoresist layer in an embodiment.
FIG. 5 is a schematic diagram of a step structure in an embodiment.
FIG. 6 is a schematic diagram of an embodiment of a polishing unit.
Fig. 7 is a schematic structural diagram of a second oxide layer in an embodiment.
Fig. 8 is a schematic structural diagram of a third oxide layer in an embodiment.
FIG. 9 is a schematic view illustrating a structure of polishing to a second oxide layer according to an embodiment.
FIG. 10 is a diagram illustrating the structure of a bonding interface layer according to an embodiment.
Fig. 11 is a schematic diagram of wafer bonding in an embodiment.
Fig. 12 is an electron micrograph of a device fabricated using another wafer bonding method.
Fig. 13 is an electron micrograph of a device fabricated using the wafer bonding method of the present invention.
Description of the drawings:
100. a substrate; 101. a non-device region; 102. a device region; 103. a step; 200. a first oxide layer; 201. a first oxide layer; 300. a first patterned photoresist layer; 400. a second patterned photoresist layer; 500. a second oxide layer; 600. a third oxide layer; 700. bonding an interface layer; 701. a contact surface; 800. a rotating shaft; 900. grinding the blade; 20. a carrier substrate; 21. a bonding surface.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may be more complicated.
The technical solutions of the present invention are further described in detail below with reference to several embodiments and the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In a Back side illuminated composite Metal Oxide Semiconductor (BSI CMOS), light enters from the Back side of the sensor and does not need to penetrate through an interlayer dielectric layer and an interconnection layer, namely, the light enters a photodiode in a pixel unit, and in the same unit time, light energy which can be obtained by a single pixel unit is larger, so that the picture quality is obviously improved. The back-illuminated image sensor has the characteristics of higher sensitivity, better wiring layout, improved image quality, high-speed recording permission and the like, and is widely used for digital cameras, interchangeable-lens digital cameras, smart phones and the like. The application provides a wafer bonding method, which can effectively reduce bubbles on a wafer bonding interface, improve bonding quality between wafers and improve performance of a back-illuminated image sensor.
Referring to fig. 1, in an embodiment of the invention, a substrate 100 is provided, and a wafer bonding process is illustrated by forming a device region 102 and a non-device region 101 on the substrate 100. The present invention is not limited to the kind of substrate, and different kinds of substrates can be selected according to the type of semiconductor device to be manufactured. In an embodiment of the invention, the substrate 100 may be a silicon (Si) substrate, for example, to fabricate a Complementary Metal Oxide Semiconductor (CMOS) transistor. In another embodiment, the substrate 100 may also be a gallium nitride (GaN) substrate, which is selected to be a Light-emitting Diode (LED) and a semiconductor laser. In other embodiments, the substrate 100 may be a silicon carbide (SiC) substrate, so as to manufacture a power device such as a schottky diode or an Insulated Gate Bipolar Transistor (IGBT). In an embodiment of the present invention, doping the substrate 100 may reduce the resistance of the substrate 100 and prevent latch-up. Specifically, the substrate 100 may be doped with boron (B) or gallium (Ga) to form a P-type doped substrate, or the substrate 100 may be doped with phosphorus (P) or arsenic (As) to form an N-type doped substrate. In this embodiment, boron (B) or gallium (Ga) is doped in the substrate 100 to form a P-type doped substrate.
Referring to fig. 1, in an embodiment of the present invention, devices are fabricated on a substrate 100, a device region 102 is formed, and a region where no device is fabricated is defined as a non-device region 101. The invention does not limit the specific type of the fabricated device, and in this embodiment, the fabricated device is, for example, a CMOS transistor. After devices are fabricated on the substrate 100, two or even more pieces of the substrate 100 are bonded together. Here, two or more substrates 100 on which the same device is fabricated may be bonded, or two or more substrates 100 on which different devices are fabricated may be bonded. In the present embodiment, the substrate on which the CMOS transistor is fabricated is bonded to a carrier substrate as an example.
Referring to fig. 1 and 2, in an embodiment of the invention, a first oxide material layer 200 is first formed on a substrate 100 for fabricating a CMOS transistor, wherein the first oxide material layer 200 covers the entire device region 102 and non-device region 101 and the sidewalls of the substrate 100. In an embodiment of the invention, the first oxide material layer 200 is, for example, a dense silicon oxide or the like. The method for forming the first oxide layer 200 is not limited in the present invention, and in the present embodiment, the first oxide layer 200 is formed by, for example, a High Density Plasma Chemical Vapor Deposition (HDPCVD). The thickness of the first oxide material layer 200 is, for example, 350nm to 400nm, specifically, 360nm, 380nm, 400nm, or the like.
Referring to fig. 1 to 5, in an embodiment of the invention, after the first oxide layer 200 is formed, the substrate 100 in the non-device region 101 is etched, for example, by an etching process, to form a step 103, so as to reduce the chipping defect and improve the device reliability. The step 103 may be formed in two steps, first, the first oxide layer 200 covering the edge of the substrate 100 in the non-device region 101 is etched to expose the substrate 100 at the edge, and after the etching is completed, the etching is continued to the edge of the substrate 100 to form the step 103.
Referring to fig. 2 and 3, in an embodiment of the invention, after the first oxide layer 200 is formed, a photoresist layer is spin-coated on the first oxide layer 200 by, for example, a spin-on process, and a first patterned photoresist layer 300 is formed by an exposure and development process. The first patterned photoresist layer 300 is used as a mask, for example, dry etching is performed toward the substrate 100, and the etching gas includes chlorine (Cl), for example 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Hydrogen bromide (HBr) or nitrogen (N) 2 ) And the like, and the like. After the etching is completed, the first patterned photoresist layer 140 is removed to form a first oxide layer 201. The width of the first oxide layer 201 is equal to the width of the first patterned photoresist layer 140, and the first oxide layer 201 covers the entire device region 102 and extends to a portion of the non-device region 101 at the edge of the device region 102, the width of the exposed edge of the substrate 100 is, for example, 1.3mm to 1.5mm, and the sum of the width of the first oxide layer 201 and the width of the exposed edge of the substrate 100 at two sides is equal to the width of the substrate 100. In other embodimentsIn this embodiment, the first oxide layer 201 may be formed by removing a portion of the first oxide layer 200 by using other etching methods, which may be selected according to specific manufacturing requirements.
Referring to fig. 3 to 5, in an embodiment of the invention, after the first oxide layer 201 is formed, the exposed edge of the substrate 100 is continuously etched. Specifically, for example, a photoresist layer is spin-coated on the first oxide layer 201 by a spin-on process, and a second patterned photoresist layer 400 is formed by an exposure and development process, where the second patterned photoresist layer 400 covers the entire first oxide layer 201 and exposes the non-device regions 101 on both sides of the first oxide layer 201. The second patterned photoresist layer 400 is used as a mask, and the edge of the substrate 100 is etched by, for example, a wet etching process, so as to form the step 103. Specifically, for example, concentrated sulfuric acid (H) is used 2 SO 4 ) Nitric acid (HNO) 3 ) And hydrofluoric acid (HF) to etch the substrate 100, and etching is performed at normal temperature. In the process, nitric acid oxidizes the back and the edge of the substrate 100 to form silicon dioxide, and hydrofluoric acid reacts with the silicon dioxide to generate complex hexafluorosilicic acid, so that the purpose of etching is achieved. After the etching is completed, loose porous silicon remains on the surface of the non-device region 101 of the substrate 100. And then, cleaning the substrate 100 by using deionized water with the resistivity larger than 15MQ & cm, removing porous silicon on the surface of the substrate 100 by using a potassium hydroxide (KOH) solution, and removing the acid liquor which is not washed clean and carried in the etching groove by using the deionized water. In one embodiment of the present invention, the concentration of sulfuric acid is, for example, 95% to 98%, the concentration of nitric acid is, for example, 60% to 70%, the concentration of hydrofluoric acid is, for example, 35% to 45%, and the concentration of potassium hydroxide is, for example, 45% to 55%. In an embodiment of the invention, the depth h of the step 103 is, for example, 140 μm to 160 μm, and specifically, for example, 140 μm, 150 μm, or 160 μm, and the width d of the step 103 is, for example, 1.3mm to 1.5mm, and specifically, for example, 1.3mm, 1.4mm, or 1.5mm. By setting the size of the step 103 within the above range, the device region 102 on the substrate 100 can be effectively prevented from being abnormal when a wafer bonding interface film layer is subsequently deposited.
Referring to fig. 5 and 6, in another embodiment of the present invention, after the first oxide material layer 200 is formed, a first Edge trimming process (Edge Trim) may be performed on the substrate 100 in the non-device region 101 by using, for example, a Chemical Mechanical Polishing (CMP) process. The first deburring process can be performed in two steps, such as flat grinding and edge cutting. Specifically, the entire first oxide material layer 200 is subjected to a planar grinding process using a chemical mechanical polishing process to flatten the surface of the first oxide material layer 200 and ensure that the depth of the edge cut is consistent. After the first oxide layer 200 is plane-ground, the edge of the substrate 100 is ground and cut by using the grinding unit in fig. 6. The grinding unit comprises a grinding blade 900 and a rotating shaft 800, wherein the grinding blade 900 is fixed on the rotating shaft 800, the rotating shaft 800 drives the grinding blade 900 to rotate in the vertical direction, the substrate 100 rotates in the horizontal direction, the grinding blade 900 is in contact with the edge of the substrate 100 and grinds and cuts the edge of the substrate 100, the first oxidation material layer 200 and part of the substrate 100 covering the edge of the substrate 100 are removed, and the step 103 is trimmed. The chemical mechanical polishing process is adopted to carry out trimming treatment on the substrate 100, the process flow is simple, the process time is greatly shortened, and the production efficiency is effectively improved.
Referring to fig. 5 and 7, in an embodiment of the invention, after the step 103 is formed, for example, a technique of depositing a Tetraethylorthosilicate (TEOS) film by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method is used to form a second oxide layer 500 on the surface of the first oxide layer 201 and on the surface and the sidewall of the step 103. In particular, for example, with Tetraethylorthosilicate (TEOS) and oxygen (O) 2 ) As a raw material, a second oxide layer 500 is deposited on the surface of the step 103. In an embodiment of the present invention, the tetraethoxysilane liquid is gasified at a temperature of, for example, 100 ℃ to 120 ℃, tetraethoxysilane gas is transported into the reaction chamber by using an inert gas as a carrier gas, for example, helium gas, and then oxygen gas is introduced into the reaction chamber. The tetraethoxysilane gas and the oxygen are dissociated in the chamber through radio frequency and react to generate the silicon dioxide. In an embodiment of the present invention, the flow rate of the oxygen gas can be set to 2000sccm to 3000sccm, for example, and the flow rate of the tetraethoxysilane liquid can be set toSuch as from 500mgm to 1000mgm, and a radio frequency power of, for example, from 400W to 800W. In one embodiment of the present invention, the reaction pressure in the reaction chamber is, for example, 7T to 9T, the reaction temperature is, for example, 400 ℃ to 420 ℃, and further, the reaction pressure is 8T, and the reaction temperature is 410 ℃. The second oxide layer 500 has good coverage and a large mobility of a Tetraethylorthosilicate (TEOS) surface, so that a low density region or a void can be prevented from being generated. And the second oxide layer 500 is formed through a process of plasma enhanced tetraethyl orthosilicate (PETEOS) film, the temperature of depositing the second oxide layer 500 is reduced, and the film quality of the second oxide layer 500 is ensured, thereby improving the quality of other film layers formed on the surface of the second oxide layer 500. In an embodiment of the invention, the thickness of the second oxide layer 500 is, for example, 1400nm to 1450nm, and specifically, 1420nm, 1440nm, 1450nm, or the like.
Referring to fig. 7 and 8, in an embodiment of the invention, after forming the second oxide layer 500, for example, a plasma enhanced tetraethyl orthosilicate film process is used to form a third oxide layer 600 on the surface of the second oxide layer 500. In an embodiment of the invention, the thickness of the third oxide layer 600 is, for example, 1180nm to 1220nm, specifically, 1190nm, 1200nm or 1210 nm. The second oxide layer 500 and the third oxide layer 600 are respectively formed by adopting a process of enhancing the tetraethoxysilane film by using plasma twice, so that the overall thickness and strength of the second oxide layer 500 and the third oxide layer 600 are ensured to be unchanged, the coverage uniformity of the oxide layers is improved, and the overall quality of the oxide layers is improved. In the manufactured CMOS transistor, the depth of a cutting channel between an exposure area (shot) and the exposure area is about 500nm, the total thickness of the second oxide layer 500 and the third oxide layer 600 is controlled to be 2500nm-2700nm, the cutting channel between the shot and the shot can be fully filled, and bubbles are prevented from being generated in the subsequent wafer bonding process.
Referring to fig. 7 and 8, in an embodiment of the invention, after forming the third oxide layer 600, the substrate 100 is annealed to improve the quality of the second oxide layer 500 and the third oxide layer 600 and further reduce the interface charges. In an embodiment of the present invention, the introduction of oxygen and TEOS into the chamber is stopped, nitrogen is injected into the chamber, the temperature of the substrate 100 is then maintained at 380-420 ℃, and the second oxide layer 500 and the third oxide layer 600 on the substrate 100 are annealed, so as to improve the compactness of the oxide layers and the bonding strength between the oxide layers.
Referring to fig. 6, 8 and 9, in an embodiment of the invention, after the substrate 100 is annealed, a second trimming process is performed on the second oxide layer 500 and the third oxide layer 600 on the substrate 100, for example, by using a chemical mechanical polishing process or an etching process. In an embodiment of the present invention, a second trimming process is performed on the second oxide layer 500 and the third oxide layer 600 on the substrate 100 by using the polishing unit in fig. 6, for example, to remove the third oxide layer 600 and a portion of the thickness of the second oxide layer 500. The second edging process may have a depth of 1750nm to 1850nm, specifically 1780nm, 1800nm, 1820nm, or the like, and a width of 1.3mm to 1.5mm, for example.
Referring to fig. 8 and 9, in an embodiment of the invention, after performing the second trimming process on the second oxide layer 500 and the third oxide layer 600 on the substrate 100, the substrate 100 is pre-heated. In one embodiment of the present invention, the substrate 100 is placed in the chamber, the substrate 100 is heated from room temperature to 300-400 ℃, and is processed in this temperature range for a predetermined time, such as 55-65 s. Further, in this embodiment, the temperature of the pre-heating treatment is, for example, 350 ℃, and the time of the pre-heating treatment is, for example, 60s. The substrate 100 is pre-heated, and the bending degree of the edge of the substrate 100 can reach an optimal value, so that the bonding quality of subsequent wafers can be improved, and the bubble defects can be reduced.
Referring to fig. 9 and 10, in an embodiment of the invention, after the substrate 100 is pre-heated, a bonding interface layer 700 is formed on the second oxide layer 500, for example, by a Low Deposition Tetraethylorthosilicate (LDTEOS) process. In particular, for example, with Tetraethylorthosilicate (TEOS) and oxygen (O) 2 ) As a raw material, a bonding interface layer 700 is deposited on the surface of the second oxide layer 500 by Plasma Enhanced CVD (PECVD). In one embodiment of the invention, the flow of oxygen is such asCan be set to 2000sccm to 3000sccm, the flow rate of the tetraethoxysilane liquid is, for example, 50mgm to 500mgm, and the radio frequency power is, for example, 100W to 200W. In one embodiment of the present invention, the reaction pressure in the reaction chamber is, for example, 7T to 9T, and the reaction temperature is, for example, 400 ℃ to 420 ℃, and further, the reaction pressure is 8T, and the reaction temperature is 410 ℃. By reducing the flow rate of the tetraethoxysilane and the radio frequency power, the reaction rate of the tetraethoxysilane and the oxygen can be reduced, so that the deposition rate of the bonding interface layer 700 is reduced, and a compact silicon oxide film layer with a thin thickness and uniform coverage can be deposited on the surface of the second oxide layer 500. In an embodiment of the present invention, the thickness of the bonding interface layer 700 is, for example, 45nm to 55nm, and specifically, for example, 48nm, 50nm or 52nm. In the early stage, after the oxide layer on the substrate 100 is preheated, on one hand, the distribution of plasma in the LD TEOS film process can be improved, so that the difference between the thickness of the edge and the thickness of the center of the substrate 100 in the LD TEOS film process is avoided, and the coverage uniformity of the bonding interface layer 700 is effectively improved. On the other hand, the damage of plasma in LD TEOS thin film process to the second oxide layer 500 can also be reduced, thereby improving the quality of the deposited bonding interface layer 700.
Referring to fig. 10 and 11, in an embodiment of the invention, after forming the bonding interface layer 700, the substrate 100 with the CMOS transistor fabricated thereon is turned over, so that the bonding interface layer 700 is close to the carrier substrate 20, and a low-temperature fusion bonding process is used to bond the substrate 100 and the carrier substrate 20. Specifically, the plasma activation treatment is performed on the contact surface 701 of the bonding interface layer 700 and the bonding surface 21 of the carrier substrate 20 by using a reaction gas including Ar and N 2 、O 2 And SF 6 One or more of (a). The substrate 100 and the carrier substrate 20 are bonded by contacting the contact surface 701 of the bonding interface layer 700 and the bonding surface 21 of the carrier substrate 20, wherein the bonding pressure is, for example, 1N to 10N, the bonding time is, for example, 10s to 60s, and the bonding temperature is, for example, 10 ℃ to 50 ℃. And annealing the bonded substrate 100 and the bearing substrate 20, wherein the annealing temperature is 300-400 ℃, and the annealing time is 40-80 min. After the annealing is completed, the substrate 100 is thinnedUntil the device region 102 is exposed to form a back-illuminated image sensor.
Referring to fig. 12 and 13, in an embodiment of the invention, fig. 12 is a schematic diagram of a backside illuminated image sensor manufactured by using another wafer bonding method, and fig. 13 is a schematic diagram of a backside illuminated image sensor manufactured by using a wafer bonding method according to the invention. As can be seen from fig. 12 and 13, bonding bubbles are greatly reduced in the backside illuminated image sensor manufactured by using the wafer bonding method provided by the present invention, and only a small amount of bubbles exist at the edge of the wafer, thereby ensuring the reliability of the device.
In summary, the invention provides a wafer bonding method, which reduces the number of chemical mechanical polishing, annealing and other processes, reduces the process duration and greatly improves the production efficiency by simplifying the process flow. By forming the step on the wafer, the generation of the broken edge defect in the bonding process is prevented. The bonding interface layer is covered on the step by the low-deposition ethyl orthosilicate film process, the formed bonding interface layer is high in coverage, high in uniformity and good in compactness, the bending degree of the substrate is in the optimal state, bubbles in the wafer bonding process are reduced, the wafer bonding quality is improved, and therefore the reliability and the yield of devices are improved.
The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.
Other technical features than those described in the specification are known to those skilled in the art, and are not described herein in detail in order to highlight the innovative features of the present invention.
Claims (10)
1. A method for wafer bonding, characterized by comprising at least the following steps:
providing a substrate, wherein the substrate comprises a device region and a non-device region;
forming a first oxidation layer on the substrate, wherein the first oxidation layer covers the device region and extends to a part of the non-device region;
forming a step on the substrate in the non-device region;
forming a second oxide layer on the substrate, wherein the second oxide layer covers the first oxide layer, the surface and the side wall of the step;
forming a bonding interface layer on the second oxide layer; and
and bonding the bonding interface layer with a bearing substrate.
2. The wafer bonding method as claimed in claim 1, wherein the step of forming the second oxide layer comprises:
placing the substrate with the step in a chamber;
introducing tetraethoxysilane and oxygen into the chamber; and
under the radio frequency condition, the tetraethoxysilane and the oxygen are dissociated in the chamber, and the second oxidation layer is formed on the surface of the first oxidation layer, the surface of the step and the side wall.
3. The wafer bonding method of claim 1, wherein the step of forming the bonding interface layer comprises:
subjecting the substrate including the second oxide layer to a pre-heating process; and
and forming a bonding interface layer on the second oxide layer after the preheating treatment under the radio frequency power of 100W-200W.
4. The method as claimed in claim 1, wherein a chemical mechanical polishing process is used to perform a first trimming process on the substrate in the non-device region to form the step.
5. The method of claim 4, wherein the first trimming process comprises a face grinding and edge cutting process.
6. The method of claim 1, wherein the step has a width of 1.3mm to 1.5mm.
7. The wafer bonding method of claim 1, wherein the step is formed by etching the substrate in the non-device region by an etching process.
8. The method of claim 1, further comprising:
forming a third oxide layer on the second oxide layer;
annealing the substrate containing the third oxide layer; and
and carrying out secondary trimming treatment on the annealed substrate, and removing the third oxide layer and the second oxide layer with partial thickness.
9. The method of claim 8, wherein a total thickness of the second oxide layer and the third oxide layer is 2500nm to 2700nm.
10. The wafer bonding method as claimed in claim 1, wherein the bonding interface layer is formed by a low-deposition tetraethyl orthosilicate film process, and the thickness of the bonding interface layer is 45nm-55nm.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117238743A (en) * | 2023-11-10 | 2023-12-15 | 合肥晶合集成电路股份有限公司 | Method for improving annular defect of wafer edge |
| CN117690943A (en) * | 2024-01-31 | 2024-03-12 | 合肥晶合集成电路股份有限公司 | Manufacturing method of image sensor |
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