CN116721918A - IGBT device manufacturing method and IGBT device - Google Patents

IGBT device manufacturing method and IGBT device Download PDF

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Publication number
CN116721918A
CN116721918A CN202310425489.6A CN202310425489A CN116721918A CN 116721918 A CN116721918 A CN 116721918A CN 202310425489 A CN202310425489 A CN 202310425489A CN 116721918 A CN116721918 A CN 116721918A
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silicon wafer
layer
metal
front surface
hard mask
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颜天才
钟育腾
吕昆谚
黄任生
杨列勇
陈为玉
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Wuyuan Semiconductor Technology Qingdao Co ltd
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Wuyuan Semiconductor Technology Qingdao Co ltd
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Priority to CN202310425489.6A priority Critical patent/CN116721918A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

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Abstract

The application provides a manufacturing method of an IGBT device and the IGBT device, wherein the manufacturing method comprises the following steps: providing a first silicon wafer and a second silicon wafer; manufacturing a MOSFET (IGBT front-face process) on the front face of the first silicon wafer, depositing an interlayer dielectric layer, a first metal layer and a first hard mask; and depositing a second hard mask on the front surface of the second silicon wafer, and bonding the front surface of the first silicon wafer and the front surface of the second silicon wafer. According to the manufacturing method of the IGBT device, the back surface process of the first silicon wafer is carried out after the first silicon wafer and the second silicon wafer are bonded, the first silicon wafer is not a thin sheet any more, and the IGBT device can be thinner. The thinner IGBT device can effectively solve the heat dissipation problem of the high-power device; meanwhile, the manufacturing process of the field termination FS region and the collector P-type region, which are performed on the back surface of the first silicon wafer, is higher in stability.

Description

IGBT device manufacturing method and IGBT device
Technical Field
The application belongs to the technical field of semiconductor manufacturing methods, and particularly relates to a manufacturing method of an IGBT device and the IGBT device.
Background
An Insulated Gate Bipolar Transistor (IGBT) with a Field Stop (FS) structure has low conduction loss and positive conduction voltage drop temperature coefficient, so that high-power devices can be used in parallel. The FS type IGBT is provided with an FS region, the FS region is an N type doped region and has higher doping concentration than an N-region in the IGBT, and the effect is that the electric field intensity is rapidly reduced in the layer under high voltage to realize electric field termination. The FS IGBT includes: the silicon substrate N-region, FS region, back P-type region, back metal layer and front MOSFET (metal-oxide-semiconductor field effect transistor) of the IGBT. The current method for manufacturing the FS type IGBT is generally as follows: firstly, manufacturing a MOSFET device on a silicon substrate, then removing a residual layer and a part of the silicon substrate left when manufacturing the MOSFET from the back of a silicon wafer by using a grinding method, then injecting N-type and P-type impurities from the back of the silicon wafer by using an ion implanter, and activating the injected impurities by adopting thermal annealing or laser annealing to form an FS region and a collector region (P-type region); and depositing a metal layer on the lower surface of the P-type region. The IGBT is thinner, the back of the IGBT is ground by using a special sheet machine in the existing back processing, and the ground sheet is easy to break in the subsequent process, so that the stability of the subsequent process is poor, and the yield of the product is affected.
Disclosure of Invention
In order to overcome one defect in the prior art, the application provides a manufacturing method of an IGBT device and the IGBT device.
The application adopts the technical scheme that:
a manufacturing method of an IGBT device comprises the following steps:
providing a first silicon wafer;
manufacturing a MOSFET on the front side of the first silicon wafer, and depositing an interlayer dielectric layer on the MOSFET;
forming a first metal connection part in the interlayer dielectric layer;
forming a first metal layer on the interlayer dielectric layer;
forming a first hard mask on the first metal layer;
forming a second metal connection in the first hard mask;
providing a second silicon wafer;
depositing a second hard mask on the front surface of the second silicon wafer;
forming a third metal connection in the second hard mask;
bonding the front surface of the first silicon wafer with the front surface of the second silicon wafer;
manufacturing a field termination (FS) region on the back surface of the first silicon wafer;
manufacturing a collector electrode P-type region on the back surface of the first silicon wafer;
and forming back metal on the back of the first silicon wafer.
In some embodiments of the present application, the method for manufacturing an I GBT device further includes:
carrying out chemical mechanical polishing on the back surface of the second silicon wafer;
forming a hole on the back surface of the second silicon wafer so as to expose the third metal connecting part in the second hard mask;
depositing a conductive layer on the back surface of the second silicon wafer and in the hole;
a passivation layer is formed on the conductive layer.
In some embodiments of the present application, the method for manufacturing an I GBT device further includes:
carrying out chemical mechanical polishing on the back surface of the second silicon wafer;
forming a hole on the back surface of the second silicon wafer so as to expose the third metal connecting part in the second hard mask;
forming a barrier layer along the side wall of the hole;
removing the barrier layer at the bottom of the hole to expose the third metal connection portion;
depositing a conductive layer on the back surface of the second silicon wafer and in the hole;
a passivation layer is formed on the conductive layer.
In some embodiments of the application, the second silicon wafer is back ground to a thickness of 5-600 μm.
In some embodiments of the present application, chemical mechanical polishing is performed on the back surface of the first silicon wafer before the back surface of the first silicon wafer is subjected to field stop FS region fabrication.
In some embodiments of the application, the first silicon wafer is back ground to a thickness of 5-400 μm.
In some embodiments of the application, the second silicon wafer has a thickness of 40-800 μm.
In some embodiments of the present application, the bonding of the first silicon front side and the second silicon front side includes: and aligning the second metal connecting part on the front surface of the first silicon wafer with the third metal connecting part on the front surface of the second silicon wafer for bonding.
In some embodiments of the present application, the bonding of the front surface of the first silicon wafer and the front surface of the second silicon wafer adopts an annealing process, and the annealing conditions are as follows: the temperature is below 600 ℃ for 30min to 3hrs.
Another aspect of the application provides an ibbt device comprising:
the back of the first silicon wafer is sequentially from outside to inside: the back metal, the collector P-type region and the field termination FS region, the front of the first silicon wafer is sequentially from outside to inside: an interlayer dielectric layer and a MOSFET;
a first metal layer and a first hard mask are sequentially formed on the front surface of the first silicon wafer and the interlayer dielectric layer; the interlayer dielectric layer is provided with a first metal connecting part, and the first metal connecting part is electrically connected with the first metal layer; the first hard mask is provided with a second metal connecting part, and the second metal connecting part is electrically connected with the first metal layer;
a second hard mask is formed on the front surface of the second silicon wafer, and a third metal connecting part is formed in the second hard mask; the third metal connecting part is electrically connected with the second metal connecting part;
and the front surface of the second silicon wafer is bonded with the front surface of the first silicon wafer.
In some embodiments of the present application, a hole is formed on the back surface of the second silicon wafer, and the hole exposes the third metal connection portion;
a conductive layer is formed in the hole and on the back of the second silicon wafer;
a passivation layer is formed on the conductive layer.
In some embodiments of the present application, a barrier layer is further disposed on the sidewall of the hole and between the conductive layer and the second silicon wafer.
In some embodiments of the present application, a protective layer is formed between the conductive layer and the second silicon wafer in addition to the hole.
Compared with the prior art, the application has the advantages and positive effects that: according to the manufacturing method of the I GBT device, the back surface process of the first silicon wafer is carried out after the first silicon wafer and the second silicon wafer are bonded, the first silicon wafer is not a thin sheet any more, and the I GBT device can be thinner. For example, for large-sized I GBT devices (12 inches or more), the chip thickness can be thinned to below 100 μm. Thinner GBT devices can effectively solve the heat dissipation problem of high power devices. Meanwhile, the manufacturing process of the field termination FS region and the collector P-type region, which are performed on the back surface of the first silicon wafer, is higher in stability.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating a method for fabricating an I GBT device according to an embodiment of the application, wherein an interlayer dielectric layer and a first metal layer are formed on a front surface of a first silicon wafer;
fig. 2 is a schematic cross-sectional view illustrating a step of a method for fabricating an ibbt device according to an embodiment of the present application, wherein a first hard mask is formed on a first metal layer;
fig. 3 is a schematic cross-sectional view illustrating a step of a method for fabricating an ibbt device according to an embodiment of the present application, wherein a second metal connection portion is formed in the first hard mask;
FIG. 4 is a schematic cross-sectional view illustrating a method for fabricating an I GBT device according to an embodiment of the application, wherein a second hard mask is formed on a second silicon wafer;
fig. 5 is a schematic cross-sectional view illustrating a step of a method for fabricating an ibbt device according to an embodiment of the present application, wherein the second hard mask is opened;
fig. 6 is a schematic cross-sectional view illustrating a step of a method for fabricating an ibbt device according to an embodiment of the present application, wherein a third metal connection portion is formed in the second hard mask;
FIG. 7 is a schematic cross-sectional view illustrating steps of a method for fabricating an I GBT device according to an embodiment of the application, wherein a first front side of a silicon wafer is bonded to a second front side of the silicon wafer;
FIG. 8 is a schematic cross-sectional view illustrating a method for fabricating an I GBT device according to an embodiment of the application, wherein the back side of the second silicon wafer is thinned;
FIG. 9 is a schematic cross-sectional view illustrating steps of a method for fabricating an I GBT device according to an embodiment of the application, wherein a via is formed in the back side of the second silicon wafer;
FIG. 10 is a schematic cross-sectional view illustrating steps of a method for fabricating an I GBT device according to an embodiment of the application, wherein a second conductive layer is formed on the back side of the second silicon wafer;
fig. 11 is a schematic cross-sectional view illustrating steps of a method for fabricating an ibbt device according to an embodiment of the present application, wherein a passivation layer is formed;
fig. 12 is a schematic flow chart illustrating a step of a method for fabricating an I GBT device according to another embodiment of the present application, wherein a barrier layer is formed on a sidewall of a hole;
fig. 13 is a schematic cross-sectional view illustrating steps of a method for fabricating an ibbt device according to another embodiment of the present application, wherein a conductive layer is formed;
fig. 14 is a schematic cross-sectional view illustrating steps of a method for fabricating an ibbt device according to another embodiment of the present application, wherein a passivation layer is formed;
FIG. 15 is a schematic cross-sectional view illustrating a method for fabricating an I GBT device according to an embodiment of the application, wherein a front side of a first silicon wafer is thinned;
FIG. 16 is a schematic cross-sectional view illustrating a method for fabricating an I GBT device according to an embodiment of the application, wherein N-type ions are implanted into the back surface of a first silicon wafer;
FIG. 17 is a schematic cross-sectional view illustrating a method for fabricating an I GBT device according to an embodiment of the application, wherein P-type ions are implanted into the back surface of a first silicon wafer;
fig. 18 is a schematic cross-sectional view illustrating steps of a method for fabricating an ibbt device according to an embodiment of the present application, wherein a back metal is formed;
fig. 19 is a schematic cross-sectional view showing steps of a method for fabricating an ibbt device according to another embodiment of the present application, wherein a back metal is formed;
fig. 20 is a flow chart of a method for fabricating an I GBT device according to an embodiment of the application;
fig. 21 is a flowchart illustrating steps of a method for fabricating an ibbt device according to another embodiment of the present application;
fig. 22 is a flowchart illustrating steps of a method for fabricating an ibbt device according to another embodiment of the present application.
In the figure:
100. a first silicon wafer; 101. a field termination FS region; 102. a collector P-type region; 110. a MOSFET; 120. an interlayer dielectric layer; 121. a first metal connection portion; 130. a first metal layer; 140. a first hard mask; 141. a second metal connection portion; 150. a back metal; 200. a second silicon wafer; 201. a hole; 210. a second hard mask; 211. a third metal connection; 212. a barrier layer; 220. a protective layer; 230. a conductive layer; 240. and a passivation layer.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The embodiment of the application provides a manufacturing method of an I GBT device, which comprises the following steps:
providing a first silicon wafer;
manufacturing a MOSFET on the front side of the first silicon wafer, and depositing an interlayer dielectric layer on the MOSFET;
forming a first metal connection part in the interlayer dielectric layer;
forming a first metal layer on the interlayer dielectric layer;
forming a first hard mask on the first metal layer, and forming a second metal connection part in the first hard mask;
providing a second silicon wafer;
depositing a second hard mask on the front surface of the second silicon wafer;
forming a third metal connection in the second hard mask;
bonding the front surface of the first silicon wafer with the front surface of the second silicon wafer;
manufacturing a field termination (FS) region on the back surface of the first silicon wafer;
manufacturing a collector electrode P-type region on the back surface of the first silicon wafer;
and forming back metal on the back of the first silicon wafer.
According to the manufacturing method of the I GBT device, the back surface process of the first silicon wafer is carried out after the first silicon wafer and the second silicon wafer are bonded, the first silicon wafer is not a thin sheet any more, and the I GBT device can be thinner. For example, for large-sized I GBT devices (12 inches or more), the chip thickness can be thinned to below 100 μm. Thinner GBT devices can effectively solve the heat dissipation problem of high power devices. Meanwhile, the manufacturing process of the field termination FS region and the collector P-type region, which are performed on the back surface of the first silicon wafer, is higher in stability.
Fig. 1 to 19 are schematic cross-sectional views of steps of a method for fabricating an ibbt device according to an embodiment of the present application. First, as shown in fig. 1, a first silicon wafer 100 is provided, and a MOSFET110 is fabricated on the front side of the first silicon wafer, i.e., I GBT front side process. The first silicon wafer 100 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate. The method of fabricating the MOSFET on the front side of the first silicon wafer may be a known method. For example, an interlayer dielectric layer is formed on the front surface of the first silicon wafer, and a grid groove is formed in the interlayer dielectric layer; forming a gate dielectric layer within the gate trench; forming a gate electrode on the gate dielectric layer; and then carrying out a planarization manufacturing process to remove the gate dielectric layer material and the gate electrode material on the interlayer dielectric layer. In order to adjust the threshold voltage of the MOSFET, the method of fabricating the MOSFET may further include a process including threshold voltage adjustment, such as a work function layer formation process, a channel region doping fabrication process, and the like. The method for manufacturing the MOSFET further comprises a source electrode and drain electrode epitaxial process, a grid electrode side wall oxide layer manufacturing process and the like.
Also shown in fig. 1 is an interlayer dielectric layer 120. The interlayer dielectric layer 120 is formed on the MOSFET110, for example, from a low-K dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated Silicate Glass (FSG), siOxCy, silicon carbide, silicon nitride, aluminum oxide material, etc., by any suitable method known in the art, such as spin-on coating, chemical Vapor Deposition (CVD), and Plasma Enhanced CVD (PECVD).
Next, a first metal connection portion 121 is formed in the interlayer dielectric layer 120. The first metal connection portion is formed of a metal material or a metal compound material, such as copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN), or the like. Specifically, the method for forming the first metal connection part in the interlayer dielectric layer comprises the following steps: forming a patterning mask on the interlayer dielectric layer, forming a through groove on the interlayer dielectric layer through an etching manufacturing process, depositing a first metal connecting part material in the through groove, and removing the first metal connecting part material on the surface of the interlayer dielectric layer through chemical mechanical polishing. The first metal connection part formed in the interlayer dielectric layer is electrically connected with the transistor circuit below the interlayer dielectric layer.
Also shown in fig. 1 is the formation of a first metal layer 130 on the interlayer dielectric layer 120. The first metal layer 130 is electrically connected to the first metal connection portion 121. The first metal layer is formed of a metal material or a metal compound material, such as copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN), or the like. The first metal layer may be formed by physical vapor deposition and chemical vapor deposition, or by electroplating. The first metal connection portion is made of metal or metal compound, and may be copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN), for example.
Then, referring to fig. 2 and 3, a first hard mask 140 is formed on the first metal layer 130, and a second metal connection portion 141 is formed in the first hard mask 140. The second metal connection portion 141 is electrically connected to the first metal layer 130. The first hard mask is made of silicon nitride (SiN), silicon dioxide (SiO 2 ) Silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), and the like. The method of forming the first hard mask may be a chemical vapor deposition method, such as a plasma-assisted chemical vapor deposition method or a low pressure chemical vapor deposition method. The second metal connection portion may be formed in the first hard mask in the same manner as the first metal connection portion is formed in the interlayer dielectric layer. The second metal connecting part can be made of the same material as the first metal connecting part.
As shown in fig. 4, a second silicon wafer 200 is provided. The second silicon wafer 200 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate. The second silicon wafer thickness may be 40-800 μm. Then, referring to fig. 5 and 6, a second hard mask 210 is formed on the front surface of the second silicon wafer 200, and a third metal connection portion 211 is formed in the second hard mask 210. The second hard mask is made of silicon nitride (SiN), silicon dioxide (SiO 2 ) Silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), and the like. The second hard mask may be formed by chemical vapor deposition, such as plasma-assisted chemical vapor deposition or low pressure chemical vapor deposition. The third metal connection portion may be formed in the second hard mask in the same manner as the first metal connection portion is formed in the interlayer dielectric layer. The third metal connecting portion may be made of the same material as the first metal connecting portion.
Next, referring to fig. 7, the front side of the first silicon wafer 100 is bonded to the front side of the second silicon wafer 200. Specifically, the front surface of the first silicon wafer 100 is used as one bonding surface of the first hard mask 140 located at the outermost layer; the front surface of the second silicon wafer 200, and the second hard mask 210 positioned at the outermost layer is used as another bonding surface to realize the front surface bonding of the first silicon wafer 100 and the front surface of the second silicon wafer 200. The front bonding of the first silicon wafer and the front bonding of the second silicon wafer adopt an annealing process, and the annealing conditions are as follows: the temperature is below 600 ℃ for 30min to 3hrs.
Before bonding the front surfaces of the first silicon wafer 100 and the second silicon wafer 200, the first hard mask 140 on the front surface of the first silicon wafer and the second hard mask 210 on the front surface of the second silicon wafer are subjected to chemical mechanical polishing, so that on one hand, the second metal connecting portion 141 and the third metal connecting portion 211 are exposed, and on the other hand, the flatness of the bonding surface is controlled, which is beneficial to the subsequent bonding process. And bonding the second metal connection part 141 on the front surface of the first silicon wafer 100 and the third metal connection part 211 on the front surface of the second silicon wafer 200 in alignment. The second metal connection portion 141 and the third metal connection portion 211 form a metal-metal bond therebetween and form an electrical connection. In addition, a dielectric-dielectric bond is formed between the first hard mask 140 and the second hard mask 210.
And then, carrying out a through hole process on the back surface of the second silicon wafer, and connecting the transistor circuit on the front surface of the first silicon wafer to the back surface of the second silicon wafer through the conductive material filled in the through hole. Referring to fig. 8 to 11, the second silicon wafer backside via hole forming process includes: performing chemical mechanical polishing on the back surface of the second silicon wafer 200; forming a hole 201 on the back surface of the second silicon wafer 200 to expose a third metal connection portion 211 in the second hard mask 210; depositing a conductive layer 230 on the back surface of the second silicon wafer 200 and the hole 201; a passivation layer 240 is formed on the conductive layer 230.
Referring to fig. 8, 9, and 12-14, a second silicon wafer backside via process flow is shown. First, as shown in fig. 8, chemical mechanical polishing is performed on the back surface of the second silicon wafer 200. The second silicon wafer is ground to a thickness of 5-600 μm. Then, as shown in fig. 9, a protective layer 220 is optionally deposited on the back surface of the second silicon wafer 200 to protect the second silicon wafer 200 covered by the protective layer from being etched in subsequent processes. Next, referring to fig. 9, a patterned hard mask layer is formed on the back surface of the second silicon wafer 200, and then the back surface of the second silicon wafer 200 is etched using the hard mask layer as a mask to remove the protective layer 220 which is subsequently used to form the hole 201, and then an etching gas and a protective gas are alternately introduced, and the back surface of the second silicon wafer 200 is alternately etched and the sidewall formed after the etching is protected until the hole 201 of a predetermined size is formed. Alternatively, the protective layer 220 is not deposited before the hole 201 is formed, and after the hole 201 is formed, a protective layer 220 is deposited on the back surface of the second silicon wafer 200 except for the hole. The material of the protective layer may be Si C, si N, si CN or a mixture thereof. The method for etching the holes can adopt a deep reactive ion etching process.
Then, as shown in fig. 12, a barrier layer 212 is formed on the back surface of the second silicon wafer 200 and the surface of the hole 201. The barrier layer can improve and eliminate stress around the holes and prevent structural defects caused by the stress. The material of the barrier layer may include silicon oxide, silicon nitride. In this embodiment, the method for forming the barrier layer may be a plasma-assisted chemical vapor deposition method or a low-pressure chemical vapor deposition method. In this embodiment, the barrier layer is formed on the surface of the hole, which includes both the bottom surface of the hole and the inner sidewall surface of the hole.
Next, as shown in fig. 12, the barrier layer 212 at the bottom of the hole 201 is removed to expose the third metal connection portion 211. Specifically, wet etching is performed on the back of the second silicon wafer, uniformity and roughness of the back of the second silicon wafer are improved, the second silicon wafer is further thinned until the second hard mask at the bottom of the hole is exposed, and therefore the third metal connecting portion is exposed, and the third metal connecting portion is electrically connected with a through hole formed subsequently. The etching liquid for wet etching may be, for example, a mixed liquid of KOH, HF and nitric acid, or TMAH solvent.
Referring to fig. 13, a conductive layer 230 is formed on the back surface of the second silicon wafer 200 and in the hole 201. In this embodiment, the conductive layer is made of copper. The conductive layer can be formed by physical vapor deposition and chemical vapor deposition, or by electroplating. It should be noted that, in other embodiments of the present application, the material of the conductive layer may be other metals or metal compounds, such as cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN), and the like.
After the barrier layer is formed, a planarization process can be performed on the barrier layer so as to keep certain flatness between the barrier layer and the back surface of the second silicon wafer; after the conductive layer is formed, a planarization process may be performed on the conductive layer. In this embodiment, the conductive layer and the barrier layer may be planarized by chemical mechanical polishing, which is capable of precisely and uniformly planarizing the corresponding structure to a desired thickness and flatness. For the back surface of the second silicon wafer with the protective layer formed thereon, the surface of the protective layer can be kept to have corresponding flatness through a planarization process.
As shown in fig. 14, a passivation layer 240 is formed on the conductive layer 230. Specifically, it can be formed by the steps of: and forming a patterned mask layer on the back surface of the second silicon wafer, and depositing a passivation layer on the conductive layer in the hole by taking the mask layer as a mask. And then removing the mask layer, and depositing a passivation layer on the back surface of the second silicon wafer. The material of the passivation layer can be silicon oxide, silicon carbon nitrogen.
Referring to fig. 15, in the method for manufacturing an IGBT device according to the present embodiment, chemical mechanical polishing is performed on the back surface of the first silicon wafer 100 before the field stop FS region is manufactured on the back surface of the first silicon wafer 100. The first silicon wafer is ground to a thickness of 5-400 μm. The first silicon wafer is bonded to the second silicon wafer, so that it can be thinned by chemical mechanical polishing; meanwhile, the degree of thinning the first silicon wafer by the thinning process is improved, the thinner first silicon wafer can be obtained, and finally the thinner IGBT device is obtained. In addition, the chipping phenomenon caused by the thinning process is greatly reduced. The thinning process of the first silicon wafer does not need an extra thin sheet machine, so that the manufacturing cost of the IGBT device is saved.
Next, referring to fig. 16, a field stop FS region is fabricated on the back side of the first silicon wafer 100. In this embodiment, the field stop FS region is formed by implanting N-type ions at the back side of the first silicon wafer and subsequent high temperature diffusion. N-type ions such As phosphorus (P), arsenic (As), antimony (Sb), sulfur (S) or selenium (Se) are implanted into the back surface of the first silicon wafer.
Then, referring to fig. 17, a collector P-type region is formed on the back surface of the first silicon wafer 100. And implanting the impurity required by the collector electrode into the back surface of the first silicon wafer. The back surface of the first silicon wafer is ion-implanted with the required P-type impurities of the collector, such as boron (B), boron difluoride (BF 2) and indium (I n).
Then, the low-temperature annealing causes the N-type impurity and the P-type impurity to finish diffusion. The temperature and time are adjusted to diffuse the N-type impurity to a desired thickness, and referring to fig. 18, a field stop FS region 101 and a collector P-type region 102 are formed while completing activation of the N-type impurity and the P-type impurity. The annealing temperature is 300-600 ℃ and the annealing time is 0.5-4 h.
Then, referring to fig. 18, a back side metal process is performed on the back side of the first silicon wafer 100 to form a back side metal 150. Back metal 150, i.e., back metal of aluminum (A l), titanium (T i), nickel (N i), and silver (Ag), is deposited on the back side of the first silicon wafer 100. The thickness of the final backside metal is 2000 a to 8000 a.
As shown in fig. 18 and 19, a second embodiment of the present application provides an ibbt device, comprising:
the back of the first silicon wafer 100 is sequentially from outside to inside: the back metal 150, the collector P-type region 102 and the field stop FS region 101, the front surface of the first silicon wafer is: an interlayer dielectric layer 120 and a MOSFET110;
and a second silicon wafer 200, the front surface of the second silicon wafer 200 being bonded to the front surface of the first silicon wafer 100.
In this embodiment, the back side of the first silicon wafer may be polished to a thickness of 5-400 μm. According to the I GBT device provided by the application, bonding is formed between the first silicon wafer and the second silicon wafer, and the thickness of the first silicon wafer can be thinner, so that the I GBT device can be thinner. For example, for large-sized I GBT devices (12 inches or more), the chip thickness can be thinned to below 100 μm. Thinner GBT devices can effectively solve the heat dissipation problem of high power devices. Meanwhile, the manufacturing process of the field termination FS region and the collector P-type region, which are performed on the back surface of the first silicon wafer, is higher in stability.
In this embodiment, the second silicon wafer is back ground to a thickness of 5-600 μm. The second silicon wafer may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate.
As shown in fig. 18 and 19, a first metal layer 130 and a first hard mask 140 are sequentially formed on the front surface of the first silicon wafer 100 and the interlayer dielectric layer 120; the interlayer dielectric layer 120 has a first metal connection portion 121, and the first metal connection portion 121 is electrically connected to the first metal layer 130; the first hard mask 140 has a second metal connection portion 141 therein, and the second metal connection portion 141 is electrically connected to the first metal layer 130;
a second hard mask 210 is formed on the front surface of the second silicon wafer 200, and a third metal connection part 211 is formed in the second hard mask 210; the third metal connection portion 211 is electrically connected to the second metal connection portion 141.
And bonding the front surface of the first silicon wafer and the front surface of the second silicon wafer, aligning the second metal connecting part of the front surface of the first silicon wafer with the third metal connecting part of the front surface of the second silicon wafer, and then bonding. In addition, a media-to-media bond may also be formed between the first hard mask and the second hard mask. Thus, metal-to-metal and dielectric-to-dielectric double bonds are formed on the first wafer front side and the second wafer front side.
The first hard mask and the second hard mask are made of silicon nitride (SiN), silicon dioxide (SiO 2 ) Silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), and the like. The first metal connection part, the second metal connection part and the third metal connection part are made of metal or metal compound, for example, copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta) and thallium nitride (TaN).
As shown in fig. 9, 18 and 19, a hole 201 is formed on the back surface of the second silicon wafer 200, and the hole 201 exposes the third metal connection portion 211; a conductive layer 230 is formed in the hole 201 and on the back surface of the second silicon wafer 200; a passivation layer 240 is formed on the conductive layer 230.
As shown in fig. 19, a barrier layer 212 is further disposed on the sidewall of the hole 201 between the conductive layer 230 and the second silicon wafer 200. The barrier layer can improve and eliminate stress around the holes and reduce structural defects caused by the stress.
As shown in fig. 18 and 19, a protective layer 220 is formed between the conductive layer 230 and the second silicon wafer 200 in addition to the hole 201. A protective layer 220 is deposited on the back side of the second silicon wafer 200 to protect the second silicon wafer 200 that it covers from being etched during the IGBT fabrication process.
Fig. 20 is a schematic flow chart of steps of a method for fabricating an IGBT device according to an embodiment of the present application. The method comprises the following steps:
providing a first silicon wafer, manufacturing a MOSFET on the front side of the first silicon wafer, and depositing an interlayer dielectric layer on the MOSFET; forming a first metal connection part in the interlayer dielectric layer; forming a first metal layer on the interlayer dielectric layer;
forming a first hard mask on the first metal layer, and forming a second metal connection part in the first hard mask;
providing a second silicon wafer; depositing a second hard mask on the front surface of the second silicon wafer;
forming a third metal connection in the second hard mask;
carrying out chemical mechanical polishing on the front surface of the first silicon wafer;
chemical mechanical polishing the front surface of the second silicon wafer
Bonding the front surface of the first silicon wafer with the front surface of the second silicon wafer;
carrying out chemical mechanical polishing on the back surface of the second silicon wafer;
forming a hole on the back of the second silicon wafer;
depositing a conductive layer on the back of the second silicon wafer;
carrying out chemical mechanical polishing on the conductive layer;
depositing a passivation layer on the conductive layer;
carrying out chemical mechanical polishing on the back surface of the first silicon wafer;
injecting N-type ions required by the field termination FS region and P-type ions required by the collector P-type region into the back surface of the first silicon wafer; then annealing to form a field termination FS region and a collector P-type region;
and performing a back metal process on the back of the first silicon wafer.
Fig. 21 is a schematic flow chart of steps of a method for fabricating an ibbt device according to another embodiment of the present application. The method comprises the following steps:
providing a first silicon wafer, manufacturing a MOSFET on the front side of the first silicon wafer, and depositing an interlayer dielectric layer on the MOSFET; forming a first metal connection part in the interlayer dielectric layer; forming a first metal layer on the interlayer dielectric layer;
forming a first hard mask on the first metal layer, and forming a second metal connection part in the first hard mask;
providing a second silicon wafer; depositing a second hard mask on the front surface of the second silicon wafer;
forming a third metal connection in the second hard mask;
carrying out chemical mechanical polishing on the front surface of the first silicon wafer;
chemical mechanical polishing the front surface of the second silicon wafer
Bonding the front surface of the first silicon wafer with the front surface of the second silicon wafer;
carrying out chemical mechanical polishing on the back surface of the first silicon wafer;
injecting N-type ions required by the field termination FS region and P-type ions required by the collector P-type region into the back surface of the first silicon wafer; then annealing to form a field termination FS region and a collector P-type region;
performing a back metal process on the back of the first silicon wafer;
carrying out chemical mechanical polishing on the back surface of the second silicon wafer;
forming a hole on the back of the second silicon wafer;
depositing a conductive layer on the back of the second silicon wafer;
carrying out chemical mechanical polishing on the conductive layer;
a passivation layer is deposited over the conductive layer.
Fig. 22 is a schematic flow chart of steps of a method for fabricating an ibbt device according to another embodiment of the present application. The method comprises the following steps:
providing a first silicon wafer, manufacturing a MOSFET on the front side of the first silicon wafer, and depositing an interlayer dielectric layer on the MOSFET; forming a first metal connection part in the interlayer dielectric layer; forming a first metal layer on the interlayer dielectric layer;
forming a first hard mask on the first metal layer, and forming a second metal connection part in the first hard mask;
providing a second silicon wafer; depositing a second hard mask on the front surface of the second silicon wafer;
forming a third metal connection in the second hard mask;
carrying out chemical mechanical polishing on the front surface of the first silicon wafer;
chemical mechanical polishing the front surface of the second silicon wafer
Bonding the front surface of the first silicon wafer with the front surface of the second silicon wafer;
carrying out chemical mechanical polishing on the back surface of the first silicon wafer;
injecting N-type ions required by the field termination FS region and P-type ions required by the collector P-type region into the back surface of the first silicon wafer; then annealing to form a field termination FS region and a collector P-type region;
carrying out chemical mechanical polishing on the back surface of the second silicon wafer;
forming a hole on the back of the second silicon wafer;
depositing a conductive layer on the back of the second silicon wafer;
carrying out chemical mechanical polishing on the conductive layer;
depositing a passivation layer on the conductive layer;
and performing a back metal process on the back of the first silicon wafer.

Claims (13)

1. The manufacturing method of the IGBT device is characterized by comprising the following steps of:
providing a first silicon wafer;
manufacturing a MOSFET on the front side of the first silicon wafer, and depositing an interlayer dielectric layer on the MOSFET;
forming a first metal connection part in the interlayer dielectric layer;
forming a first metal layer on the interlayer dielectric layer;
forming a first hard mask on the first metal layer;
forming a second metal connection in the first hard mask;
providing a second silicon wafer;
depositing a second hard mask on the front surface of the second silicon wafer;
forming a third metal connection in the second hard mask;
bonding the front surface of the first silicon wafer with the front surface of the second silicon wafer;
manufacturing a field termination (FS) region on the back surface of the first silicon wafer;
manufacturing a collector electrode P-type region on the back surface of the first silicon wafer;
and forming back metal on the back of the first silicon wafer.
2. The method for fabricating the IGBT device of claim 1, further comprising:
carrying out chemical mechanical polishing on the back surface of the second silicon wafer;
forming a hole on the back surface of the second silicon wafer so as to expose the third metal connecting part in the second hard mask;
depositing a conductive layer on the back surface of the second silicon wafer and in the hole;
a passivation layer is formed on the conductive layer.
3. The method for fabricating the IGBT device of claim 1, further comprising:
carrying out chemical mechanical polishing on the back surface of the second silicon wafer;
forming a hole on the back surface of the second silicon wafer so as to expose the third metal connecting part in the second hard mask;
forming a barrier layer along the side wall of the hole;
removing the barrier layer at the bottom of the hole to expose the third metal connection portion;
depositing a conductive layer on the back surface of the second silicon wafer and in the hole;
a passivation layer is formed on the conductive layer.
4. The method for fabricating an IGBT device according to claim 2 or 3, wherein the second silicon wafer is back ground to a thickness of 5 to 600 μm.
5. The method of fabricating an IGBT device of claim 1 wherein the first silicon wafer backside is subjected to chemical mechanical polishing before the first silicon wafer backside is subjected to the field stop FS region.
6. The method for fabricating the IGBT device of claim 5 wherein the first silicon wafer is back ground to a thickness of 5 to 400 μm.
7. The method for fabricating the IGBT device of claim 1 wherein the second silicon wafer has a thickness of 40-800 μm.
8. The method for fabricating the IGBT device of claim 1 wherein the bonding the first silicon front surface and the second silicon front surface comprises: and aligning the second metal connecting part on the front surface of the first silicon wafer with the third metal connecting part on the front surface of the second silicon wafer for bonding.
9. The method for manufacturing the IGBT device according to claim 1, wherein the bonding of the front surface of the first silicon wafer and the front surface of the second silicon wafer adopts an annealing process, and the annealing conditions are: the temperature is below 600 ℃ for 30min to 3hrs.
10. An IGBT device, comprising:
the back of the first silicon wafer is sequentially from outside to inside: the back metal, the collector P-type region and the field termination FS region, the front of the first silicon wafer is sequentially from outside to inside: an interlayer dielectric layer and a MOSFET;
a first metal layer and a first hard mask are sequentially formed on the front surface of the first silicon wafer and the interlayer dielectric layer; the interlayer dielectric layer is provided with a first metal connecting part, and the first metal connecting part is electrically connected with the first metal layer; the first hard mask is provided with a second metal connecting part, and the second metal connecting part is electrically connected with the first metal layer;
a second hard mask is formed on the front surface of the second silicon wafer, and a third metal connecting part is formed in the second hard mask; the third metal connecting part is electrically connected with the second metal connecting part;
and the front surface of the second silicon wafer is bonded with the front surface of the first silicon wafer.
11. The IGBT device of claim 10 wherein:
a hole is formed in the back surface of the second silicon wafer, and the hole exposes the third metal connecting part; a conductive layer is formed in the hole and on the back of the second silicon wafer;
a passivation layer is formed on the conductive layer.
12. The IGBT device of claim 11 wherein:
and a blocking layer is arranged on the side wall of the hole and positioned between the conducting layer and the second silicon chip.
13. The IGBT device of claim 11 or 12, wherein:
and a protective layer is formed between the conductive layer and the second silicon wafer outside the hole.
CN202310425489.6A 2023-04-19 2023-04-19 IGBT device manufacturing method and IGBT device Pending CN116721918A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310425489.6A CN116721918A (en) 2023-04-19 2023-04-19 IGBT device manufacturing method and IGBT device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310425489.6A CN116721918A (en) 2023-04-19 2023-04-19 IGBT device manufacturing method and IGBT device

Publications (1)

Publication Number Publication Date
CN116721918A true CN116721918A (en) 2023-09-08

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