CN116631872A - Manufacturing method of trench gate power device and trench gate power device - Google Patents

Manufacturing method of trench gate power device and trench gate power device Download PDF

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Publication number
CN116631872A
CN116631872A CN202310716074.4A CN202310716074A CN116631872A CN 116631872 A CN116631872 A CN 116631872A CN 202310716074 A CN202310716074 A CN 202310716074A CN 116631872 A CN116631872 A CN 116631872A
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China
Prior art keywords
hole
forming
substrate
trench gate
power device
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Inventor
任世强
颜天才
吕昆谚
黄任生
杨列勇
陈为玉
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Wuyuan Semiconductor Technology Qingdao Co ltd
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Wuyuan Semiconductor Technology Qingdao Co ltd
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Priority to CN202310716074.4A priority Critical patent/CN116631872A/en
Publication of CN116631872A publication Critical patent/CN116631872A/en
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The application provides a manufacturing method of a trench gate power device and the trench gate power device, wherein the method comprises the following steps: and forming a second through hole on the front surface of the substrate, wherein the second through hole extends to the drain region on the back surface of the substrate, so that the drain electrode is introduced into the front surface of the substrate, and therefore, the substrate thinning and back surface metal process is omitted. On one hand, the thickness of the substrate can be thinner, so that the substrate resistance is reduced, and a trench gate power device with lower on-resistance is obtained; on the other hand, the back thinning process and the back metal process are omitted, so that the process is more compatible with the traditional logic process, the problems of broken pieces and the like generated by the back thinning process are avoided, and the product yield is improved. Meanwhile, the back thinning process is omitted, a sheet machine is not needed any more, and the production cost can be saved.

Description

Manufacturing method of trench gate power device and trench gate power device
Technical Field
The application belongs to the technical field of semiconductor manufacturing methods, and particularly relates to a manufacturing method of a trench gate power device and the trench gate power device.
Background
The trench power MOS device has the characteristics of high integration level, low on-resistance, high switching speed and small switching loss, and is widely applied to various power management and switching conversion. With the development of industry, the global warming causes the climate environment to be worse and worse, and the countries begin to pay more attention to energy conservation, carbon reduction and sustainable development, so that the requirements on the power consumption and the conversion efficiency of the power MOS device are higher and higher, and under the condition of low application frequency, the power consumption is mainly determined by the conduction loss, and the conduction loss is mainly influenced by the magnitude of the characteristic on-resistance; wherein, the smaller the characteristic on-resistance, the smaller the on-loss.
The on-resistance includes: channel resistance, diffusion resistance, resistance of the drift region, and substrate resistance. The resistance of the substrate depends on the thickness of the substrate. In the conventional trench gate power device, a source region and a gate region are formed on the front surface of a substrate, and a drain region is formed on the back surface of the substrate. The substrate is heavily doped, and the drain region directly consists of the thinned substrate; or the drain region is formed by carrying out back heavy doping drain injection on the thinned substrate, and then carrying out a back metal process. If the substrate is too thin, the problems of broken pieces and the like are easily caused by a thinning process and a back metal process. Therefore, the thickness of the substrate is limited, and the substrate resistance cannot be reduced due to the influence of the thickness of the substrate, limiting the reduction of the on-resistance.
Disclosure of Invention
In order to overcome one defect in the prior art, the application provides a manufacturing method of a trench gate power device and the trench gate power device.
The application adopts the technical scheme that:
the manufacturing method of the trench gate power device comprises the following steps:
providing a substrate;
forming an epitaxial layer on the front surface of the substrate;
forming groove gates in the epitaxial layer, and forming a channel region between the groove gates;
forming a source region on the surface of the channel region;
forming a drain region on the back surface of the substrate;
forming an interlayer dielectric layer on the epitaxial layer, wherein the interlayer dielectric layer covers the source region and the trench gate;
forming a first through hole penetrating through the interlayer dielectric layer in the interlayer dielectric layer, and filling the first through hole with a conductive material to form a first metal guide hole connecting the source region and the trench gate;
forming a first conductive layer on the interlayer dielectric layer, and patterning the first conductive layer to form a grid electrode and a source electrode, wherein the source electrode and the grid electrode are electrically connected with the first metal guide hole;
forming a first hard mask on the first conductive layer;
forming a second through hole in the interlayer dielectric layer and the first hard mask, wherein the second through hole penetrates through the epitaxial layer;
filling the second via with a conductive material, thereby forming a second metal via connecting the drain region;
depositing a second conductive layer over the second metal via, patterning the second conductive layer to form a drain, the drain electrically connected to the second metal via;
depositing a second hard mask over the second conductive layer;
the first hard mask and the second hard mask are patterned to expose the source electrode, the gate electrode, and the drain electrode.
In some embodiments of the application, the second via diameter is above 10 μm.
In some embodiments of the application, the second via has a depth of 3-150 μm.
In some embodiments of the application, after filling the second via with the conductive material, the conductive material is removed from areas other than the second via.
In some embodiments of the present application, the second via-filled conductive material may be at least one selected from Cu, co, al, W, ti, tiN, ta, taN.
The application also provides a manufacturing method of the trench gate power device, which comprises the following steps:
providing a substrate;
forming an epitaxial layer on the front surface of the substrate;
forming groove gates in the epitaxial layer, and forming a channel region between the groove gates;
forming a source region on the surface of the channel region;
forming a drain region on the back surface of the substrate;
forming an interlayer dielectric layer on the epitaxial layer;
forming a first through hole and a second through hole in the interlayer dielectric layer, wherein the first through hole penetrates through the interlayer dielectric layer, and the second through hole penetrates through the epitaxial layer;
filling the first via and the second via with a conductive material such that the first via forms a first metal via connecting the source region and the trench gate and the second via forms a second metal via connecting the drain region;
depositing a conductive layer over the first metal via and the second metal via;
patterning the conductive layer over the first metal via to form a gate and a source, and patterning the conductive layer over the second metal via to form a drain;
depositing a hard mask on the conductive layer;
the hard mask is patterned to expose the source, the gate, and the drain.
In some embodiments of the application, the second via diameter is above 10 μm.
In some embodiments of the application, the second via has a depth of 3-150 μm.
In some embodiments of the present application, after the first and second vias are filled with the conductive material, the conductive material is removed from areas other than the first and second vias.
Another aspect of the present application provides a channel power device, comprising:
a substrate;
an epitaxial layer over the substrate;
a trench gate is formed in the epitaxial layer;
a channel region located between each of the trench gates;
the source region is positioned on the surface of the channel region;
an interlayer dielectric layer and a hard mask are arranged on the epitaxial layer; the interlayer dielectric layer is provided with a first through hole and a second through hole, the first through hole penetrates through the interlayer dielectric layer, and the second through hole penetrates through the epitaxial layer; the first through hole and the second through hole are filled with conductive materials;
a gate electrode and a source electrode patterned from a conductive layer formed over the first via hole;
and a drain electrode patterned by the conductive layer formed on the second via hole.
Compared with the prior art, the application has the advantages and positive effects that: according to the manufacturing method of the trench gate power device, the drain electrode is led into the front surface of the substrate through the second through hole, so that the substrate thinning and back metal process are omitted, the thickness of the substrate can be thinner on one hand, the back thinning process and the back metal process are omitted on the other hand, the substrate resistance is further reduced, and the trench gate power device with lower on-resistance is obtained.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating steps of a method for fabricating a trench-gate power device according to an embodiment of the application, wherein a source and a gate are formed on a front surface of a substrate;
FIG. 2 is a schematic cross-sectional view illustrating a method for fabricating a trench-gate power device according to an embodiment of the application, wherein a first hard mask and an interlayer dielectric layer are opened to form a second via;
fig. 3 is a schematic cross-sectional view illustrating a step of a method for fabricating a trench-gate power device according to an embodiment of the application, in which a second via penetrates through an epitaxial layer;
fig. 4 is a schematic cross-sectional view illustrating a step of a method for fabricating a trench-gate power device according to an embodiment of the application, in which a conductive material fills a second via;
fig. 5 is a schematic cross-sectional view illustrating steps of a method for fabricating a trench-gate power device according to an embodiment of the application, in which a drain is formed;
FIG. 6 is a schematic cross-sectional view illustrating steps of a method for fabricating a trench-gate power device according to an embodiment of the application, wherein a second hard mask is formed;
FIG. 7 is a schematic cross-sectional view illustrating steps of a method for fabricating a trench-gate power device according to an embodiment of the application, wherein a first hard mask and a second hard mask are opened;
fig. 8 is a schematic cross-sectional view illustrating a step of a method for fabricating a trench-gate power device according to another embodiment of the present application, in which an interlayer dielectric layer 120 is formed;
FIG. 9 is a schematic cross-sectional view illustrating steps of a method for fabricating a trench-gate power device according to an embodiment of the application, wherein an interlayer dielectric layer is opened;
fig. 10 is a schematic cross-sectional view illustrating steps of a method for fabricating a trench-gate power device according to an embodiment of the application, in which a second via is formed;
fig. 11 is a schematic cross-sectional view illustrating steps of a method for fabricating a trench-gate power device according to an embodiment of the application, in which the first via and the second via are filled with a conductive material;
FIG. 12 is a schematic flow chart showing steps of a method for fabricating a trench-gate power device according to another embodiment of the present application, wherein a gate electrode, a source electrode and a drain electrode are formed;
fig. 13 is a schematic cross-sectional view illustrating steps of a method for fabricating a trench-gate power device according to another embodiment of the present application, wherein a hard mask is opened to perform a passivation process;
fig. 14 is a flowchart illustrating a method for fabricating a trench gate power device according to an embodiment of the application;
fig. 15 is a flowchart illustrating a method for manufacturing a trench gate power device according to another embodiment of the present application;
in the figure:
100. a substrate; 110. an epitaxial layer; 120. an interlayer dielectric layer; 121. a first through hole; 122. a first metal via; 130. a first conductive layer; 131. a source electrode; 140. a first hard mask; 141. a second through hole; 142. a second metal via; 150. a second conductive layer; 151. a drain electrode; 160. a second hard mask; 161. a third through hole; 200. a trench gate; 300. a channel region; 310. a source region; 400. and a drain region.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The embodiment of the application provides a manufacturing method of a trench gate power device, which comprises the following steps:
providing a substrate 100;
forming an epitaxial layer 110 on the front surface of the substrate 100;
forming trench gates 200 in the epitaxial layer 110, and forming channel regions 300 between the respective trench gates;
forming a source region 310 on the surface of the channel region 300;
forming a drain region 400 on the back surface of the substrate 100;
forming an interlayer dielectric layer 120 on the epitaxial layer 110, the interlayer dielectric layer 120 covering the source region 300 and the trench gate 200;
forming a first via in the interlayer dielectric layer 120 through the interlayer dielectric layer 120, filling the first via with a conductive material to form a first metal via 121 connecting the source region 310 and the trench gate 200;
forming a first conductive layer 130 on the interlayer dielectric layer, patterning the first conductive layer 130 to form a gate electrode (not shown) and a source electrode 131, the source electrode 131 and the gate electrode being electrically connected to the first metal via 121;
forming a first hard mask 140 on the first conductive layer 130;
forming a second via 141 in the interlayer dielectric layer 120 and the first hard mask 140, the second via 141 penetrating through the epitaxial layer 110;
filling the second via with a conductive material, thereby forming a second metal via 142 connecting the drain region;
depositing a second conductive layer 150 over the second metal via 142, patterning the second conductive layer 150 to form a drain 151, the drain 151 being electrically connected to the second metal via 142;
depositing a second hard mask 160 on the second conductive layer 150;
the first hard mask 140 and the second hard mask 160 are patterned to expose the source electrode 131, the gate electrode and the drain electrode 151.
In the trench gate type power device, a source region and a channel region are formed on the front surface of a substrate, and a drain region is formed on the back surface of the substrate, which is determined by the channel ion flow direction of the channel region. According to the manufacturing method of the trench gate power device, the second through hole is formed in the front surface of the substrate to introduce the drain electrode into the front surface of the substrate, so that the substrate thinning and back metal processes are omitted, on one hand, the thickness of the substrate can be thinner, and further the substrate resistance is reduced, and the trench gate power device with lower on-resistance is obtained; on the other hand, the back thinning process and the back metal process are omitted, so that the process is more compatible with the traditional logic process, the problems of broken pieces and the like generated by the back thinning process are avoided, and the product yield is improved. Meanwhile, the back thinning process is omitted, a sheet machine is not needed any more, and the production cost can be saved. For example, in addition, a thinner trench gate power device can effectively solve the heat dissipation problem of a high power device.
Fig. 1 to 7 are schematic cross-sectional views of steps of a method for fabricating a trench gate power device according to an exemplary embodiment of the application. In the present exemplary embodiment, the trench gate power device is a trench gate MOSFET. Of course, the trench gate power device may also be a trench gate IGBT. The application is not limited to the type of trench gate power device. First, as shown in fig. 1, a substrate 100 is provided, and a MOSFET is fabricated on the front side of the substrate, i.e., a front side process. The substrate 100 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator substrate. The method of fabricating the MOSFET on the front side of the substrate may be a known method. For example, an epitaxial layer 110 is formed on the front surface of the substrate, and a trench gate 200 is formed in the epitaxial layer 110; trench gate 200 includes a gate dielectric layer; depositing a gate conductive material layer over the gate dielectric layer; and then carrying out a planarization manufacturing process to remove the gate dielectric layer material and the gate conductive material on the epitaxial layer. Taking an N-type device as an example, the N-type heavily doped drain on the back of the substrate is implanted. The epitaxial layer has an N-type light doping. The channel region is P-type doped. The source region is heavily doped with N type. The drift region is formed by an epitaxial layer on the surface of the semiconductor substrate from the drain region to the channel region.
Also shown in fig. 1 is an interlayer dielectric layer 120. The interlayer dielectric layer 120 is formed on the MOSFET, for example, from a low-K dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated Silicate Glass (FSG), siOxCy, silicon carbide, silicon nitride, aluminum oxide material, etc., by any suitable method known in the art, such as spin-on coating, chemical Vapor Deposition (CVD), and Plasma Enhanced CVD (PECVD).
Next, a first via 121 penetrating the interlayer dielectric layer 120 is formed in the interlayer dielectric layer 120. The first via 121 is filled with a conductive material to form a first metal via 122. The conductive material is selected from a metal material or a metal compound material, for example, copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN), or the like. Specifically, the method for forming the first metal via 122 in the interlayer dielectric layer 10 is as follows: a patterning mask is formed on the interlayer dielectric layer, then a first through hole is formed on the interlayer dielectric layer through an etching manufacturing process, then a conductive material is deposited in the first through hole, and then chemical mechanical polishing is performed to remove the conductive material on the surface of the interlayer dielectric layer. The first metal via formed in the interlayer dielectric layer is electrically connected to the transistor circuit under the interlayer dielectric layer.
Also shown in fig. 1 is the formation of a first conductive layer 130 on the interlayer dielectric layer 120. The patterned first conductive layer 130 forms a gate (not shown, the gate is formed of the same layer of conductive layer as the source, but the conductive layer forming the gate is located in a different position on the same layer as the conductive layer forming the source, and is just not visible in the cross-sectional position of fig. 1) and a source 131. The gate and source 131 are electrically connected to the first metal via 122. The first conductive layer 130 is formed of a metal material or a metal compound material, for example, copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN), or the like. The first conductive layer may be formed by physical vapor deposition or chemical vapor deposition, or by electroplating.
Then, referring to fig. 1, 2 and 3, a first hard mask 140 is formed on the first conductive layer 130, and then the first hard mask is opened in the first hard mask 140 by etching to form a first portion of the second via 141, and then the second via 141 is penetrated through the epitaxial layer 110 by a through-silicon via process. Referring to fig. 4, the second via 141 is filled with a conductive material, thereby forming a second metal via 142 connecting the drain region. The first hard mask is formed of a material such as silicon nitride (SiN), silicon dioxide (SiO 2), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), or the like. The method of forming the first hard mask may be a chemical vapor deposition method, such as a plasma-assisted chemical vapor deposition method or a low pressure chemical vapor deposition method. The conductive material deposited in the second via may be the same material as the conductive material deposited in the first via. After filling the second via with the conductive material, the conductive material is removed from the area outside the second via. The conductive material in the area except the second through hole is removed by etching or chemical mechanical polishing. The diameter of the second through hole is more than 10 mu m. The depth of the second through hole is 3-150 μm.
Next, referring to fig. 5, a second conductive layer 150 is deposited over the second metal via 142, the second conductive layer 150 is patterned to form a drain 151, and the drain 151 is electrically connected to the second metal via 142. The second metal via 142 introduces a drain region on the back side of the substrate 100 into the front side of the substrate, thus transferring the metal process on the back side of the substrate to the front side of the substrate without performing a thinning process on the back side of the substrate. The second conductive layer may be formed by physical vapor deposition or chemical vapor deposition, or by electroplating.
And finally, opening the hard mask by dry etching to complete the passivation process. Referring to fig. 6, a second hard mask 160 is formed on the second conductive layer 150. Referring to fig. 7, the first hard mask 140 and the second hard mask 160 are patterned to form a third via hole 161, and the third via hole 161 exposes the source electrode 131, the gate electrode and the drain electrode 151. The second hard mask is formed of a material such as silicon nitride (SiN), silicon dioxide (SiO 2), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), or the like. The second hard mask may be formed by chemical vapor deposition, such as plasma-assisted chemical vapor deposition or low pressure chemical vapor deposition. A passivation layer 240 is then deposited in the third via. The material of the passivation layer can be silicon oxide, silicon carbon nitrogen.
A barrier layer is further formed on the sidewalls of the second via 141 (excluding the bottom of the second via 141) between the conductive material and the epitaxial layer, the substrate. The barrier layer can improve and eliminate the stress around the second through hole and reduce the structural defect caused by the stress. The barrier layer is formed by chemical vapor deposition or atomic layer deposition and includes at least one layer, each layer having a thickness of about 50-2000 angstroms.
The steps of forming the first metal via and the second metal via may be fused, and referring to fig. 8-14, another exemplary embodiment of the present application provides a method for manufacturing a trench gate power device, including:
providing a substrate 100;
forming an epitaxial layer 110 on the front surface of the substrate;
forming trench gates 200 in the epitaxial layer, and forming channel regions 300 between the respective trench gates 200;
forming a source region 310 on the channel region surface;
forming a drain region 400 on the back surface of the substrate;
forming an interlayer dielectric layer 120 on the epitaxial layer 110;
forming a first through hole 121 and a second through hole 141 in the interlayer dielectric layer 120, wherein the first through hole 121 penetrates through the interlayer dielectric layer, and the second through hole penetrates through the epitaxial layer 110;
filling the first and second via holes 121 and 141 with a conductive material such that the first via hole 121 forms a first metal via hole 122 connecting the source region 310 and the trench gate 200 and the second via hole 141 forms a second metal via hole 142 connecting the drain region 400;
depositing a conductive layer (130, 150) over the first metal via 122 and the second metal via 142;
patterning the conductive layer 130 over the first metal via 122 to form a gate (not shown) and a source 131, and patterning the conductive layer 150 over the second metal via 142 to form a drain 151;
depositing a hard mask 160 over the conductive layer (130, 150);
the hard mask 160 is patterned to expose the source electrode 131, the gate electrode (not shown), and the drain electrode 151.
Referring to fig. 8, a substrate 100 is provided, and a front side process is performed; forming an epitaxial layer 110 on the front surface of the substrate 100; forming trench gates 200 in the epitaxial layer, and forming channel regions 300 between the respective trench gates 200; forming a source region 310 on the channel region surface; forming a drain region 400 on the back surface of the substrate; an interlayer dielectric layer 120 is sequentially formed on the epitaxial layer 110.
Then, referring to fig. 9 and 10, a first via hole 121 and a second via hole 141 are formed in the interlayer dielectric layer, the first via hole 121 penetrating the interlayer dielectric layer. First, the interlayer dielectric layer 120 is opened by an etching method to form a first portion of the second via 141, and then the second via 141 penetrates through the epitaxial layer 110 by a through-silicon via process.
Referring to fig. 11, the first and second via holes 121 and 141 are filled with a conductive material such that the first via hole 121 forms the first metal via hole 122 connecting the source region 310 and the trench gate 200 and the second via hole 141 forms the second metal via hole 142 connecting the drain region 400.
Referring to fig. 12, a conductive layer (130, 150) is deposited over the first metal via 122 and the second metal via 142; patterning the conductive layer (130, 150) to form a gate and source 131 over the first metal via 122 and a drain 151 over the second metal via 142; a hard mask 160 is deposited over the conductive layer (130, 150).
And finally, opening the hard mask by dry etching to complete the passivation process. Referring to fig. 13, the hard mask 160 is patterned to expose the source electrode 131, the gate electrode (not shown), and the drain electrode 151.
In some of these embodiments, after the first and second through holes 121 and 141 are filled with the conductive material, the conductive material of the areas other than the first and second through holes 121 and 141 is removed.
In some of these embodiments, the second via 141 is above 10 μm in diameter.
In some of these embodiments, the depth of the second via 141 is 3-150 μm.
As shown in fig. 7 and 13, a second embodiment of the present application provides a trench gate power device, including:
a substrate 100;
an epitaxial layer 110 over the substrate 100; the epitaxial layer 110 has a trench gate 200 formed therein;
a channel region 300 located between the respective trench gates 200;
a source region 310 located on the surface of the channel region 300;
an interlayer dielectric layer 120 and a hard mask 160 are sequentially arranged on the epitaxial layer 110; the interlayer dielectric layer 120 has a first through hole 121 and a second through hole 141, the first through hole 121 penetrates through the interlayer dielectric layer 120, and the second through hole 141 penetrates through the epitaxial layer 110; the first through hole 121 and the second through hole 141 are filled with a conductive material;
a gate electrode (not shown) and a source electrode 131 patterned from a conductive layer 130 formed over the first via hole 121;
a drain electrode 151 patterned from the conductive layer 150 formed over the second via hole 141;
in this embodiment, the second via diameter is 10 μm or more. The depth of the second through hole is 3-150 μm. According to the trench gate power device provided by the application, the drain region positioned at the back of the substrate is introduced to the front of the substrate through the second through hole, so that the metal process of the back of the substrate can be fused with the metal process of the front of the substrate, and the back thinning process is not required.
The hard mask is formed of a material such as silicon nitride (SiN), silicon dioxide (SiO 2), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), or the like. The conductive material filled in the first through hole and the second through hole is metal or metal compound, and can be copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta) or thallium nitride (TaN), for example.
Fig. 14 is a schematic flow chart of steps of a method for fabricating a trench gate power device according to an embodiment of the present application. The method comprises the following steps:
providing a substrate;
completing a metal deposition process of the trench gate power MOS device on the front surface of the substrate;
depositing a first hard mask;
opening the first hard mask and the interlayer dielectric layer through an etching process;
forming a second through hole through a through silicon via process;
depositing a barrier layer and a conductive material in the second via;
removing the conductive material except the second through hole through chemical mechanical polishing;
depositing a conductive layer and patterning the conductive layer;
and (5) passivation process.
Fig. 15 is a schematic flowchart illustrating a method for manufacturing a trench gate power device according to another embodiment of the present application. The method comprises the following steps:
providing a substrate;
finishing a deposition process of an interlayer dielectric layer of the trench gate power MOS device on the front surface of the substrate;
opening the interlayer dielectric layer through an etching process;
forming a first through hole by etching process to manufacture contact window
Forming a second via by a through silicon via process
Depositing a barrier layer and a conductive material in the first through hole and the second through hole;
removing the conductive material except the first through hole and the second through hole through chemical mechanical polishing;
depositing a conductive layer and patterning the conductive layer;
and (5) passivation process.

Claims (10)

1. The manufacturing method of the trench gate power device is characterized by comprising the following steps of:
providing a substrate;
forming an epitaxial layer on the front surface of the substrate;
forming groove gates in the epitaxial layer, and forming a channel region between the groove gates;
forming a source region on the surface of the channel region;
forming a drain region on the back surface of the substrate;
forming an interlayer dielectric layer on the epitaxial layer, wherein the interlayer dielectric layer covers the source region and the trench gate;
forming a first through hole penetrating through the interlayer dielectric layer in the interlayer dielectric layer, and filling the first through hole with a conductive material to form a first metal guide hole connecting the source region and the trench gate;
forming a first conductive layer on the interlayer dielectric layer, and patterning the first conductive layer to form a grid electrode and a source electrode, wherein the source electrode and the grid electrode are electrically connected with the first metal guide hole;
forming a first hard mask on the first conductive layer;
forming a second through hole in the interlayer dielectric layer and the first hard mask, wherein the second through hole penetrates through the epitaxial layer;
filling the second via with a conductive material, thereby forming a second metal via connecting the drain region;
depositing a second conductive layer over the second metal via, patterning the second conductive layer to form a drain, the drain electrically connected to the second metal via;
depositing a second hard mask over the second conductive layer;
the first hard mask and the second hard mask are patterned to expose the source electrode, the gate electrode, and the drain electrode.
2. The method for manufacturing the trench gate power device as claimed in claim 1, wherein:
the diameter of the second through hole is more than 10 mu m.
3. The method for manufacturing the trench gate power device as claimed in claim 2, wherein:
the depth of the second through hole is 3-150 mu m.
4. The method for manufacturing the trench gate power device as claimed in claim 3, wherein:
after filling the second through hole with the conductive material, the conductive material in the area outside the second through hole is removed.
5. The method for manufacturing the trench gate power device as claimed in claim 4, wherein:
the second via-filled conductive material may be at least one selected from Cu, co, al, W, ti, tiN, ta, taN.
6. The manufacturing method of the trench gate power device is characterized by comprising the following steps:
providing a substrate;
forming an epitaxial layer on the front surface of the substrate;
forming groove gates in the epitaxial layer, and forming a channel region between the groove gates;
forming a source region on the surface of the channel region;
forming a drain region on the back surface of the substrate;
forming an interlayer dielectric layer on the epitaxial layer;
forming a first through hole and a second through hole in the interlayer dielectric layer, wherein the first through hole penetrates through the interlayer dielectric layer, and the second through hole penetrates through the epitaxial layer;
filling the first via and the second via with a conductive material such that the first via forms a first metal via connecting the source region and the trench gate and the second via forms a second metal via connecting the drain region;
depositing a conductive layer over the first metal via and the second metal via;
patterning the conductive layer over the first metal via to form a gate and a source, and patterning the conductive layer over the second metal via to form a drain;
depositing a hard mask on the conductive layer;
the hard mask is patterned to expose the source, the gate, and the drain.
7. The method for manufacturing the trench gate power device as claimed in claim 6, wherein:
the diameter of the second through hole is more than 10 mu m.
8. The method for manufacturing the trench gate power device as claimed in claim 7, wherein:
the depth of the second through hole is 3-150 mu m.
9. The method for manufacturing the trench gate power device as claimed in claim 8, wherein:
after the first and second vias are filled with the conductive material, the conductive material in areas other than the first and second vias is removed.
10. A trench gate power device, comprising:
a substrate;
an epitaxial layer over the substrate;
a trench gate is formed in the epitaxial layer;
a channel region located between each of the trench gates;
the source region is positioned on the surface of the channel region;
an interlayer dielectric layer and a hard mask are arranged on the epitaxial layer; the interlayer dielectric layer is provided with a first through hole and a second through hole, the first through hole penetrates through the interlayer dielectric layer, and the second through hole penetrates through the epitaxial layer; the first through hole and the second through hole are filled with conductive materials;
a gate electrode and a source electrode patterned from a conductive layer formed over the first via hole;
and a drain electrode patterned by the conductive layer formed on the second via hole.
CN202310716074.4A 2023-06-15 2023-06-15 Manufacturing method of trench gate power device and trench gate power device Pending CN116631872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310716074.4A CN116631872A (en) 2023-06-15 2023-06-15 Manufacturing method of trench gate power device and trench gate power device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310716074.4A CN116631872A (en) 2023-06-15 2023-06-15 Manufacturing method of trench gate power device and trench gate power device

Publications (1)

Publication Number Publication Date
CN116631872A true CN116631872A (en) 2023-08-22

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Application Number Title Priority Date Filing Date
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