CN117894747A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN117894747A CN117894747A CN202311724694.9A CN202311724694A CN117894747A CN 117894747 A CN117894747 A CN 117894747A CN 202311724694 A CN202311724694 A CN 202311724694A CN 117894747 A CN117894747 A CN 117894747A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- trench
- forming
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 90
- 238000001465 metallisation Methods 0.000 claims abstract description 66
- 230000008569 process Effects 0.000 claims description 69
- 239000000758 substrate Substances 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 24
- 239000003989 dielectric material Substances 0.000 claims description 18
- 238000001312 dry etching Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 238000007517 polishing process Methods 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 238000011049 filling Methods 0.000 abstract description 15
- 238000005429 filling process Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 5
- 230000002349 favourable effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 246
- 229910052751 metal Inorganic materials 0.000 description 30
- 239000002184 metal Substances 0.000 description 30
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 239000005368 silicate glass Substances 0.000 description 8
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000005137 deposition process Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 229920002313 fluoropolymer Polymers 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- WUPHOULIZUERAE-UHFFFAOYSA-N 3-(oxolan-2-yl)propanoic acid Chemical compound OC(=O)CCC1CCCO1 WUPHOULIZUERAE-UHFFFAOYSA-N 0.000 description 2
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052980 cadmium sulfide Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 229910021426 porous silicon Inorganic materials 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910008807 WSiN Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application provides a manufacturing method of a semiconductor structure, which comprises the following steps: forming a trench extending downward from the upper surface of the dielectric layer; chamfering at least the top corners of the grooves to form the grooves into gradually expanding contours from the inside toward the opening direction; forming a metallization layer positioned in the groove and on the upper surface of the dielectric layer, wherein the metallization layer positioned on the upper surface of the dielectric layer is provided with a concave surface which is leveled and flattened in gradient and is not lower than the upper surface of the dielectric layer; and removing the part of the metallization layer positioned on the upper surface of the dielectric layer so that the upper surface of the metallization layer is flush with the upper surface of the dielectric layer. The method can widen the filling process window of the conductive plug, improve the problem of filling the cavity, improve the flatness of the metallization layer, improve the step coverage performance of the subsequently deposited covering layer, and be favorable for improving the hole filling effect and the device performance and reducing the production cost.
Description
Technical Field
The application belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor structure and a manufacturing method thereof.
Background
As the lateral dimensions of interconnect structures continue to decrease, there is an increasing demand for void-free or seam-free metal filling capability for implementing substrate-to-metal, and inter-metal interconnects. For power field effect transistor structures, there is an etch to form a trench region in a conventional fabrication process, and a metal such as tungsten is deposited and grown in the trench region to form the gate, source and drain leads and connections thereto. However, as the critical dimensions of devices shrink, the aspect ratio of the trenches increases accordingly, which tends to recess the upper metal layer when the trench regions are filled with metal.
At this stage, a common solution is to form a relatively flat surface by depositing a thicker metal layer and then removing the excess portion of the metal layer by a mechanical planarization process such as Chemical Mechanical Polishing (CMP). The above scheme has the following problems: it is necessary to ensure that the trench area is covered with a relatively thick metal layer when depositing the metal layer so that the metal layer is thick enough in the mechanical planarization process to ensure process margin, but this will undoubtedly increase the manufacturing process costs of the metal filling. In some cases, the lowermost surface of the inverted cone-shaped recess may enter the inside of the trench or the via hole, and the complete planarization of the recess region cannot be ensured by a Chemical Mechanical Polishing (CMP) process, so that a cavity is formed in the metallization layer located in the trench or the via hole, thereby affecting the electrical performance of the device.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a semiconductor structure and a manufacturing method thereof, which are used for solving the problems of small filling process window, high manufacturing cost and influence on the electrical performance of metal caused by the fact that the upper metal is easy to generate a recess in the process of filling the trench or the through hole with high depth-width ratio with metal.
To achieve the above and other related objects, the present application provides a method for fabricating a semiconductor structure, including the steps of:
forming a dielectric layer on a substrate;
forming a trench extending downwards from the upper surface of the dielectric layer;
chamfering at least the top corners of the grooves to form the grooves into gradually expanding contours from the inside toward the opening direction;
forming a metallization layer positioned in the groove and on the upper surface of the dielectric layer, wherein the metallization layer positioned on the upper surface of the dielectric layer is provided with a concave surface which is leveled and is not lower than the upper surface of the dielectric layer;
and removing the part of the metallization layer positioned on the upper surface of the dielectric layer so that the upper surface of the metallization layer is flush with the upper surface of the dielectric layer.
Optionally, the step of forming a dielectric layer on the substrate includes:
forming a first dielectric layer on the substrate;
and forming a second dielectric layer on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are made of different dielectric materials.
Optionally, the step of chamfering at least the top corners of the groove includes:
reflux-treating the second dielectric material positioned at the top corners of the grooves by adopting a heating treatment process so as to round the top corners of the grooves; wherein the material of the second medium comprises one or a combination of at least two of USG, PSG, BPSG and FSG, and the heating treatment process is performed at a temperature not lower than 500 ℃.
Optionally, the step of forming a trench extending downward from an upper surface of the dielectric layer includes: and etching the dielectric layer by adopting an anisotropic dry etching process to form a groove in the dielectric layer.
Optionally, before the step of forming the dielectric layer on the substrate, the method includes:
forming a gate structure on the substrate and a source region on a side of the gate structure,
the grid structure comprises a grid dielectric layer and a grid conductor which are sequentially positioned on the upper surface of the substrate;
an etch stop layer is formed over the gate structure and the substrate.
Optionally, forming a trench extending from the upper surface of the dielectric layer to the etching stop layer, wherein the trench is a contact hole, the contact hole comprises a gate contact hole exposing the surface of the gate structure, and a source contact hole exposing the source region is formed;
and performing ion implantation and rapid thermal annealing processes on the substrate through the contact hole to form a contact region at the bottom of the contact hole.
Optionally, before the ion implantation into the contact hole, the step of chamfering at least the top corner of the trench includes:
and carrying out transverse etching treatment on the second dielectric layer by adopting a wet etching process so as to form the groove into a gradually-expanding profile from the inside towards the opening direction.
Optionally, the wet etching process is performed using an etchant having a selectivity to the second dielectric layer such that a section of the trench adjacent to the opening is formed as a diverging profile.
Optionally, after the step of forming the trench, the method includes: and etching the dielectric layer by adopting an anisotropic dry etching process, wherein the obtained groove is formed with a side wall with an inverted cone-shaped profile, and the groove is formed into an interconnection groove.
Optionally, the step of forming the trench includes: and etching the dielectric layer through an anisotropic dry etching process based on the pattern mask, wherein the obtained groove is formed with a side wall with an inverted cone-shaped profile, and the groove is formed into an interconnection groove.
Optionally, after the chamfering treatment step is performed on at least the top corners of the grooves, the chamfering treatment step includes:
forming an adhesion layer, a seed layer and a metallization layer which are sequentially positioned on the inner surface of the groove, wherein the metallization layer fills the groove and covers the groove and the upper surface of the dielectric layer;
and flattening the metallization layer by adopting a chemical mechanical polishing process, and removing the part of the metallization layer, which is positioned on the upper surface of the dielectric layer, so that the upper surface of the metallization layer is flush with the upper surface of the dielectric layer.
The application also provides a semiconductor structure, which is manufactured according to the manufacturing method of the semiconductor structure, and comprises the following steps:
a substrate;
a dielectric layer on the substrate, wherein a groove extending downwards from the upper surface of the dielectric layer is arranged in the dielectric layer, and the groove comprises a vertex angle part subjected to chamfering treatment so that the groove is formed into a gradually-expanding profile from the inside towards the opening direction;
and the metallization layer is filled in the groove, and the upper surface of the metallization layer is flush with the upper surface of the dielectric layer.
As described above, the semiconductor structure and the manufacturing method thereof of the present application have the following beneficial effects:
after forming a groove extending downwards from the upper surface of a dielectric layer, chamfering the top corner of the groove to form a gradually-expanding shape from the inner part towards the opening direction, and then filling metal into the groove, wherein the obtained metalized layer has a concave surface with a flat gradient and not lower than the upper surface of the dielectric layer, so that the situation that the concave surface enters the groove in the filling process of the groove with a higher depth-to-width ratio is avoided, on one hand, the filling process window of a conductive plug can be widened, and the problem of filling a cavity is solved; on the other hand, the flatness of the metallization layer can be improved, the step coverage performance of the subsequent covering layer is improved, the hole filling effect and the device performance are improved, and the production cost is reduced.
Drawings
Fig. 1 shows a schematic diagram of the structure obtained after the conventional metal filling process.
Fig. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present application.
FIGS. 3 a-3 i are cross-sectional views illustrating various stages in a method of fabricating a semiconductor structure in a first embodiment of the present application; wherein,
fig. 3a shows a cross-sectional view after forming a gate structure according to a first embodiment of the present application;
figure 3b shows a cross-sectional view of the first embodiment of the present application after forming the source region;
FIG. 3c shows a cross-sectional view of the first embodiment of the present application after forming a dielectric layer;
FIG. 3d shows a cross-sectional view of the first embodiment of the present application after forming a trench;
fig. 3e shows a cross-sectional view of the first embodiment of the present application after forming a contact region;
fig. 3f shows a cross-sectional view of the first embodiment of the present application after chamfering the top corners of the trench;
FIG. 3g shows a cross-sectional view of the first embodiment of the present application after formation of an adhesion layer;
FIG. 3h illustrates a cross-sectional view of the first embodiment of the present application after forming a metallization layer;
fig. 3i shows a cross-sectional view after removal of a portion of the metallization layer according to the first embodiment of the present application.
Fig. 4 shows a partial enlarged view of the structure shown in fig. 3 h.
FIGS. 5 a-5 c are cross-sectional views illustrating stages in a method of fabricating a semiconductor structure in a second embodiment of the present application; wherein,
fig. 5a shows a cross-sectional view of the second embodiment of the present application after chamfering the top corners of the trench;
fig. 5b shows a cross-sectional view of a second embodiment of the present application after forming a contact region;
fig. 5c shows a cross-sectional view after removal of a portion of the metallization layer according to a second embodiment of the present application.
Fig. 6 a-6 b are cross-sectional views illustrating stages of a method of fabricating a semiconductor structure in a third embodiment of the present application; wherein,
FIG. 6a shows a cross-sectional view of a third embodiment of the present application after bottom corners of the trench are rounded;
fig. 6b shows a cross-sectional view after removal of a portion of the metallization layer according to a third embodiment of the present application.
Fig. 7 a-7 b are cross-sectional views illustrating stages of a method of fabricating a semiconductor structure according to a fourth embodiment of the present application; wherein,
fig. 7a shows a cross-sectional view of a fourth embodiment of the present application after forming a trench;
fig. 7b shows a cross-sectional view after removal of a portion of the metallization layer according to a fourth embodiment of the present application.
Description of element numbers:
100. substrate and method for manufacturing the same
112. Gate dielectric layer
114. Gate conductor
120. Source region
122. Source contact region
210. Etching stop layer
220. Dielectric layer
230. Groove(s)
231a apex angle
232a adjacent to the open section
232b bottom corner
241. Adhesive layer
1242. 242 metallization layer
1242c inverted cone shaped recess
242c slope flattening concave
Height of H1, H2
Detailed Description
The following will describe embodiments of the present application in detail with reference to the drawings and examples, thereby how to apply technical means to the present application to solve technical problems, and realizing the technical effects can be fully understood and implemented accordingly. It should be noted that, as long as no conflict exists, each embodiment and each feature in each embodiment in the present application may be combined with each other, and the formed technical solutions are all within the protection scope of the present application.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one component or feature's relationship to another component or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
Unless specifically indicated below, the various portions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), and the like, group IV-IV semiconductors such as silicon carbide (SiC), and the like, group II-VI compound semiconductors such as cadmium sulfide (CdS), cadmium telluride (CdTe), and the like, and group IV semiconductors such as silicon (Si), germanium (Ge), and the like.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present utility model by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. For clarity, the drawings are not drawn to scale and may be simplified and not all structures are indicated. Elements and features of one embodiment may be advantageously used in other embodiments without further elaboration.
The present application relates generally to, but is not limited to, trench fill-related problems, and trench may refer to a hole, trench, gap, or similar feature located above a substrate and disposed in a dielectric layer for forming a conductive connection, referred to herein as a "dielectric layer" including inter-layer dielectric layers, inter-metal dielectric layers, and/or similar functional dielectric layers.
Although planar field effect transistors are generally described herein, it will be apparent to those of ordinary skill in the art that using this information disclosed herein, the fabrication methods of the semiconductor structures of the present application are applicable to the fabrication of trench gate field effect transistors, shielded gate field effect transistors, or other similar structures.
Fig. 2 shows a cross-sectional view of a semiconductor structure according to an embodiment of the present application. The semiconductor structure includes a substrate 100 and a dielectric layer 220, the dielectric layer 220 being located on an upper surface of the substrate, the substrate 100 typically being a silicon substrate.
The semiconductor structure comprises a trench 230 in a dielectric layer 220, the trench 230 extending downwardly from an upper surface of the dielectric layer 220 and penetrating the dielectric layer 220, the trench 230 comprising a chamfer-treated top corner 231a such that at least an upper section of the trench has a lateral dimension gradually increasing in a direction towards the opening, i.e. the trench is formed as a diverging profile from the inside towards the opening. In this application, the grooves 230 may have the top corners 231a chamfered. In one embodiment, the top 231a is a rounded top, or a right-angled top.
The semiconductor structure includes a metallization layer 242, the metallization layer 242 filling the trench 230, the end face of the metallization layer 242 terminating at the opening of the trench 230 such that the upper surface of the metallization layer is level with the upper surface of the dielectric layer.
The semiconductor structure further includes a device layer on the substrate 100, the device layer including a source region (not shown) on an upper surface of the substrate, and a gate structure on an upper surface of the substrate, the source region being disposed on a side of the gate structure.
In one embodiment, as shown in fig. 2, the gate structure includes a gate dielectric layer 112 and a gate conductor 114 sequentially stacked on a substrate 100, the dielectric layer 220 is used as an interlayer dielectric layer, and a metallization layer fills the contact hole for electrode extraction.
In one embodiment, the semiconductor structure further includes at least one metal interconnect layer between the substrate 100 and the dielectric layer 220, the dielectric layer 220 acting as an inter-metal dielectric layer, the metallization layer filling interconnect trenches extending through the dielectric layer for making electrical connections between devices.
Fig. 3a to 3i are sectional views illustrating stages of a method for fabricating a semiconductor structure according to an embodiment of the present application. The following describes a method for manufacturing the semiconductor structure according to the embodiment of the present application with reference to fig. 3a to 3 i.
Fig. 3a shows a cross-sectional view after forming a gate structure according to a first embodiment of the present application. As shown in fig. 3a, a gate structure is formed on the upper surface of the substrate 100.
In this step, a gate dielectric layer 112 and a gate conductor 114 are sequentially formed on the upper surface of the substrate 100.
In one embodiment, a gate dielectric layer is formed on the upper surface of the substrate 100 by thermal oxidation or chemical vapor deposition. The gate dielectric layer 112 may be comprised of an oxide or nitride, such as silicon oxide or silicon nitride, among others. For example, thermal oxidation includes hydrothermal oxidation HTO or selective reactive oxidation (Selective Reactive Oxidation; SRO) processes, and Chemical Vapor Deposition (CVD) processes include Low Pressure Chemical Vapor Deposition (LPCVD) processes, or sub-atmospheric pressure chemical vapor deposition (SACVD) processes.
In one embodiment, the gate conductor 114 is deposited over the gate dielectric layer 112 by chemical vapor deposition. The gate dielectric layer 112 isolates the gate conductor 114 from the substrate 100.
In this step, a photoresist layer is formed over the gate conductor 114; and sequentially performing a series of photoetching processes such as spin coating, photoresist exposure, development and the like, patterning the photoresist layer to form a patterned region in the photoresist layer, wherein the patterned region corresponds to the etching position, and etching the gate structure along the etching position.
Fig. 3b shows a cross-sectional view after source regions are formed in accordance with the first embodiment of the present application. As shown in fig. 3b, a self-aligned source region 120 is formed based on the gate structure, i.e. the source region 120 is located at the side of the gate structure.
Further, as shown in fig. 3b, in the present embodiment, after the process step of manufacturing the device layer, an etch stop layer 210 is formed on the substrate 100, and the etch stop layer 210 is interposed between the substrate 100 and the dielectric layer 220, and may be conformally deposited on the surfaces of the gate structure and the substrate by, for example, a plasma chemical vapor deposition (PECVD) process.
Fig. 3c shows a cross-sectional view after forming a dielectric layer according to a first embodiment of the present application. As shown in fig. 3c, a dielectric layer 220 is formed over the substrate 100.
A step of forming a dielectric layer 220, including forming a first dielectric layer 2201 on the substrate; the first dielectric layer 2202 is formed on the first dielectric layer, and the first dielectric layer 2201 and the second dielectric layer 2202 may be made of the same or different dielectric materials. The first dielectric layer 2201 is between the etching stop layer 210 and the second dielectric layer 2202, where the material of the first dielectric layer may be a Low-K dielectric material, for example, a porous material with a dielectric constant less than 3.5, for example, porous silicon oxide, carbon doped silicon oxide (Black Diamond), and nitrogen doped silicon carbide (BLOK); the second dielectric material used to form the second dielectric layer 2202 may include Undoped Silicate Glass (USG), phosphorus doped silicate glass (PSG), boron phosphorus doped silicate glass (BPSG), fluorine doped silicate glass (FSG), or a dielectric material with good flowability, which is advantageous for planarization. In one embodiment, the second dielectric layer 2202 may be optionally Undoped Silicate Glass (USG) to prevent oxygen radicals from damaging the porous dielectric material during the photoresist ashing process.
It will be appreciated by those skilled in the art that the first dielectric layer and the second dielectric layer may be formed by a suitable deposition process, including but not limited to a Low Pressure Chemical Vapor Deposition (LPCVD) process, an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or the like, depending on the type of dielectric material.
In an example, the first dielectric layer 2201 may be Undoped Silicate Glass (USG) deposited by a PECVD process and the second dielectric layer 2202 may be boron-phosphorus doped silicate glass (BPSG) deposited by an APCVD process.
Fig. 3d shows a cross-sectional view after forming a trench according to the first embodiment of the present application. As shown in fig. 3d, a trench 230 is formed extending downward from the upper surface of the dielectric layer 220.
In this step, for example, a hard mask layer (not shown) is formed on the dielectric layer 220 by using a deposition process, and a series of photolithography processes such as spin-on photoresist, exposure and development may be sequentially performed to define a photoresist pattern; transferring the photoresist pattern into the hard mask layer through an etching process to form a patterned hard mask layer, wherein the photoresist pattern can be removed through an ashing process in a subsequent process; subsequently, the dielectric layer 220 is etched by an anisotropic dry etching process based on the patterned hard mask layer, forming a trench 230 extending downward from the upper surface of the dielectric layer. In one embodiment, the anisotropic dry etching process may be, for example, plasma etching, or reactive ion etching.
In one embodiment, the trench 230 may be a contact hole, the etch stop layer 210 is conformally deposited over the gate structure and the substrate 100, the contact hole extending from the upper surface of the dielectric layer to the etch stop layer may be formed by an anisotropic dry etching process, forming a first contact hole exposing the gate structure, and forming a second contact hole exposing the source region. The etching selectivity of the dielectric layer with respect to the etch stop layer can be changed by adjusting the composition, concentration and reaction conditions of the etchant used to perform the dry etching, so that a first contact hole exposing the gate structure is formed while a second contact hole exposing the source region is formed.
Fig. 3e shows a cross-sectional view after the contact region is formed in accordance with the first embodiment of the present application. As shown in fig. 3e, a contact region is formed at the bottom of the contact hole, wherein the contact region includes a source contact region 122.
After forming the contact hole, an ion implantation process is performed on the substrate through the contact hole, and a source contact region 122 is formed at the bottom of the contact hole exposing the source region through a Rapid Thermal Annealing (RTA) process. In one embodiment, the trench 230 is a contact hole disposed in the dielectric layer.
In other embodiments, the trench 230 may be an interconnection trench in the dielectric layer, so that the above steps for forming the contact region are not required.
Fig. 3f shows a cross-sectional view of the first embodiment of the present application after chamfering the top corners of the trench; as shown in fig. 3f, the top corners 231a of the grooves are rounded.
In this step, the top corners 231a of the grooves 230 are rounded so that the grooves 230 have a gradually expanding shape from the inside toward the opening direction. When the first dielectric layer 2201 and the second dielectric layer 2202 are made of different dielectric materials, the materials used to form the first dielectric layer and the second dielectric layer include one or a combination of at least two of USG, PSG, BPSG and FSG,
in one embodiment, rounding the top corners of the trench 230 includes: the second dielectric layer 2202 on the upper surface layer of the dielectric layer is reflowed by a heat treatment process to round the top corners of the trench, and in particular, the second dielectric material on the top corners of the trench is reflowed, as shown in fig. 3f, to round the top corners 231a of the trench. For example, the dielectric layer 220 is heated by heating at a temperature of not lower than 500 ℃, preferably 500 ℃ to 1000 ℃ for 10 to 30 minutes, the second dielectric material located at the top corners 231a of the trench, for example, the top corners 231a of the trench, is heated more intensively to generate reflow, the top corners 231a of the trench are rounded, thereby realizing the transition of the top corners 231a of the trench from right angles to rounded angles, and the sections 232a of the trench adjacent to the opening are formed into a diverging shape; at the same time, the second dielectric layer becomes more uniform, forming a denser film. By "diverging profile" as referred to herein is meant that the top corners of the trench are chamfered after the step of forming the trench such that the section of the trench adjacent to the opening has a lateral dimension that gradually increases from the interior of the trench towards the opening, for example a linearly increasing or a non-linearly increasing lateral dimension.
FIG. 3g shows a cross-sectional view of the first embodiment of the present application after formation of an adhesion layer; as shown in fig. 3g, an adhesion layer is formed on the inner surface of the trench.
After the step of rounding the top corners of the trench 230, an adhesion layer 241 is deposited on the inner surface of the trench to block diffusion of metal and promote adhesion of the subsequently deposited metallization layer to the oxide layer. In one embodiment, the adhesion layer 241 may be formed by a deposition process such as Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD), and the adhesion layer 241 may contain ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tungsten silicon nitride (WSiN), tantalum (Ta), tantalum nitride (TaN), or other alloys containing these materials. In one embodiment, a seed layer (not shown) is deposited over adhesion layer 241; preferably, a seed layer may be conformally deposited on adhesion layer 241 by, for example, a PECVD process to enhance the fill quality of the subsequently deposited metallization layer.
FIG. 3h illustrates a cross-sectional view of the first embodiment of the present application after forming a metallization layer; as shown in fig. 3h, a metallization layer 242 is formed within the trench and on the upper surface of the dielectric layer.
In this step, a metallization layer 242 filling the trench 230 and covering the trench and the dielectric layer 220 is formed, wherein the resulting metallization layer 242 has a recessed surface with a slope that is planarized and not lower than the upper surface of the dielectric layer, and the metallization layer 242 may contain at least one of ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu). In one embodiment, the metal filling material used to form the metallization layer 242 may be tungsten, and the metallization layer 242 is formed by, for example, an electroplating process or a chemical vapor deposition process. Because the grooves shown in fig. 3f are formed into the rounded outline of the top corners, the surface flatness of the metallization layer formed in the metal filling process is improved, the occurrence of filling holes is avoided, and the window of the filling process is widened.
It will be appreciated by those skilled in the art that the metallization layer may be deposited using well known materials and deposition processes, and is not particularly limited herein.
Fig. 4 shows an enlarged view of a portion of the structure shown in fig. 3h, in contrast to fig. 1 which shows a schematic view of the structure after a prior art metal filling process. As shown in fig. 1, the dielectric layer 220 is provided with a trench 1230 extending downward from the upper surface thereof, a metallization layer 1242 fills the trench 1230 and overlies the trench 1230, and the surface of the metallization layer 1242 above the trench 1230 is formed as an inverted cone-shaped recess 1242c, the inverted cone-shaped recess surface entering the interior of the trench 1230.
As can be seen from fig. 4, in the process of forming the metallization layer 242 filling the trench 230 and covering the upper surface of the dielectric layer by providing the trench 230 with the rounded top corners in the dielectric layer 220, the slope change tends to be gentle compared with the metallization layer 1242 shown in fig. 1 on the concave surface of the metallization layer 242 in this application, and the maximum thickness and the minimum thickness from the top surface of the concave 242c with the flat slope to the dielectric layer are respectively H 1 And H 2 Indicating thickness H 1 And H 2 Near, the concave surface of the inverted cone is not lower than the upper surface of the dielectric layer 220, indicating a significant improvement in the metal filling effect.
FIG. 3i shows a cross-sectional view of a first embodiment of the present application after removal of a portion of the metallization layer; as shown in fig. 3i, the metallization layer on the upper surface of the dielectric layer is removed so that the upper surface of the metallization layer is flush with the upper surface of the dielectric layer.
In this step, planarization is performed by mechanical polishing, so that a portion of the metallization layer 242 located on the upper surface of the dielectric layer is removed, and the end surface of the remaining metallization layer 242 terminates at the opening of the trench 230, where the upper surface of the resulting metallization layer is substantially flush or level with the upper surface of the dielectric layer. In one embodiment, when the adhesion layer 241 and the seed layer (not shown) are sequentially deposited on the inner surface of the trench 230 and cover the upper surface of the dielectric layer, the metallization layer, the seed layer and the adhesion layer on the upper surface of the dielectric layer are removed during the planarization process. In one embodiment, the planarization process is performed by, for example, a chemical mechanical polishing process.
In this embodiment, the adhesion layer 241, the seed layer and the metallization layer 242 remaining in the contact hole integrally form a conductive plug, wherein the conductive plug is formed in the first contact hole for realizing electrode extraction of the gate conductor, and the conductive plug is formed in the second contact hole for realizing electrode extraction of the source region and the source contact region.
Fig. 5a to 5c are sectional views illustrating stages of a method for fabricating a semiconductor structure according to an embodiment of the present application. The following describes a method for manufacturing a semiconductor structure according to an embodiment of the present application with reference to fig. 5a to 5 c.
In this embodiment, in the same manner as the steps shown in fig. 3a to 3d in the first embodiment, a trench extending downward from the upper surface of the substrate is formed, and will not be described here again.
Fig. 5a shows a cross-sectional view of the second embodiment of the present application after chamfering the top corners of the trench; as shown in fig. 5a, the section 232a of the trench adjacent to the opening is laterally etched to form the trench into a diverging profile from the inside toward the opening.
In this step, the second dielectric layer is laterally etched by a wet etching process based on a patterned mask, so that the section 232a of the trench adjacent to the opening is formed into a tapered shape, the patterned mask may be a patterned hard mask layer remaining on the dielectric layer after the trench 230 is formed, and the patterned hard mask layer may be removed in a subsequent process to expose the opening of the trench 230. In an embodiment, the first dielectric layer and the second dielectric layer are made of different dielectric materials, an etchant with etching selectivity to the second dielectric layer is selected to perform a wet etching process, and the etching selectivity ratio of the top corner of the trench relative to the bottom corner can be changed by adjusting the composition, concentration and reaction condition of the etchant, so that the upper section of the trench is etched preferentially and the etching amount of the middle and lower sections is reduced.
For example, FPM (HF-H 2 O 2 -H 2 O mixture) is subjected to a wet etch process in which the etch selectivity of the second dielectric layer with respect to the etch stop layer 210 is increased by increasing the H in the FPM solution 2 O 2 The etching selectivity ratio of the porous silicon oxide layer to the silicon oxynitride is improved to 10:1 such that the etched portion is located primarily in the region 232a of the trench adjacent the opening, and the bottom corner topography of the trench is unchanged or nearly unchanged, thereby reducing the effect on the topography below the middle region of the trench. In other examples, the amount of sidewall etching is greater for the upper section of the trench relative to the middle and lower sections of the trench at the same time by adjusting the amount of HF in the FPM solution, and the duration of the wet etch process.
Fig. 5b shows a cross-sectional view of a second embodiment of the present application after forming a contact region; as shown in fig. 5b, after the section 232a of the trench adjacent to the opening is laterally etched, an ion implantation process is performed on the substrate through the contact hole by using a window defined by the patterned hard mask layer as a mask, and a Rapid Thermal Annealing (RTA) process is performed to form a source contact region 122 at the bottom of the contact hole exposing the source region.
The steps thereafter of this embodiment may be followed by the steps shown in fig. 3g to 3i of the first embodiment to form a conductive plug in the trench, as shown in fig. 5 c. Since the steps thereafter in this embodiment are the same as those shown in fig. 3g to 3i in the first embodiment, the description thereof will be omitted.
Fig. 6a to 6b show, as an additional or alternative implementation, sectional views of stages of a method of manufacturing a semiconductor structure according to an embodiment of the present application. The following describes a method for manufacturing a semiconductor structure according to an embodiment of the present application with reference to fig. 6a to 6 b.
In this embodiment, in the same manner as the steps shown in fig. 3a to 3d in the first embodiment, a trench 230 extending downward from the upper surface of the substrate is formed, and will not be described again.
FIG. 6a shows a cross-sectional view of a third embodiment of the present application after bottom corners of the trench are rounded; as shown in fig. 6a, the trench is isotropically etched to arc the bottom corners of the trench.
In this step, the bottom corners 232b of the trench are rounded by an isotropic dry etching process based on the patterned hard mask layer, which may be the patterned hard mask layer remaining on the dielectric layer after the trench 230 is formed. In one embodiment, the isotropic dry etching process may be a plasma etching process, such as using CH 4 、O 2 、SF 6 、NF 3 As an etchant.
The subsequent steps in this embodiment may be substantially the same steps as those shown in fig. 3e to 3i in the first embodiment (e.g. fig. 6 b), or substantially the same steps as those shown in fig. 5a to 5c in the second embodiment, so as to form the conductive plugs in the trenches, which will not be described herein.
Fig. 7a to 7b are sectional views illustrating stages of a method for fabricating a semiconductor structure according to an embodiment of the present application. The following describes a method for manufacturing a semiconductor structure according to an embodiment of the present application with reference to fig. 7a to 7 b.
In this embodiment, the dielectric layer 220 on the substrate is formed in the same manner as shown in fig. 3a to 3c in the first embodiment, except that at least one metal interconnection layer (not shown) is further formed between the substrate 100 and the dielectric layer 220, and the metal interconnection layer may be preferably formed according to the same steps as shown in fig. 3c to 3i in the first embodiment, although other manners of forming the metal interconnection layer may be adopted.
Further, in this embodiment, the step of forming the dielectric layer 220 includes forming a first dielectric layer 2201 on the underlying metal interconnect layer; the first dielectric layer 2202 is formed on the first dielectric layer, and the first dielectric layer 2201 and the second dielectric layer 2202 may be made of the same or different dielectric materials, for example, the material of the first dielectric layer 2201 may be a Low-K dielectric material, for example, a porous material with a dielectric constant less than 3.0, for example, carbon doped silicon oxide (Black Diamond) and nitrogen doped silicon carbide (BLOK).
It will be appreciated by those skilled in the art that the first dielectric layer and the second dielectric layer may be formed by a suitable deposition process, including but not limited to a Low Pressure Chemical Vapor Deposition (LPCVD) process, an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or the like, depending on the type of dielectric material.
In an example, the first dielectric layer 2201 may be carbon doped silicon oxide (Black Diamond) or nitrogen doped silicon carbide (BLOK) deposited by a PECVD process, where the low dielectric constant material can well reduce signal attenuation caused by impedance and capacitive delay of the circuit itself when the electrical signal propagates, i.e. reduce RC delay of the back-end interconnect; the second dielectric layer 2202 may be Undoped Silicate Glass (USG) deposited by an APCVD process.
Fig. 7a shows a cross-sectional view of a fourth embodiment of the present application after forming a trench; as shown in fig. 7a, a trench 230 is formed extending downward from the upper surface of the dielectric layer.
In this step, the dielectric layer 220 is etched by an anisotropic dry etching process based on a pattern mask to form a trench 230 extending downward from the upper surface of the dielectric layer, and the resulting trench is formed with sidewalls of an inverted cone profile.
In one embodiment, the step of forming the trench includes: dielectric layer 220 is anisotropically etched using the photoresist pattern as a mask, wherein a process such as CH is used 2 F 2 And C 4 F 8 The anisotropic dry etching process is performed with a fluorocarbon high etching gas so that the side walls of the trench are formed to have an inclination angle θ with respect to the horizontal plane where the bottom surface of the trench is located, where θ is preferably 75 ° to 90 °. The etching gas reacts with the dielectric layer during etching to leave fluorocarbon polymer on the sidewall of the trench, the fluorocarbon polymer plays a role of sidewall protection, and the fluorocarbon polymer attached to the sidewall of the trench has a thickness increasing along the depth direction from the opening of the trench to the bottom, as shown in fig. 7b, the thickness of the dielectric material etched away from the opening of the trench 230 towards the bottom is gradually reduced, so that the trench is formed with the sidewall with the inverted cone profile.
The steps thereafter of this embodiment may be followed by the steps shown in fig. 3g to 3i of the first embodiment to form a conductive plug in the trench, as shown in fig. 7 b. Since the steps thereafter in this embodiment are the same as those shown in fig. 3g to 3i in the first embodiment, the description thereof will be omitted.
Further, in the present embodiment, the trench 230 is formed as an interconnection trench, and the metallization layer remaining in the interconnection trench is formed as a conductive plug for connecting adjacent metal interconnection layers, and the device and external circuit.
It will be appreciated by those skilled in the art that although the specific process steps for forming a conductive plug in an intermetal dielectric layer are illustrated herein as an example, the method of fabricating a semiconductor structure of the present application is also applicable to vias, deep trenches, or similar features having high aspect ratios to be filled.
While the embodiments disclosed herein are described above, the descriptions are presented only to facilitate an understanding of the present application and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of protection of this application shall be subject to the scope of the claims that follow.
Claims (12)
1. A method of fabricating a semiconductor structure, the method comprising:
forming a dielectric layer on a substrate;
forming a trench extending downwards from the upper surface of the dielectric layer;
chamfering at least the top corners of the grooves to form the grooves into gradually expanding contours from the inside toward the opening direction;
forming a metallization layer positioned in the groove and on the upper surface of the dielectric layer, wherein the metallization layer positioned on the upper surface of the dielectric layer is provided with a concave surface which is leveled and is not lower than the upper surface of the dielectric layer;
and removing the part of the metallization layer positioned on the upper surface of the dielectric layer so that the upper surface of the metallization layer is flush with the upper surface of the dielectric layer.
2. The method of claim 1, wherein the step of forming a dielectric layer on the substrate comprises:
forming a first dielectric layer on the substrate;
and forming a second dielectric layer on the first dielectric layer, wherein the first dielectric layer and the second dielectric layer are made of different dielectric materials.
3. The method according to claim 2, wherein the chamfering process for at least the top corners of the trench comprises:
reflux-treating the second dielectric material positioned at the top corners of the grooves by adopting a heating treatment process so as to round the top corners of the grooves; wherein the material of the second medium comprises one or a combination of at least two of USG, PSG, BPSG and FSG, and the heating treatment process is performed at a temperature not lower than 500 ℃.
4. The method of claim 1, wherein the step of forming a trench extending downward from the upper surface of the dielectric layer comprises: and etching the dielectric layer by adopting an anisotropic dry etching process to form a groove in the dielectric layer.
5. The method of claim 2, wherein prior to the step of forming a dielectric layer on the substrate, comprising:
forming a gate structure on the substrate and a source region on a side of the gate structure,
the grid structure comprises a grid dielectric layer and a grid conductor which are sequentially positioned on the upper surface of the substrate;
an etch stop layer is formed over the gate structure and the substrate.
6. The method of manufacturing according to claim 5, wherein:
forming a groove extending from the upper surface of the dielectric layer to the etching stop layer, wherein the groove is a contact hole, and the contact hole comprises a gate contact hole exposing the surface of the gate structure and a source contact hole exposing the source region;
and performing ion implantation and rapid thermal annealing processes on the substrate through the contact hole to form a contact region at the bottom of the contact hole.
7. The method of manufacturing according to claim 6, wherein the chamfering at least the top corners of the trench before the ion implantation into the contact hole comprises:
and carrying out transverse etching treatment on the second dielectric layer by adopting a wet etching process so as to form the groove into a gradually-expanding profile from the inside towards the opening direction.
8. The method of manufacturing according to claim 7, wherein: the wet etching process is performed with an etchant having a selectivity to the second dielectric layer such that a section of the trench adjacent to the opening is formed into a diverging profile.
9. The method of manufacturing according to claim 3 or 7, wherein after the step of forming the trench, comprising:
and an isotropic dry etching process is adopted to enable the bottom corner of the groove to be circular-arc.
10. The method of manufacturing of claim 1, wherein the step of forming the trench comprises: and etching the dielectric layer by adopting an anisotropic dry etching process, wherein the obtained groove is formed with a side wall with an inverted cone-shaped profile, and the groove is formed into an interconnection groove.
11. The method according to claim 1, wherein the chamfering step for at least the top corners of the trench comprises:
forming an adhesion layer, a seed layer and a metallization layer which are sequentially positioned on the inner surface of the groove, wherein the metallization layer fills the groove and covers the groove and the upper surface of the dielectric layer;
and flattening the metallization layer by adopting a chemical mechanical polishing process, and removing the part of the metallization layer, which is positioned on the upper surface of the dielectric layer, so that the upper surface of the metallization layer is flush with the upper surface of the dielectric layer.
12. A semiconductor structure, characterized in that the semiconductor structure is manufactured according to the manufacturing method of the semiconductor structure according to any one of claims 1 to 11, and the semiconductor structure comprises:
a substrate;
a dielectric layer on the substrate, wherein a groove extending downwards from the upper surface of the dielectric layer is arranged in the dielectric layer, and the groove comprises a vertex angle part subjected to chamfering treatment so that the groove is formed into a gradually-expanding profile from the inside towards the opening direction;
and the metallization layer is filled in the groove, and the upper surface of the metallization layer is flush with the upper surface of the dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311724694.9A CN117894747A (en) | 2023-12-14 | 2023-12-14 | Semiconductor structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311724694.9A CN117894747A (en) | 2023-12-14 | 2023-12-14 | Semiconductor structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117894747A true CN117894747A (en) | 2024-04-16 |
Family
ID=90643178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311724694.9A Pending CN117894747A (en) | 2023-12-14 | 2023-12-14 | Semiconductor structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117894747A (en) |
-
2023
- 2023-12-14 CN CN202311724694.9A patent/CN117894747A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10943823B2 (en) | Conductive feature formation and structure using bottom-up filling deposition | |
| KR101967541B1 (en) | Contact plugs and methods forming same | |
| US6407002B1 (en) | Partial resist free approach in contact etch to improve W-filling | |
| KR100791345B1 (en) | Semiconductor device including a recessed spherical silicide contact portion and method of manufacturing the same | |
| US6503829B2 (en) | Metal via contact of a semiconductor device and method for fabricating the same | |
| US6337282B2 (en) | Method for forming a dielectric layer | |
| US7670946B2 (en) | Methods to eliminate contact plug sidewall slit | |
| US6444574B1 (en) | Method for forming stepped contact hole for semiconductor devices | |
| US9773699B2 (en) | Methods of forming wiring structures including a plurality of metal layers | |
| US8026604B2 (en) | Semiconductor devices having contact holes including protrusions exposing contact pads | |
| US6551901B1 (en) | Method for preventing borderless contact to well leakage | |
| US6548388B2 (en) | Semiconductor device including gate electrode having damascene structure and method of fabricating the same | |
| KR20170096690A (en) | Methods of forming wiring structures and methods of manufacturing semiconductor devices | |
| CN106373921A (en) | Method for interconnect scheme | |
| CN113451203A (en) | Method for forming semiconductor structure | |
| KR20160067349A (en) | Methods of forming conductive structures, semiconductor devices and methods of manufacturing semiconductor devices | |
| CN217822792U (en) | Semiconductor structure and semiconductor device | |
| US7098515B1 (en) | Semiconductor chip with borderless contact that avoids well leakage | |
| CN117894747A (en) | Semiconductor structure and manufacturing method thereof | |
| US6218291B1 (en) | Method for forming contact plugs and simultaneously planarizing a substrate surface in integrated circuits | |
| JP3677755B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN111211095B (en) | Method for manufacturing conductive interconnection line | |
| US6583055B1 (en) | Method of forming stepped contact trench for semiconductor devices | |
| US20230013102A1 (en) | Semiconductor device structure and methods of forming the same | |
| CN217933788U (en) | Integrated circuit structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |