CN114121881A - Interconnect structure with air gaps and method - Google Patents

Interconnect structure with air gaps and method Download PDF

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Publication number
CN114121881A
CN114121881A CN202010907052.2A CN202010907052A CN114121881A CN 114121881 A CN114121881 A CN 114121881A CN 202010907052 A CN202010907052 A CN 202010907052A CN 114121881 A CN114121881 A CN 114121881A
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CN
China
Prior art keywords
air gap
mask
layer
dielectric layer
metal
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Chinese (zh)
Inventor
金廷修
高建峰
刘卫兵
杨涛
李俊峰
王文武
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Priority to CN202010907052.2A priority Critical patent/CN114121881A/en
Publication of CN114121881A publication Critical patent/CN114121881A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

Abstract

The invention provides an interconnection structure with an air gap aiming at the problem of complex preparation process of the interconnection structure with the air gap, which comprises the following steps: the first dielectric layer is provided with a first groove, and a first metal is arranged in the first groove; the second interlayer dielectric layer is formed on the upper surface of the first dielectric layer and provided with a second groove, a first through hole is formed in the bottom of the second groove, a second metal is arranged in the second groove and the first through hole, and the second metal is electrically conducted with the first metal; the second dielectric layer is also provided with an air gap, and the air gap is arranged between two adjacent second metals; and the air gap sealing layer is formed on the second dielectric layer and is used for sealing the opening at the top of the air gap. The interconnection structure with the air gap provided by the invention can complete the etching of the through hole and the air gap together without a subsequent separate treatment process, and the process is simple.

Description

Interconnect structure with air gaps and method
Technical Field
The present invention relates to the field of semiconductor device technology, and more particularly, to an interconnection structure with an air gap and a method thereof.
Background
The increasing demand for speed and functionality of semiconductor devices has led to an increasing degree of integration of semiconductor devices. Due to high integration of the device, the width of the metal lines and the interval between the lines become narrow, and parasitic capacitance is easily generated between the metal lines, and the function of the device is easily degraded due to the generation of the parasitic capacitance. In general, a method of depositing a material having a low dielectric constant on an interlayer insulating film is mainly used to reduce parasitic capacitance generated between metal lines. The method of forming the air gap includes forming an air gap pattern, filling the air gap with a sacrificial material, removing the metal wiring after it is formed, and performing separate photolithography and wet etching processes for forming the air gap after the metal wiring to remove an interlayer insulating film.
Disclosure of Invention
The interconnection structure with the air gap and the method provided by the invention can form the air gap and the through hole simultaneously, and the process is simple.
In a first aspect, the present invention is an interconnect structure with an air gap, comprising:
the first dielectric layer is provided with a first groove, and a first metal is arranged in the first groove;
the second interlayer dielectric layer is formed on the upper surface of the first dielectric layer and provided with a second groove, a first through hole is formed in the bottom of the second groove, a second metal is arranged in the second groove and the first through hole, and the second metal is electrically conducted with the first metal; the second dielectric layer is also provided with an air gap, and the air gap is arranged between two adjacent second metals;
and the air gap sealing layer is formed on the second dielectric layer and is used for sealing the opening at the top of the air gap.
Optionally, a barrier layer is disposed between the first dielectric layer and the second dielectric layer, a second through hole corresponding to the first through hole is disposed on the barrier layer, and the second metal in the first through hole penetrates through the second through hole and is electrically conducted with the first metal.
Optionally, the air gap capping layer is formed of an oxide of silane group or an oxide of tetraethoxysilane group formed by a plasma enhanced chemical vapor deposition method; the air gap sealing layer covers the top opening of the air gap, so that the air gap forms a closed cavity.
According to the interconnection structure with the air gap, the etching of the air gap and the etching of the through hole are completed in the same step, and the air gap is sealed after the etching of the air gap and the etching of the through hole are completed, so that the air gap structure cannot be influenced when other layer materials are deposited subsequently. Therefore, the interconnection structure with the air gap can simultaneously form the air gap and the through hole without adding other process steps.
In a second aspect, the present invention provides an interconnection method with air gaps, comprising:
providing a laminated structure to be etched, wherein the laminated structure comprises a first dielectric layer, a barrier layer, a second dielectric layer and a first mask which are sequentially laminated from bottom to top; the first dielectric layer is provided with a first groove, and a first metal is arranged in the first groove;
patterning the first mask to form a patterned first mask;
etching the second dielectric layer according to the patterned first mask to form a first through hole and an air gap;
removing the patterned first mask;
forming an air gap sealing layer on the upper surface of the first dielectric layer to seal and cover the upper opening of the air gap;
continuously etching the second dielectric layer to form a second groove;
depositing a second metal in the first through hole and the second groove so as to electrically conduct the second metal with the first metal; the air gap is positioned between two adjacent second metals.
Optionally, the air gap capping layer is formed of an oxide of silane group or an oxide of tetraethoxysilane group formed by a plasma enhanced chemical vapor deposition method; the air gap sealing layer covers the top opening of the air gap, so that the air gap forms a closed cavity.
Optionally, before the etching the second dielectric layer to form the first via and the air gap, the method further includes:
and depositing a second mask layer on the patterned first mask to adjust the size of the first mask pattern.
Optionally, the thickness of the second mask layer is less than 49% of the air gap dimension.
Optionally, the second mask layer forms a step coverage of the patterned first mask by using an atomic layer deposition technique.
Optionally, a pattern size of the air gaps in the patterned first mask is less than 49% of the first via size.
Optionally, the first mask is a hard mask or a photoresist.
According to the interconnection method with the air gap, the etching of the air gap and the etching of the through hole are completed in the same step, and the air gap is sealed after the etching of the air gap and the etching of the through hole are completed, so that the air gap structure is not affected when other layer materials are deposited subsequently. Therefore, the interconnection method with the air gap can simultaneously form the air gap and the through hole without adding other process steps.
Drawings
FIG. 1 is a schematic diagram of an interconnect structure with air gaps in accordance with one embodiment of the present invention;
fig. 2 a-2 e are schematic process diagrams of an interconnection method with air gaps according to an embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The present embodiment provides an interconnect structure with air gaps 32, as shown in fig. 1, including: the device comprises a first medium layer 1, wherein the first medium layer 1 is provided with a first groove, and a first metal 11 is arranged in the first groove; a second dielectric layer 3 formed on the upper surface of the first dielectric layer 1, the second interlayer dielectric layer having a second groove 33, the bottom of the second groove 33 being provided with a first through hole 31, a second metal (not shown) being provided in the second groove 33 and the first through hole 31, the second metal (not shown) being electrically connected to the first metal 11; the second dielectric layer 3 further has an air gap 32, and the air gap 32 is disposed between two adjacent second metals (not shown in the figure); and an air gap capping layer 6 formed on the second dielectric layer 3, wherein the air gap capping layer 6 is used for capping the opening on the top of the air gap 32.
In this embodiment, a first dielectric layer 1 may be formed over the substrate,such as silicon, silicon germanium, compound semiconductors, etc., and a device layer, such as a MOSFET, DRAM, or NAND device, may be formed on the substrate. The first dielectric layer 1 may be a contact layer in which the first metal 11 is connected to the source and drain regions of the MOSFET, or the first dielectric layer 1 may be a metal layer in which the first metal 11 is connected to an underlying metal layer. The second dielectric layer 3 is a low-k dielectric layer, and may be one or more of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, silicon nitride, and nitrogen-doped silicon carbide as an optional embodiment, and as a specific optional embodiment, the second dielectric layer 3 may be a nitrogen-doped silicon carbide/carbon-doped silicon oxide/silicon oxide multilayer stacked structure. In the first dielectric layer 1, a first groove is formed to provide a deposition position for the first metal 11, and the first metal 11 is deposited in the first groove. On the second dielectric layer 3, a deposition position is provided for a second metal (not shown in the figure) by forming a through hole and a groove, the second metal (not shown in the figure) is deposited in the through hole and the groove, so that the second metal (not shown in the figure) is electrically connected with the first metal 11, and an air gap 32 is formed between two adjacent second metals (not shown in the figure). An air gap capping layer 6 is further formed on the upper surface of the second dielectric layer 3, and the air gap capping layer 6 caps the top of the air gap 32, so that the air gap 32 is not closed due to entering the air gap 32 when other subsequent materials are deposited. Therefore, the interconnection structure with the air gap 32 provided by the embodiment can complete the etching of the air gap 32 and the etching of the through hole in the same step, and the air gap 32 is capped after the completion, so that the structure of the air gap 32 is not affected when other layer materials are subsequently deposited. Therefore, the interconnect structure with the air gap 32 of the present embodiment enables the air gap 32 and the via to be formed simultaneously without adding other process steps. In a preferred embodiment, the air gap capping layer 6 is formed by a silane-based oxide or a tetraethoxysilane-based oxide formed by a plasma enhanced chemical vapor deposition method, and the air gap capping layer is used for capping the top opening of the air gap so as to form a closed cavity by the air gap; step-coating of silane-based oxide or tetraethoxysilane-based oxide formed by the aforementioned plasma enhanced chemical vapor deposition methodThe covering capability is weak, and at the same time, due to the small size of the air gap 32, the air gap 32 is not deposited into the air gap 32 during the deposition process, but the covering is formed at the opening of the air gap 32, so that the complete air gap covering layer 6 can be formed to cover the air gap 32. As another preferred embodiment, for the air gap capping layer, the ordinary oxide can be formed by PVD, for example, SiO can be deposited by reactive sputtering of silicon target with oxygen and argon2Or directly using SiO2Target sputter deposition of SiO2(ii) a Of course, other poorly covering SiO's may be used2A membrane or other dielectric membrane.
As an optional implementation manner, a barrier layer 2 is disposed between the first dielectric layer 1 and the second dielectric layer 3, a second via corresponding to the first via 31 is disposed on the barrier layer 2, and a second metal (not shown in the figure) in the first via 31 penetrates through the second via to be electrically connected to the first metal 11. During the etching process, since the etching depth needs to be controlled, the barrier layer 2 needs to be provided. Thereby, the barrier layer 2 is provided as an end point during the etching of the second medium during the etching process. In addition, the region of the barrier layer 2 covering the upper surface of the first metal 11 also has the function of blocking the diffusion of the first metal 11 into the second dielectric layer 3. As a preferred embodiment, nitrogen-doped silicon carbide can be selected as the material of the barrier layer 2. Of course, if the etching end point of the second medium can be precisely controlled by other methods, the whole device structure may not have the barrier layer 2, for example, the etching end point is controlled according to the etching rate or controlled by the end point detection method.
The present embodiment provides an interconnection method with air gaps 32, including:
s1, providing a laminated structure to be etched, wherein the laminated structure comprises a first dielectric layer 1, a barrier layer 2, a second dielectric layer 3 and a first mask 4 which are sequentially laminated from bottom to top; wherein the first dielectric layer 1 is provided with a first groove, and a first metal 11 is arranged in the first groove; as an optional specific implementation manner of this step, the stacked structure to be etched may be prepared in the following manner:
a substrate is first provided, and as an alternative embodiment, silicon germanium, a compound semiconductor, or the like may be selected as the substrate. The first dielectric layer 1 may be formed over a substrate on which a device layer, such as a MOSFET, DRAM, or NAND device, may be formed. The first dielectric layer 1 may be a contact layer in which the first metal 11 is connected to the source and drain regions of the MOSFET, or the first dielectric layer 1 may be a metal layer in which the first metal 11 is connected to an underlying metal layer.
Forming a hard mask on the first dielectric layer 1, coating photoresist in a spinning mode, carrying out patterning processing on the photoresist, etching the hard mask by adopting the photoresist after patterning processing to form a patterned hard mask, then etching the first dielectric layer 1 according to the patterned hard mask to form a first groove, and then carrying out planarization processing after depositing a first metal 11 in the first groove; before depositing the first metal 11, in order to ensure that the first metal 11 does not diffuse into the material of the first dielectric layer 1, a diffusion barrier layer may be first deposited before depositing the metal, and the material of the diffusion barrier layer may be tantalum or tantalum oxide. After the deposition of the first metal 11 is completed, the device is planarized to form a flat plane for subsequent processes.
A barrier layer 2 is deposited on the upper surface of the device. In the subsequent etching process, since the etching depth needs to be controlled, the barrier layer 2 needs to be provided. Thereby, the barrier layer 2 is provided as an end point during the etching of the second medium during the etching process. As a preferred embodiment, nitrogen-doped silicon carbide can be selected as the material of the barrier layer 2.
A second dielectric is deposited on the upper surface of the barrier layer 2. The second dielectric layer 3 is a low-k dielectric layer.
A first mask 4 is deposited on the second dielectric layer 3, and as an alternative embodiment, the first mask 4 may be a hard mask or may be a photoresist.
S2, performing a patterning process on the first mask 4 to form a patterned first mask 4; as an optional specific implementation manner of this step, when the first mask 4 is a hard mask, a photoresist needs to be formed on the hard mask, and then the photoresist needs to be subjected to photolithography, so as to pattern the photoresist, and the patterned photoresist is used to etch the hard mask, and then the photoresist is removed, so as to form the patterned first mask 4. When the first mask 4 is made of photoresist, the patterning process for the first mask 4 may be completed by photolithography, so as to form the patterned first mask 4. The patterned first mask 4 includes a pattern of first through holes 31 and a pattern of air gaps 32. The structure formed after this step is completed is shown in fig. 2 a.
S3, etching the second dielectric layer 3 according to the patterned first mask 4 to form a first via 31 and an air gap 32; as an optional embodiment of this step, the second dielectric layer 3 is etched based on the patterned first mask 4, and during the etching process, the first via 31 and the air gap 32 are simultaneously etched, and at this time, the position of the air gap 32 is located between the subsequently formed second metals (not shown in the figure) to improve or avoid the parasitic capacitance phenomenon between the adjacent second metals (not shown in the figure).
S4, removing the patterned first mask 4; as an alternative embodiment of this step, when the first mask 4 is a hard mask, the photoresist may be removed by a photoresist stripping method, for example, by soc (spin on carbon) or soh (spin on hardmark), or, when the material is appropriate, by a wet method. When the first mask 4 is a photoresist, the existing photoresist removing process may be used for removing the photoresist. The structure formed after this step is completed is shown in fig. 2 c.
S5, forming an air gap sealing layer 6 on the upper surface of the first dielectric layer 1 to seal the upper opening of the air gap 32; after the upper opening of the air gap 32 is covered, the air gap 32 is not affected when other materials are deposited subsequently, so that the purpose that the first through hole 31 and the air gap 32 are completed in the same etching process in the embodiment can be achieved. In a preferred embodiment, the air gap capping layer 6 is formed by a silane-based oxide or a tetraethoxysilane-based oxide formed by a plasma enhanced chemical vapor deposition process, and the air gap capping layer is used to cap the top opening of the air gapSo that the air gap forms a closed cavity; the silane-based oxide or tetraethoxysilane-based oxide step formed by the aforementioned pecvd method has a weak coverage, and at the same time, due to the small size of the air gap 32, the silane-based oxide or tetraethoxysilane-based oxide is not deposited into the air gap 32 during the deposition process, but covers the opening of the air gap 32, so that the air gap 32 can be covered by the complete air gap capping layer 6. The structure after this step is completed is shown in fig. 2 d. As another preferred embodiment, for the air gap capping layer, the ordinary oxide can be formed by PVD, for example, SiO can be deposited by reactive sputtering of silicon target with oxygen and argon2Or directly using SiO2Target sputter deposition of SiO2(ii) a Of course, other poorly covering SiO's may be used2A membrane or other dielectric membrane.
S6, continuously etching the second dielectric layer 3 to form a second groove; as an optional specific implementation manner of this embodiment, a specific process of this step is as follows:
forming a mask on the second medium, and carrying out patterning treatment on the mask;
the second dielectric layer 3 is etched according to the patterned mask, so as to form a second groove 33, and the bottom of the second groove 33 is communicated with the first via 31, so that a second metal (not shown in the figure) subsequently deposited in the groove can be electrically conducted with the first metal 11 through the second metal (not shown in the figure) deposited in the via. The structure formed after this step is completed is shown in fig. 2 e. In fig. 2e, the rightmost second recess 33 does not show a via hole communicating with it, however, it should be understood by those skilled in the art that the second recess 33 may be deposited with a second metal (not shown) for electrical interconnection of the layer, or there may be a metal plug in the second recess 33, which is conductive to the metal in the first dielectric layer 1 or other layers, but not in the current cross section.
S7, depositing a second metal (not shown) in the first via 31 and the second recess 33 to electrically connect the second metal (not shown) and the first metal 11; the air gap 32 is located between two adjacent second metals (not shown).
As an optional implementation manner of this embodiment, before etching the second dielectric layer 3 to form the first through hole 31 and the air gap 32, the method further includes: a layer of a second mask 5 is deposited on the patterned first mask 4 to adjust the size of the pattern of the first mask 4. When the second mask 5 layer is formed, since the material of the second mask 5 layer covers the sidewalls of the pattern of the first mask 4, the size of the pattern of the first mask 4, that is, the size of the etched via and air gap 32, can be adjusted during the formation process. As an alternative embodiment, the second mask 5 layer forms a step coverage of the patterned first mask 4 using atomic layer deposition techniques. When the second mask 5 layer is formed, a material with stronger step coverage capability needs to be adopted, and the material is formed by adopting an atomic layer deposition technology, so that the second mask 5 layer can form good step coverage for the first mask 4, and the capability of adjusting the pattern size of the first mask 4 can be improved. The completed structure of this embodiment is shown in fig. 2 b.
As an optional implementation manner of this embodiment, the thickness of the second mask 5 layer is less than 49% of the size of the air gap 32. The thickness of the second mask 5 layer can be selected according to the requirement, when the size of the air gap 32 is required to be smaller, the thickness of the second mask 5 layer can be selected to be larger, and when the size of the air gap 32 is required to be larger, the thickness of the second mask 5 layer can be selected to be smaller. For example, the thickness of the second mask 5 layer may be selected to be 1%, 25%, or 49% of the air gap 32 dimension; of course, other ratios may be selected according to actual requirements.
As an optional implementation manner of this embodiment, the pattern size of the air gaps 32 in the patterned first mask 4 is less than 49% of the size of the first through holes 31. The pattern size of the air gap 32 can be selected according to specific requirements, for example, the size of the air gap 32 pattern can be selected to be 1%, 25% or 49% of the size of the first through hole 31, and of course, other proportions can be selected according to actual requirements.
The interconnection method with the air gap 32 provided by the embodiment can be applied to a dual damascene process, the etching of the air gap 32 and the etching of the through hole are completed in the same step, and the air gap 32 is capped after the completion, so that the structure of the air gap 32 is not affected when other layer materials are subsequently deposited. Therefore, the interconnection method with the air gap 32 of the present embodiment enables the air gap 32 and the via to be formed simultaneously without adding other process steps.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. An interconnect structure having an air gap, comprising:
the first dielectric layer is provided with a first groove, and a first metal is arranged in the first groove;
the second interlayer dielectric layer is formed on the upper surface of the first dielectric layer and provided with a second groove, a first through hole is formed in the bottom of the second groove, a second metal is arranged in the second groove and the first through hole, and the second metal is electrically conducted with the first metal; the second dielectric layer is also provided with an air gap, and the air gap is arranged between two adjacent second metals;
and the air gap sealing layer is formed on the second dielectric layer and is used for sealing the opening at the top of the air gap.
2. The interconnect structure with an air gap according to claim 1, wherein a barrier layer is disposed between the first dielectric layer and the second dielectric layer, a second via corresponding to the first via is disposed on the barrier layer, and the second metal in the first via is electrically connected to the first metal through the second via.
3. The interconnect structure with an air gap according to claim 1, wherein the air gap capping layer is formed of an oxide of a silane group or an oxide of an tetraethoxysilane group formed by a plasma enhanced chemical vapor deposition method; the air gap sealing layer covers the top opening of the air gap, so that the air gap forms a closed cavity.
4. An interconnect method with air gaps, comprising:
providing a laminated structure to be etched, wherein the laminated structure comprises a first dielectric layer, a barrier layer, a second dielectric layer and a first mask which are sequentially laminated from bottom to top; the first dielectric layer is provided with a first groove, and a first metal is arranged in the first groove;
patterning the first mask to form a patterned first mask;
etching the second dielectric layer according to the patterned first mask to form a first through hole and an air gap;
removing the patterned first mask;
forming an air gap sealing layer on the upper surface of the first dielectric layer to seal and cover the upper opening of the air gap;
continuously etching the second dielectric layer to form a second groove;
depositing a second metal in the first through hole and the second groove so as to electrically conduct the second metal with the first metal; the air gap is positioned between two adjacent second metals.
5. The method of claim 4, wherein the air gap capping layer is formed of an oxide of silane group or an oxide of tetraethoxysilane group formed by plasma enhanced chemical vapor deposition; the air gap sealing layer covers the top opening of the air gap, so that the air gap forms a closed cavity.
6. The interconnection method with air gaps of claim 4, wherein before etching the second dielectric layer to form the first via and the air gap, further comprising:
and depositing a second mask layer on the patterned first mask to adjust the size of the first mask pattern.
7. The method of claim 6, wherein the thickness of the second mask layer is less than 49% of the air gap dimension.
8. The method of claim 6, wherein the second mask layer forms a step coverage of the patterned first mask using atomic layer deposition.
9. The method of claim 4, wherein a pattern size of the air gaps in the patterned first mask is less than 49% of the first via size.
10. The method of claim 4, wherein the first mask is a hard mask or a photoresist.
CN202010907052.2A 2020-09-01 2020-09-01 Interconnect structure with air gaps and method Pending CN114121881A (en)

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