CN115863183A - Method for manufacturing flow-measurable micro-channel for heat dissipation of three-dimensional integrated wafer system - Google Patents
Method for manufacturing flow-measurable micro-channel for heat dissipation of three-dimensional integrated wafer system Download PDFInfo
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Abstract
The invention discloses a method for manufacturing a micro flow channel with measurable flow for heat dissipation of a three-dimensional integrated wafer system, which comprises the following steps: the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure on the upper surface of a silicon wafer on an insulator, and constructing a force-sensitive resistor and a temperature measuring resistor; and (3) releasing the silicon dioxide of the buried oxide layer: etching a release hole on the upper surface of the silicon wafer on the insulator, and corroding silicon dioxide on an oxygen burying layer below the release hole by using a wet method to form a micro channel; and (3) closing the release hole by electroplating copper: seed layer metal is deposited on the upper surface of the silicon wafer on the insulator and the side wall of the release hole, and a copper cylinder is formed on the basis of the seed layer copper electroplating to seal the upper surface of the micro flow channel; inorganic copper plating on the inner wall of the micro-channel: and plating copper heat dissipation layers on the upper surface and the lower surface of the inner wall of the micro flow channel by using a chemical method.
Description
Technical Field
The application relates to the technical field of electronics, in particular to a method for manufacturing a micro flow channel with measurable flow for heat dissipation of a three-dimensional integrated wafer system.
Background
In the post-Moore era, with the development of advanced packaging technology, different chips can be integrated by high-density three-dimensional stacking, so that the performance of the system is greatly improved. However, the high-density integrated system generates a large amount of heat, which seriously affects the normal operation of the chip. In recent years, heat dissipation from the inside of a three-dimensionally integrated chip has been performed using a microchannel carrying a coolant. One conventional method is to etch a groove structure of a micro-channel on the back of a chip, and then perform alignment bonding with another silicon chip or glass chip etched with the groove structure of the micro-channel to form a micro-channel closed pipeline; the other common method is to coat organic polymer on the back of the chip and etch the groove structure of the micro-channel, and then to form the micro-channel closed pipeline by attaching with other gaskets. The conventional method needs to additionally introduce other liners and bonding processes, which not only increases the process complexity, but also increases the thickness of the chip.
Disclosure of Invention
Aiming at the problems in the prior art, the embodiment of the application aims to provide a preparation method of a wafer heat dissipation micro-channel with a piezoresistive flow detection function, a buried oxide layer Silicon dioxide sacrificial release process is developed On the basis of a Silicon-On-Insulator (SOI) wafer, organic polymers do not need to be filled, and a micro-channel closed pipeline can be formed only by depending On device layer Silicon, buried oxide layer Silicon dioxide and substrate layer Silicon of the SOI wafer; an electro-coppering sealing process and an inner wall selective chemical copper plating process are developed, and the formed copper column heat sink and the inner wall metallized copper layer greatly improve the heat dissipation capacity of the micro-channel; meanwhile, the invention also integrates a piezoresistive flowmeter in the micro-channel, and can detect the flow speed and the temperature of the cooling liquid microfluid in real time.
According to a first aspect of the embodiments of the present application, there is provided a method for manufacturing a micro flow channel with a measurable flow rate for heat dissipation of a three-dimensional integrated wafer system, including:
the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure on the upper surface of a silicon wafer on an insulator, and constructing a force-sensitive resistor and a temperature measuring resistor;
and (3) releasing the silicon dioxide of the buried oxide layer: etching a release hole on the upper surface of the silicon wafer on the insulator, and corroding silicon dioxide of the buried oxide layer below the release hole by using a wet method to form a micro channel;
and (3) closing the release hole by electroplating copper: seed layer metal is deposited on the upper surface of the silicon wafer on the insulator and the side wall of the release hole, and a copper cylinder is formed on the basis of the seed layer copper electroplating to seal the upper surface of the micro flow channel;
inorganic copper plating on the inner wall of the micro-channel: and plating copper heat dissipation layers on the upper surface and the lower surface of the inner wall of the micro flow channel by using a chemical method.
Further, the silicon-on-insulator wafer is the back surface of the silicon wafer adapter plate with the active integrated circuit or the completed silicon vertical through hole and the rewiring layer.
Further, the piezoresistive flowmeter manufacturing step includes:
photoetching and etching the upper surface of the silicon wafer on the insulator to form a first force-sensitive strain structure, wherein the first force-sensitive strain structure is a cantilever beam, a folding beam-flat plate or a thin film with holes;
forming a semiconductor force-sensitive resistor on the first force-sensitive strain structure by ion implantation;
forming a temperature measuring resistor by depositing metal in the vicinity of the force sensitive resistor;
and sputtering chromium/gold to form an ohmic contact electrode of the force-sensitive resistor and an interconnection line of the temperature measuring resistor, and depositing first passivation layer silicon dioxide by plasma enhanced chemical vapor deposition.
Further, the step of releasing the silicon dioxide of the buried oxide layer comprises the following steps:
etching a release hole and a cooling liquid inlet and outlet hole on the upper surface of the silicon wafer on the insulator by photoetching;
coating a thick photoresist on the outer side wall of the cooling liquid inlet and outlet hole and the first passivation layer silicon dioxide on the upper silicon surface of the insulator, wherein the thickness of the thick photoresist is more than or equal to 10 microns;
and carrying out wet etching on the silicon dioxide on the buried oxide layer below the release hole through the release hole and the cooling liquid inlet and outlet holes to form a micro-channel for the cooling liquid to flow in the horizontal direction.
Further, the release hole electro-coppering closing step comprises:
depositing a chromium/copper seed layer on the upper surface of the silicon-on-insulator wafer and the side walls of the release holes;
growing copper in the release holes by an electroplating method to form a copper column heat sink;
stripping the thick photoresist on the surface, wherein the thickness of the thick photoresist is more than or equal to 10 microns;
and depositing a second passivation layer of silicon dioxide on the lower surface of the silicon-on-insulator wafer.
Further, the step of inorganic copper plating on the inner wall of the micro-channel comprises the following steps:
and immersing the silicon wafer on the insulator into an electroless copper plating solution, and forming an upper surface copper deposition layer and a lower surface copper deposition layer on the upper surface and the lower surface of the inner wall of the micro flow channel.
Further, the electroless copper plating solution comprises an activation solution and a reaction solution, the silicon wafer on the insulator is firstly immersed into the activation solution for activation and then immersed into the reaction solution for copper plating, wherein the components of the activation solution comprise deionized water, hydrofluoric acid and palladium chloride, and the components of the reaction solution comprise copper sulfate and formaldehyde.
Further, the method also comprises a vibration compensation step, wherein the vibration compensation step is arranged before the buried oxide layer silicon dioxide release step, and the vibration compensation step comprises the following steps:
and constructing a second force-sensitive strain structure on the upper surface of the silicon-on-insulator wafer outside the micro flow channel so as to eliminate errors generated by vibration on fluid pressure measurement.
Further, after the step of inorganic copper plating on the inner wall of the micro flow channel, removing the second passivation layer silicon dioxide.
According to a second aspect of the embodiments of the present application, there is provided a use of the micro flow channel with measurable flow rate for heat dissipation of three-dimensional integrated wafer system manufactured according to the method of the first aspect, for preparing a silicon wafer interposer with vertical through silicon vias or redistribution layers for three-dimensional vertical stack integration of multi-layer integrated circuit chips or wafers.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
firstly, the micro-fluid channel is directly manufactured on the back of the wafer based on the SOI wafer, and the micro-fluid channel is not required to be bonded with other silicon chips or glass sheets with the micro-channel, so that the process complexity is reduced;
secondly, the sacrificial release process of the buried oxide layer silicon dioxide based on the SOI wafer is skillfully developed, organic polymer is not required to be filled, and a micro-channel closed pipeline can be formed only by depending on device layer silicon, buried oxide layer silicon dioxide and substrate layer silicon of the SOI wafer;
thirdly, the application skillfully develops an electroplating copper sealing process and an inner wall selective chemical copper plating process, wherein the electroplating copper column structure not only can seal the side wall of the micro-channel, but also can form a heat sink structure to improve the heat dissipation capability; the inner wall selective chemical copper plating process can deposit copper layers on the upper surface and the lower surface of the inner wall of the micro-channel, so that the heat dissipation capacity of the inner wall of the micro-channel is further improved;
fourth, the present application develops a piezoresistive flow meter integrated with a microchannel on-chip, and has the functions of temperature compensation and vibration compensation, which can monitor the flow rate and temperature of the cooling liquid in real time.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a flowchart illustrating a method for manufacturing a micro flow channel with a measurable flow rate for heat dissipation of a three-dimensional integrated wafer system according to an exemplary embodiment, wherein (a) in fig. 1 to (h) in fig. 1 are schematic structural diagrams of each flow path in the method for manufacturing a micro flow channel with a measurable flow rate for heat dissipation of a three-dimensional integrated wafer system.
FIG. 2 is a schematic diagram illustrating a shock compensation configuration according to an exemplary embodiment.
Fig. 3 is a schematic top view of a flow-enabled microchannel for heat dissipation in a three-dimensional integrated wafer system according to an exemplary embodiment.
Fig. 4 is a schematic diagram of an embodiment of a flow-measurable micro flow channel for heat dissipation in a three-dimensional integrated wafer system in a three-dimensional integrated application field according to an exemplary embodiment.
In the figure: 1. an SOI wafer; 2. a first force sensitive strain structure; 3. a force sensitive resistor; 4. a temperature measuring resistor; 5. a first passivation layer of silicon dioxide; 6. a release aperture; 7. buried oxide layer silicon dioxide; 8. cooling liquid inlet and outlet holes; 9. thick photoresist; 10. a micro flow channel; 11. closing the cylinder; 12. a second passivation layer of silicon dioxide; 13. a copper deposit layer on the upper surface; 14. a lower surface copper deposition layer; 15. a second force sensitive strain structure; 16. an integrated circuit chip; 17. micro-bumps; 18. a rewiring layer; 19. silicon vertical vias.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on context.
Fig. 1 is a flow chart illustrating a method for manufacturing a flow-measurable micro flow channel for heat dissipation of a three-dimensional integrated wafer system according to an exemplary embodiment, as shown in fig. 1, the method may include the following steps:
the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure 2, a force-sensitive resistor 3 and a temperature measuring resistor 4 on the upper surface of a silicon wafer on an insulator;
and (3) releasing the buried oxide layer silicon dioxide 7: etching a release hole 6 on the upper surface of the silicon wafer on the insulator, and corroding buried oxide layer silicon dioxide 7 below the release hole 6 by using a wet method to form a micro channel 10;
and (3) closing the release holes 6 by electroplating copper: seed layer metal is deposited on the upper surface of the silicon-on-insulator wafer and the side walls of the release holes 6, and copper columns are formed on the basis of seed layer copper electroplating to seal the upper surface of the micro flow channels 10;
inorganic copper plating on the inner wall of the micro-channel 10: and plating copper heat dissipation layers on the upper surface and the lower surface of the inner wall of the micro flow channel 10 by using a chemical method.
From the above embodiments, it can be seen that the present application directly manufactures the micro fluid channel on the back of the wafer based on the SOI wafer 1, and the micro fluid channel 10 is not required to be bonded with other silicon wafers or glass sheets with the micro fluid channel 10, thereby reducing the process complexity; the sacrifice release process of the buried oxide layer silicon dioxide 7 based on the SOI wafer 1 is skillfully developed, organic polymer is not required to be filled, and a closed pipeline of the micro-channel 10 can be formed only by depending on device layer silicon, the buried oxide layer silicon dioxide 7 and substrate layer silicon of the SOI wafer 1; an electro-coppering sealing process and an inner wall selective chemical copper plating process are skillfully developed, wherein the electro-coppering pillar structure can not only seal the side wall of the micro-channel 10, but also form a heat sink structure to improve the heat dissipation capability; the selective chemical copper plating process of the inner wall can deposit copper layers on the upper and lower surfaces of the inner wall of the micro flow channel 10, so that the heat dissipation capacity of the inner wall of the micro flow channel 10 is further improved; a piezoresistive flow meter integrated on-chip with the micro flow channel 10 was developed and has the functions of temperature compensation and vibration compensation, and the flow rate and temperature of the cooling liquid can be monitored in real time.
In the concrete implementation of the manufacturing steps of the piezoresistive flowmeter, a first force-sensitive strain structure 2 is constructed on the upper surface of a silicon-on-insulator (SOI) wafer, and a force-sensitive resistor 3 and a temperature measuring resistor 4 are constructed;
as shown in fig. 1, the fabrication of the micro flow channels 10 begins with a silicon-on-insulator (SOI) wafer (fig. 1 (a)) being the back side of the silicon wafer adapter plate already with active integrated circuits or already with vertical through silicon vias 19 (TSVs) and redistribution layers 18 (RDLs). This step may specifically include the following processes:
photoetching and etching the upper surface of the silicon wafer on the insulator to form a first force-sensitive strain structure 2, wherein the first force-sensitive strain structure 2 is a cantilever beam, a folded beam-flat plate or a thin film with holes; forming a semiconductor force-sensitive resistor 3 on the first force-sensitive strain structure 2 by ion implantation; forming a temperature measuring resistor 4 by depositing metal near the force sensitive resistor 3; and sputtering chromium/gold to form an ohmic contact electrode and an interconnection line of the force-sensitive resistor 3, and depositing a first passivation layer silicon dioxide 5 by plasma enhanced chemical vapor deposition. In a specific implementation, the thermometric resistor 4 is preferably formed by sputtering chromium/platinum, the ohmic contact electrode and the interconnection line of the force sensitive resistor 3 are preferably formed by sputtering chromium/gold, and the first passivation layer silicon dioxide 5 is preferably deposited by plasma enhanced chemical vapor deposition (PECVD (b) in fig. 1).
Before the step of releasing the buried oxide layer silicon dioxide 17, the method may further include a vibration compensation step, which may include:
and constructing a second force-sensitive strain structure 15 on the upper surface of the silicon-on-insulator wafer outside the micro flow channel 10 so as to eliminate errors generated by vibration on fluid pressure measurement.
Fig. 2 shows a vibration compensation structure of the micro flow channel 10 capable of measuring flow rate, pressure and temperature according to the present invention. Since the first force-sensitive strain structure 2 has a certain vibration sensitivity, in order to eliminate an error generated by measuring the fluid pressure by vibration, a second force-sensitive strain structure 15 having the same mechanical sensitive structure as the first force-sensitive strain structure 2 can be manufactured at a position near the micro flow channel 10, the second force-sensitive strain structure 15 also has a force-sensitive resistor 3 and a temperature-measuring resistor 4, and the specific forming process is the same as the manufacturing step of the piezoresistive flowmeter, and is not described herein again. The force sensitive resistors 3 on the second force sensitive strain structure 15 only sense the change of the piezoresistive resistance value caused by vibration and are not influenced by microfluid, so that the influence of vibration can be eliminated by calculating the piezoresistive resistance values measured by the two force sensitive resistors 3.
In the concrete implementation of the release step of the silicon dioxide 7 of the buried oxide layer, etching release holes 6 on the upper surface of the silicon wafer on the insulator, and corroding the silicon dioxide 7 of the buried oxide layer below the release holes 6 by a wet method to form a micro flow channel 10;
specifically, etching release holes 6 and cooling liquid inlet and outlet holes 8 on the upper surface of the silicon-on-insulator wafer by photoetching; coating a thick photoresist 9 on the outer side wall of the cooling liquid inlet and outlet hole 8 and the first passivation layer silicon dioxide 5 on the upper silicon surface of the insulator, wherein the thickness of the thick photoresist 9 is more than or equal to 10 microns, in the specific implementation, the thickness of the photoresist depends on the thickness of a step, and in order to ensure the wall thickness of the micro-channel, a device layer SOI wafer which is more than 5 microns is generally selected, so the thickness of the thick photoresist 9 is preferably 10 microns; and wet etching the silicon dioxide 7 of the buried oxide layer below the release hole 6 through the release hole 6 and the cooling liquid inlet and outlet hole 8 to form a micro channel 10 for the cooling liquid to flow in the horizontal direction. In specific implementation, the first passivation layer silicon dioxide 5 is etched by photolithography, the buried oxide release hole 6 is formed in the upper surface silicon of the SOI wafer 1 (fig. 1 (c)), the upper surface silicon of the SOI wafer 1 and the buried oxide layer silicon dioxide 7 are etched by photolithography to form the cooling liquid access hole 8 (fig. 1 (d)), the thick photoresist 9 is coated by spin coating or spray coating, and the structure in which only the inner sidewall and the inner bottom of the microfluidic access hole are exposed and the outer sidewall and the outer surface are protected by the photoresist is formed by photolithography (fig. 1 (e)). And releasing the silicon dioxide 7 of the buried oxide layer of the SOI wafer 1 by using a wet process, preferably hydrofluoric acid, to form a micro-channel 10.
In the specific implementation of the step of closing the release hole 6 by electroplating copper, seed layer metal is deposited on the upper surface of the silicon-on-insulator wafer and the side wall of the release hole 6, and a copper column is formed on the basis of the seed layer electroplating copper to close the upper surface of the micro flow channel 10;
specifically, a chromium/copper seed layer is deposited on the upper surface of the silicon-on-insulator wafer and the side walls of the release holes 6; copper grows in the release holes 6 by an electroplating method to form a copper column heat sink, and the thick photoresist 9 on the surface is stripped; a second passivation layer of silicon dioxide 12 is deposited on the lower surface of the silicon on insulator wafer. In specific implementation, preferably, chromium/copper is sputtered, a seed layer is formed on the side wall and the outer surface of the release hole 6, and copper electroplating is performed to form a closed cylinder 11, which serves to both close the upper side wall of the micro flow channel 10 and serve as a heat sink. And stripping the thick photoresist 9 coated on the outer side wall of the cooling liquid inlet and outlet hole 8 and the first passivation layer silicon dioxide 5 on the upper surface of the silicon on insulator after the electroplating is finished. Finally, a second passivation layer of silicon dioxide 12 is deposited by PECVD on the lower surface of the SOI wafer 1 ((f) in fig. 1).
In the specific implementation of the inorganic copper plating step on the inner wall of the micro flow channel 10, the copper heat dissipation layer is chemically plated on the upper and lower surfaces of the inner wall of the micro flow channel 10.
Specifically, the silicon-on-insulator wafer is immersed in an electroless copper plating solution, and an upper surface copper deposition layer 13 and a lower surface copper deposition layer 14 are formed on the upper and lower surfaces of the inner wall of the micro flow channel 10. In a specific implementation, the SOI wafer 1 is immersed in an electroless copper plating solution to form a copper deposit on the silicon surface without a copper deposit on the inactive silicon oxide surface. Thus, an upper surface copper deposit layer 13 and a lower surface copper deposit layer 14 are also formed on the upper and lower surfaces of the inner wall of the micro flow channel 10, and the heat dissipation capability of the micro flow channel 10 is further improved ((g) in fig. 1). The electroless metal plating method includes, but is not limited to, copper, gold, nickel. Taking electroless copper plating as an example, the electroless copper plating solution comprises an activation solution and a reaction solution, the silicon-on-insulator wafer is firstly immersed into the activation solution for activation and then immersed into the reaction solution for copper plating, wherein the components of the activation solution include but are not limited to deionized water, hydrofluoric acid and palladium chloride, and the components of the reaction solution include but are not limited to copper sulfate and formaldehyde.
After the inorganic copper plating step on the inner wall of the micro flow channel 10, the second passivation layer silicon oxide 12 is removed ((h) in fig. 1).
Fig. 3 (a) is a schematic top view of a wafer heat sink microchannel 10 with piezoresistive flow detection function. The measuring principle of the micro-fluid flow velocity is a piezoresistive type, when the micro-fluid flow velocity measuring device works, the first force-sensitive strain structure 2 of the cantilever beam structure is driven by flowing of cooling liquid to generate elastic deformation, so that the resistance value of the force-sensitive resistor 3 is changed, and the corresponding flow velocity and flow of the cooling liquid can be obtained by detecting the change of the resistance value. As the resistance value of the force sensitive resistor 3 is sensitive to temperature, the platinum temperature measuring resistor 4 is arranged near the force sensitive resistor 3 and used for carrying out temperature drift compensation on the force sensitive resistor 3. Fig. 3 (b) shows an embodiment of the first force-sensitive strain structure 2 based on a beam-slab structure according to the present invention.
The application also provides application of the micro flow channel with the measurable flow rate, which is manufactured according to the method and used for heat dissipation of the three-dimensional integrated wafer system, in preparation of a silicon wafer adapter plate with silicon vertical through holes or redistribution layers, and the silicon wafer adapter plate is used for three-dimensional vertical stacking integration of multilayer integrated circuit chips or wafers. Fig. 4 shows an embodiment of the micro flow channel with measurable flow for heat dissipation of the three-dimensional integrated wafer system in the three-dimensional integrated application field. The integrated circuit chip 16 is bonded with a silicon wafer adapter plate with a rewiring layer 18 and a heat dissipation micro-channel 10 through micro bumps 17, and signals are led out from the bottom through a silicon vertical through hole 19 (TSV), so that the heat dissipation capacity of the three-dimensional integrated system can be effectively improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof.
Claims (10)
1. A method for manufacturing a micro flow channel with measurable flow rate for heat dissipation of a three-dimensional integrated wafer system is characterized by comprising the following steps:
the manufacturing steps of the piezoresistive flowmeter are as follows: constructing a first force-sensitive strain structure on the upper surface of a silicon wafer on an insulator, and constructing a force-sensitive resistor and a temperature measuring resistor;
and (3) releasing the silicon dioxide of the buried oxide layer: etching a release hole on the upper surface of the silicon wafer on the insulator, and corroding silicon dioxide on an oxygen burying layer below the release hole by using a wet method to form a micro channel;
and (3) release hole electro-coppering sealing: seed layer metal is deposited on the upper surface of the silicon wafer on the insulator and the side wall of the release hole, and a copper cylinder is formed on the basis of the seed layer copper electroplating to seal the upper surface of the micro flow channel;
inorganic copper plating on the inner wall of the micro-channel: and plating copper heat dissipation layers on the upper surface and the lower surface of the inner wall of the micro flow channel by using a chemical method.
2. The method of claim 1, wherein the silicon-on-insulator wafer is a back side of a silicon wafer interposer with active integrated circuits or completed vertical through silicon vias and redistribution layers.
3. The method of claim 1, wherein the piezoresistive flow meter manufacturing step comprises:
photoetching and etching the upper surface of the silicon wafer on the insulator to form a first force-sensitive strain structure, wherein the first force-sensitive strain structure is a cantilever beam, a folding beam-flat plate or a thin film with holes;
forming a semiconductor force-sensitive resistor on the first force-sensitive strain structure by ion implantation;
forming a temperature measuring resistor by depositing metal in the vicinity of the force sensitive resistor;
and sputtering chromium/gold to form an ohmic contact electrode of the force-sensitive resistor and an interconnection line of the temperature measuring resistor, and depositing first passivation layer silicon dioxide by plasma enhanced chemical vapor deposition.
4. The method of claim 1, wherein the buried oxide layer silicon dioxide release step comprises:
etching a release hole and a cooling liquid inlet and outlet hole on the upper surface of the silicon wafer on the insulator by photoetching;
coating a thick photoresist on the outer side wall of the cooling liquid inlet and outlet hole and the first passivation layer silicon dioxide on the upper silicon surface of the insulator, wherein the thickness of the thick photoresist is more than or equal to 10 micrometers;
and carrying out wet etching on the silicon dioxide on the buried oxide layer below the release hole through the release hole and the cooling liquid inlet and outlet hole to form a micro-channel for the cooling liquid to flow in the horizontal direction.
5. The method of claim 1, wherein the release hole electro-coppering closing step comprises:
depositing a chromium/copper seed layer on the upper surface of the silicon-on-insulator wafer and the side walls of the release holes;
growing copper in the release holes by an electroplating method to form a copper column heat sink;
stripping the thick photoresist on the surface, wherein the thickness of the thick photoresist is more than or equal to 10 microns;
and depositing a second passivation layer of silicon dioxide on the lower surface of the silicon-on-insulator wafer.
6. The method according to claim 1, wherein the step of inorganic copper plating the inner wall of the micro flow channel comprises:
and immersing the silicon wafer on the insulator into an electroless copper plating solution to form an upper surface copper deposition layer and a lower surface copper deposition layer on the upper and lower surfaces of the inner wall of the micro flow channel.
7. The method of claim 6, wherein the electroless copper plating solution comprises an activation solution and a reaction solution, the silicon-on-insulator wafer is activated by immersion in the activation solution and then copper plated by immersion in the reaction solution, wherein the composition of the activation solution comprises deionized water, hydrofluoric acid, and palladium chloride, and the composition of the reaction solution comprises copper sulfate and formaldehyde.
8. The method according to claim 1, further comprising a vibration compensation step, wherein the vibration compensation step is provided before the buried oxide layer silicon dioxide release step, and the vibration compensation step comprises:
and constructing a second force-sensitive strain structure on the upper surface of the silicon-on-insulator wafer outside the micro flow channel so as to eliminate errors generated by vibration on fluid pressure measurement.
9. The method according to claim 5, wherein the second passivation layer silicon oxide is removed after the micro flow channel inner wall inorganic copper plating step.
10. Use of a flow-enabled microchannel fabricated according to the method of any one of claims 1-9 for heat dissipation in three-dimensional integrated wafer systems for the fabrication of silicon wafer interposer with vertical through-silicon vias or redistribution layers for three-dimensional vertical stack integration of multi-layer integrated circuit chips or wafers.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116399489A (en) * | 2023-06-09 | 2023-07-07 | 之江实验室 | High-temperature silicon-based photoelectric pressure sensing chip for system-on-chip integration |
| CN116429300A (en) * | 2023-06-12 | 2023-07-14 | 之江实验室 | Ultrahigh temperature pressure sensing chip and system based on monocrystalline silicon and micro-channel cooling |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200426253A (en) * | 2003-05-07 | 2004-12-01 | Microfabrica Inc | Electrochemically fabricated structures having dielectric or active bases and methods of and apparatus for producing such structures |
| CN1649084A (en) * | 2003-12-22 | 2005-08-03 | 索尼株式会社 | Process for producing a movable structure and etchant for silicon oxide film |
| US20080266787A1 (en) * | 2005-12-23 | 2008-10-30 | Laurent Gosset | On-Chip Interconnect-Stack Cooling Using Sacrificial Interconnect Segments |
| WO2012005706A1 (en) * | 2010-07-07 | 2012-01-12 | Haluk Kulah | Cmos compatible microchannel heat sink for electronic cooling and its fabrication |
| CN102539033A (en) * | 2012-03-09 | 2012-07-04 | 上海宏力半导体制造有限公司 | Method for making micro electromechanical system pressure sensor |
| US20140191322A1 (en) * | 2013-01-10 | 2014-07-10 | International Business Machines Corporation | Silicon-on-insulator heat sink |
| CN104003350A (en) * | 2014-05-15 | 2014-08-27 | 北京大学 | Wafer-level vacuum packaging method of bulk silicon resonant pressure transducer |
| CN110739231A (en) * | 2019-09-24 | 2020-01-31 | 杭州臻镭微波技术有限公司 | three-dimensional stacking radio frequency optical module manufacturing method |
| US20200144152A1 (en) * | 2018-11-07 | 2020-05-07 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of manufacturing a cooling circuit |
| CN114199306A (en) * | 2021-12-06 | 2022-03-18 | 西安交通大学 | Composite film sensor for measuring heat flow density and pressure and preparation method thereof |
| WO2022265714A1 (en) * | 2021-06-16 | 2022-12-22 | Intel Corporation | Glass-based cavity and channels for cooling of embedded dies and 3d integrated modules using package substrates with glass core |
-
2023
- 2023-02-03 CN CN202310052799.8A patent/CN115863183B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200426253A (en) * | 2003-05-07 | 2004-12-01 | Microfabrica Inc | Electrochemically fabricated structures having dielectric or active bases and methods of and apparatus for producing such structures |
| CN1649084A (en) * | 2003-12-22 | 2005-08-03 | 索尼株式会社 | Process for producing a movable structure and etchant for silicon oxide film |
| US20080266787A1 (en) * | 2005-12-23 | 2008-10-30 | Laurent Gosset | On-Chip Interconnect-Stack Cooling Using Sacrificial Interconnect Segments |
| WO2012005706A1 (en) * | 2010-07-07 | 2012-01-12 | Haluk Kulah | Cmos compatible microchannel heat sink for electronic cooling and its fabrication |
| CN102539033A (en) * | 2012-03-09 | 2012-07-04 | 上海宏力半导体制造有限公司 | Method for making micro electromechanical system pressure sensor |
| US20140191322A1 (en) * | 2013-01-10 | 2014-07-10 | International Business Machines Corporation | Silicon-on-insulator heat sink |
| CN104003350A (en) * | 2014-05-15 | 2014-08-27 | 北京大学 | Wafer-level vacuum packaging method of bulk silicon resonant pressure transducer |
| US20200144152A1 (en) * | 2018-11-07 | 2020-05-07 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of manufacturing a cooling circuit |
| CN110739231A (en) * | 2019-09-24 | 2020-01-31 | 杭州臻镭微波技术有限公司 | three-dimensional stacking radio frequency optical module manufacturing method |
| WO2022265714A1 (en) * | 2021-06-16 | 2022-12-22 | Intel Corporation | Glass-based cavity and channels for cooling of embedded dies and 3d integrated modules using package substrates with glass core |
| CN114199306A (en) * | 2021-12-06 | 2022-03-18 | 西安交通大学 | Composite film sensor for measuring heat flow density and pressure and preparation method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116399489A (en) * | 2023-06-09 | 2023-07-07 | 之江实验室 | High-temperature silicon-based photoelectric pressure sensing chip for system-on-chip integration |
| CN116399489B (en) * | 2023-06-09 | 2023-09-01 | 之江实验室 | High-temperature silicon-based photoelectric pressure sensing chip for system-on-chip integration |
| CN116429300A (en) * | 2023-06-12 | 2023-07-14 | 之江实验室 | Ultrahigh temperature pressure sensing chip and system based on monocrystalline silicon and micro-channel cooling |
| CN116429300B (en) * | 2023-06-12 | 2023-09-22 | 之江实验室 | Ultrahigh temperature pressure sensing chip and system based on monocrystalline silicon and micro-channel cooling |
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