CN116429300A - Ultrahigh temperature pressure sensing chip and system based on monocrystalline silicon and micro-channel cooling - Google Patents
Ultrahigh temperature pressure sensing chip and system based on monocrystalline silicon and micro-channel cooling Download PDFInfo
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- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00119—Arrangement of basic structures like cavities or channels, e.g. suitable for microfluidic systems
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B81C3/001—Bonding of two components
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- G—PHYSICS
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- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/18—Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/02—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning
- G01L9/06—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning of piezo-resistive devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses an ultra-high temperature pressure sensing chip and system based on monocrystalline silicon and micro-channel cooling, which are characterized in that a method of combining anisotropic corrosion and oxidation at the bottom with etching of a resistor separation structure around a piezoresistive semiconductor resistor and filling and covering of an insulating layer is used for wrapping the semiconductor resistor forming a Wheatstone bridge by using a silicon dioxide layer in an insulating and insulating way, so that the problem of failure of isolating high-temperature leakage current of a traditional monocrystalline silicon pn junction is avoided. The invention also provides a micro-assembly method for surrounding the high-temperature pressure sensing chip by using the micro-flow channel, which isolates the external high temperature and reduces the temperature around the chip, so that the system can work in an ultra-high temperature environment which is higher than the highest working temperature of the silicon-based pressure sensing chip by more than 1000 ℃. Meanwhile, the method for cooling the micro-channel surrounding chip is also suitable for sensors, integrated circuits, high-power devices and the like which are made of other materials and principles and work in extremely high-temperature environments.
Description
Technical Field
The application relates to the technical field of electronics, in particular to an ultrahigh temperature pressure sensing chip and system based on monocrystalline silicon and micro-channel cooling.
Background
Pressure is an important physical quantity, and although the piezoresistive pressure sensor manufactured on the basis of the monocrystalline silicon wafer has the advantages of high sensitivity, good linearity, compatibility with integrated circuit technology and the like, the pn junction isolation structure of monocrystalline silicon can fail due to aggravation of leakage current in a high-temperature environment of more than 120 ℃, and the requirement of the fields of aerospace, petroleum drilling, universe detection and the like on higher working temperature cannot be met. In order to meet the requirement of pressure measurement in a high-temperature environment above 120 ℃, and eliminate the high-temperature leakage current of a monocrystalline silicon pn junction isolation structure, a high-temperature pressure sensing chip based on Silicon On Insulator (SOI) has been developed, namely, silicon oxide buried oxide layer of an SOI wafer is used for isolating a monocrystalline silicon resistor from a substrate silicon. However, SOI wafers are expensive and limit the large-scale application of high temperature pressure sensors in modern industry. Furthermore, while heavily doped single crystal silicon materials can maintain good mechanical properties and resistivity at 600 ℃, single crystal silicon materials will suffer from degradation of mechanical and electrical properties at higher temperatures, also limiting the maximum operating temperature of silicon-based pressure sensors, including SOI.
Disclosure of Invention
In order to replace an expensive SOI wafer with a monocrystalline silicon wafer, solve the problem of pn junction isolation high-temperature failure of the monocrystalline silicon wafer and overcome the problem of degradation of mechanical properties and electrical properties of monocrystalline silicon materials at 600 ℃, the embodiment of the application aims to provide an ultrahigh-temperature pressure sensing chip and an ultrahigh-temperature pressure sensing system based on cooling of monocrystalline silicon and micro-channels, which not only make the pressure sensing chip capable of working in a high-temperature environment of more than 120 ℃ by using a general monocrystalline silicon wafer, but also can work in an ultrahigh-temperature environment higher than the highest working temperature of the chip under the effect of surrounding cooling of the micro-channels.
According to a first aspect of embodiments of the present application, there is provided an ultra-high temperature pressure sensing chip based on monocrystalline silicon and micro-channel cooling, the preparation process of the ultra-high temperature pressure sensing chip includes:
(1) Etching the lower surface of the monocrystalline silicon wafer to form a silicon cavity structure, and oxidizing the inner wall of the silicon cavity structure to form a silicon dioxide layer;
(2) Photoetching and etching the upper surface corrosion barrier layer and the silicon layer below the upper surface corrosion barrier layer to form a resistor separation structure;
(3) Manufacturing piezoresistive semiconductor resistors on the upper surface of a wafer, and arranging the piezoresistive semiconductor resistors side by side to form a Wheatstone bridge structure;
(4) A passivation layer grows in the gap of the resistor separation structure and on the upper surface of the semiconductor resistor bridge;
(5) Heavily doping the ohmic contact area of the semiconductor resistor bridge and manufacturing a high-temperature-resistant composite metal lead interconnection structure with an adhesion layer, a thermal diffusion barrier layer and a conductive layer;
(6) Etching a first deep groove on the lower surface of a monocrystalline silicon wafer to form a pressure sensing diaphragm with the first deep groove on the lower surface, and etching a corresponding second deep groove on a substrate;
(7) The pressure sensitive membrane is bonded with the substrate to form a vacuum reference cavity and a micro-channel closed pipeline, so that the pressure sensing chip is manufactured.
Further, step (1) includes:
respectively growing an upper surface corrosion barrier layer and a lower surface corrosion barrier layer on the upper surface and the lower surface of the monocrystalline silicon wafer;
photoetching the lower surface corrosion barrier layer on the lower surface of the monocrystalline silicon wafer to expose a silicon substrate window on the lower surface;
etching monocrystalline silicon in the silicon substrate window by a wet chemical method along the depth direction by taking the etching barrier layer on the upper surface of the wafer and the etching barrier layer outside the lower surface silicon substrate window as masks to form a C-shaped silicon cavity;
and oxidizing the silicon exposed from the inner wall of the C-shaped silicon cavity by using a dry oxygen oxidation method to form a silicon cavity silicon dioxide layer.
Further, the step (2) specifically comprises:
and coating photoresist on the lower surface of the monocrystalline silicon wafer by using a photoresist spraying method or a photoresist throwing method which is alternately performed by spin coating and drying for multiple times, photoetching and etching the upper surface corrosion barrier layer and the silicon layer below the upper surface corrosion barrier layer until the silicon dioxide layer is exposed, so as to form a resistor separation structure.
Further, step (3) includes:
removing the upper surface corrosion barrier layer and the lower surface corrosion barrier layer, coating photoresist on the lower surface of the monocrystalline silicon wafer for protection by using a photoresist spraying method or a photoresist throwing method which is alternately performed by spin coating and drying for multiple times, and photoetching the shape of the semiconductor resistor on the upper surface of the monocrystalline silicon wafer; etching monocrystalline silicon by taking the photoresist with the shape of the semiconductor resistor as a mask;
and p-type ion implantation is carried out on the monocrystalline silicon wafer by taking the photoresist in the shape of the semiconductor resistor as a mask, photoresist is removed, and annealing is carried out to form the semiconductor resistor, wherein each semiconductor resistor is distributed on the outer surface of the silicon cavity structure and is distributed to form a Wheatstone bridge structure.
Further, step (4) includes:
dry-oxygen oxidation, namely generating a silicon dioxide thin layer of 30-100 nm on the surfaces of the monocrystalline silicon wafer and the resistor separation structure;
generating a silicon dioxide layer with the thickness of 500 nm-2 mu m on the surface of the monocrystalline silicon wafer and the resistor separation structure by using low-pressure chemical vapor deposition for insulating filling and covering;
and depositing a silicon nitride layer with the passivation function of 50-200 nm.
Further, prior to depositing the silicon nitride layer, one or more of plasma enhanced chemical vapor deposited silicon dioxide, low pressure chemical vapor deposited polysilicon, and the like is used to continue depositing a thick film on the wafer upper surface and to form a planar and insulating upper surface using chemical mechanical polishing, depending on the performance requirements of the pressure sensor.
Further, step (5) includes:
photoetching and etching a passivation layer above the ohmic contact area of the semiconductor resistor to form an ohmic contact window;
carrying out heavy doping ion implantation and annealing on the silicon in the ohmic contact window;
and manufacturing the high-temperature-resistant composite metal lead interconnection structure on the upper surfaces of the ohmic contact window and the passivation layer by using a sputtering method.
Further, in the step (6), before the first deep groove is etched on the lower surface of the monocrystalline silicon wafer, photoresist is coated on the lower surface of the monocrystalline silicon wafer by a photoresist spraying method or a photoresist throwing method in which spin coating and drying are alternately performed for a plurality of times.
Further, step (7) includes:
vacuum bonding is carried out on the pressure sensitive membrane and the substrate, and the vacuum bonding method is selected from silicon-silicon bonding, high-temperature-resistant glass-based anode bonding, glass solder bonding, metal hot-pressing bonding, transient liquid phase bonding and BCB bonding;
after bonding, a closed pipeline of the micro-channel in the vacuum reference cavity and the ultra-high temperature pressure sensing chip is formed and is connected with the micro-channel in the shell micro-channel, the micro-channel in the low temperature co-fired ceramic adapter plate and an external micro-pump cooler to form a surrounding micro-channel cooling packaging structure which is distributed around the chip and can drive cooling liquid to circulate.
According to a second aspect of the embodiments of the present application, an ultra-high temperature pressure sensing system based on a surrounding micro-channel cooling package is provided, and based on the above monolithic integrated structure based on an ultra-high temperature pressure sensing chip, a silicon-based pressure sensing chip or other high temperature pressure sensing chip and an integrated circuit chip, the ultra-high temperature pressure sensing system is obtained by adopting wire bonding and hydraulic conduction packaging or leadless flip packaging.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
firstly, the invention uses the method of combining the anisotropic corrosion and oxidation of the bottom and the etching of the insulating isolation groove around the force sensitive resistor and the filling and covering of the insulating layer to wrap the force sensitive resistor forming the Wheatstone bridge by using the silicon dioxide layer insulating isolation, thereby avoiding the problem of failure of the traditional monocrystalline silicon pn junction isolation high-temperature leakage current and realizing the manufacturing of the pressure sensing chip working in the high-temperature environment above 120 ℃ by using the monocrystalline silicon wafer instead of the expensive SOI wafer;
secondly, the invention provides a micro-assembly method for surrounding the high-temperature pressure sensing chip by using the micro-flow channel, wherein the cooling liquid micro-flow channel formed by the chip micro-flow channel and the tube shell micro-flow channel isolates the external high temperature and reduces the temperature around the chip, so that the system can work in an ultra-high temperature environment which is higher than the highest working temperature of the silicon-based pressure sensing chip by more than 1000 ℃.
Thirdly, the leadless flip-chip packaged ultrahigh temperature pressure sensing system provided by the invention completes vacuum sealing of the pressure sensor based on the sealing ring and electrical signal extraction based on the silicon through hole in one bonding process, thereby not only improving the reliability of electrical connection, but also being completely compatible with a silicon-based CMOS process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a flow chart of a process for manufacturing an ultra-high temperature pressure sensing chip based on single crystal silicon and micro flow channels according to an exemplary embodiment, wherein (a) in fig. 1- (l) in fig. 1 are schematic structural diagrams of each flow in the manufacturing process;
FIG. 2 is a schematic diagram showing a chip micro-channel extraction mode of two pressure sensing chips according to the present invention;
FIG. 3 is a schematic diagram of an ultra-high temperature pressure sensing system employing wire bonding and hydraulic conduction packaging;
FIG. 4 is a schematic diagram of an ultra-high temperature pressure sensing system employing leadless flip-chip packaging;
FIG. 5 is a schematic diagram of monolithic integration using a silicon-based pressure sensing chip or other high temperature pressure sensing chip and integrated circuit chip.
Reference numerals: 1. a monocrystalline silicon wafer; 2. an upper surface corrosion barrier layer; 3. a lower surface corrosion barrier layer; 4. a C-type silicon cavity; 5. a silicon dioxide layer; 6. a resistor separation structure; 7. a semiconductor resistor-shaped photoresist; 8. a semiconductor resistor; 9. a passivation layer; 10. a lead interconnection structure; 11. a first deep groove; 12. a microchannel; 13. a cooling liquid inlet; 14. a cooling liquid outlet; 15. bonding a substrate; 16. a vacuum reference chamber; 17. a pressure sensitive membrane; 18. diaphragm seal ring; 19. bonding a substrate; 20. TSV; 21. tin micro-bumps; 22. a substrate seal ring; 23. a tin seal ring; 24. a temperature sensor; 25. a pressure sensing chip; 26. a hydraulic medium; 27. a pressure-sensitive metal film; 28. an inner metal shell; 29. binding posts; 30. an electrical instrument; 31. an outer metal shell; 32. a shell microchannel; 33. a micropump cooler; 34. a hole; 35. a low-temperature co-fired ceramic adapter plate; 36. high-temperature sealant; 37. an integrated circuit chip.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
Fig. 1 is a flowchart illustrating a process for manufacturing an ultra-high temperature pressure sensing chip based on single crystal silicon and micro flow channels according to an exemplary embodiment, and as shown in fig. 1, the chip is manufactured using an N (100) -type double-sided polished single crystal silicon wafer 1 as a material ((a) of fig. 1), and may include the steps of:
(1) And a silicon cavity manufacturing step: etching the lower surface of the monocrystalline silicon wafer to form a silicon cavity structure, and oxidizing the inner wall of the silicon cavity structure to form a compact silicon dioxide layer;
(2) And manufacturing the resistor separation structure: photoetching and etching the upper surface corrosion barrier layer 2 and a silicon layer below the upper surface corrosion barrier layer to form a resistor separation structure;
(3) Semiconductor resistor bridge manufacturing steps: manufacturing piezoresistive semiconductor resistors on the upper surface of a wafer, and arranging the piezoresistive semiconductor resistors side by side to form a Wheatstone bridge structure;
(4) And a passivation layer manufacturing step: a passivation layer grows in the gap of the resistor separation structure and on the upper surface of the semiconductor resistor bridge;
(5) The manufacturing steps of the metallization structure comprise: heavily doping the ohmic contact area of the semiconductor resistor bridge and manufacturing a high-temperature-resistant composite metal lead interconnection structure with an adhesion layer, a thermal diffusion barrier layer and a conductive layer;
(6) And manufacturing a deep groove of the micro-channel: etching a deep groove on the lower surface of a monocrystalline silicon wafer to form a pressure sensing diaphragm with the deep groove on the lower surface, and etching a corresponding deep groove on a substrate;
(7) And a bonding step: the pressure sensitive membrane is bonded with the substrate to form a vacuum reference cavity and a micro-channel closed pipeline, so that the pressure sensing chip is manufactured.
In the specific implementation of the silicon cavity manufacturing step (1), the lower surface of the monocrystalline silicon wafer 1 is corroded to form a silicon cavity structure, and the inner wall of the silicon cavity structure is oxidized to form a compact silicon dioxide layer 5; the method comprises the following steps:
(1.1) growing an upper surface corrosion barrier layer 2 and a lower surface corrosion barrier layer 3 on the upper and lower surfaces of the single crystal silicon wafer 1, respectively (b) in fig. 1; the upper surface corrosion barrier layer 2 and the lower surface corrosion barrier layer 3 are preferably silicon dioxide/silicon nitride deposited by Low Pressure Chemical Vapor Deposition (LPCVD);
(1.2) photoetching the lower surface corrosion barrier layer 3 on the lower surface of the monocrystalline silicon wafer 1 to expose a lower surface silicon substrate window;
(1.3) wet-chemical etching is carried out on monocrystalline silicon in the silicon substrate window along the depth direction by taking the corrosion barrier layer on the upper surface of the wafer and the corrosion barrier layer outside the lower surface silicon substrate window as masks to form a C-shaped silicon cavity 4 (C) in fig. 1, wherein the wet-chemical etching liquid preferably comprises TMAH (tetramethylammonium hydroxide) solution which has selectivity to the crystal direction and has uniform and easily controlled etching rate;
(1.4) oxidizing the silicon exposed from the inner wall of the C-type silicon cavity 4 by dry oxygen oxidation to form a dense silicon cavity silicon dioxide layer 5 ((d) in fig. 1).
In the specific implementation of the resistor separation structure manufacturing step (2), photoetching and etching the upper surface corrosion barrier layer (2) and a silicon layer below the upper surface corrosion barrier layer to form a resistor separation structure; the method comprises the following steps:
coating photoresist on the lower surface of the monocrystalline silicon wafer 1 by using a photoresist spraying method or a photoresist throwing method which is performed by alternately carrying out spin coating and drying for multiple times, photoetching and etching the upper surface corrosion barrier layer 2 and a silicon layer below the upper surface corrosion barrier layer until the silicon cavity silicon dioxide layer 5 is exposed, forming a resistor separation structure 6 ((e) in fig. 1), and removing the photoresist; the method for etching the silicon on the upper surface of the monocrystalline silicon wafer 1 can be dry etching or wet etching by using a tetramethylammonium hydroxide solution, wherein the etching progress is required to be accurately controlled, and the method has the advantage of self-stopping. The side surfaces of the semiconductor resistor are separated by the resistor separation structure, and the bottom is separated by the silicon dioxide layer, so that the insulation between the semiconductor resistor and the silicon dioxide layer is realized;
in the implementation of the semiconductor resistor bridge manufacturing step (3), piezoresistance type semiconductor resistors are manufactured on the upper surface of the wafer, and are distributed side by side to form a Wheatstone bridge structure; the method comprises the following steps:
(3.1) removing the upper surface corrosion barrier layer 2 and the lower surface corrosion barrier layer 3, coating photoresist on the lower surface of the monocrystalline silicon wafer 1 by using a photoresist spraying method or a photoresist throwing method which is alternately performed by spin coating and drying for a plurality of times to protect the lower surface, and photoetching the upper surface of the monocrystalline silicon wafer 1 to form the shape of a semiconductor resistor; monocrystalline silicon is etched using the semiconductor resistor-shaped photoresist 7 as a mask, the remaining thickness of the monocrystalline silicon layer being typically less than 1 micron, typically 1 micron (fig. 1 (f)).
(3.2) p-type ion implantation of the monocrystalline silicon wafer 1 with the resist 7 in the shape of a semiconductor resistor as a mask, photoresist removal and annealing to form a semiconductor resistor 8 (fig. 1 (g)), the doping concentration of the annealed semiconductor resistor preferably being higher than 3e18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The formed semiconductor resistors are distributed on the outer surface of the silicon cavity structure and are distributed to form a Wheatstone bridge structure.
In a specific implementation of the passivation layer manufacturing step (4), a passivation layer 9 is grown in the gaps of the resistor separation structures 6 and on the upper surface of the semiconductor resistor bridge;
specifically, a passivation layer 9 is grown on the upper surface of the single crystal silicon wafer 1 ((h) in fig. 1). The passivation layer 9 has the main functions of insulation, passivation and range adjustment, and the preferred process is that firstly, dry oxygen oxidation is carried out to generate a compact silicon dioxide thin layer (30-100 nm) on the surfaces of the monocrystalline silicon wafer 1 and the resistor separation structure 6; then, a compact and thicker silicon dioxide layer (500 nm-2 μm) is generated on the surfaces of the monocrystalline silicon wafer 1 and the resistor separation structure 6 by Low Pressure Chemical Vapor Deposition (LPCVD) for insulating filling and covering; then, according to the performance requirements of the pressure sensor such as the measuring range, the sensitivity and the like, one or more methods of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon dioxide, LPCVD polysilicon and the like can be continuously used for continuously depositing a thick film on the upper surface of the wafer, and a flat and insulated upper surface is formed by using a chemical mechanical polishing method; and finally, depositing a silicon nitride layer with a passivation effect of 50-200 nm.
In the specific implementation of the metallization structure manufacturing step (5), heavily doping is performed on the ohmic contact region of the semiconductor resistor bridge and the high-temperature-resistant composite metal lead interconnection structure 10 with an adhesion layer, a thermal diffusion barrier layer and a conductive layer is manufactured;
specifically, the passivation layer 9 above the ohmic contact region of the semiconductor resistor 8 is subjected to photoetching and etching to form an ohmic contact window; then, heavily doped ions are implanted and annealed; then, a high temperature resistant composite metal lead interconnection structure 10 having an adhesive layer, a thermal diffusion barrier layer, and a conductive layer is manufactured by sputtering on the upper surface of the passivation layer 9 and the ohmic contact region. The adhesion layer material is preferably titanium or chromium, the thermal diffusion barrier material is preferably titanium nitride or tantalum nitride or tungsten titanium or platinum, and the conductive layer material is preferably gold or silver or copper.
In the specific implementation of the deep groove manufacturing step (6) of the micro-channel, a first deep groove 11 is etched on the lower surface of the monocrystalline silicon wafer, a pressure sensing diaphragm with the first deep groove 11 on the lower surface is formed, and a corresponding second deep groove is etched on the substrate;
specifically, photoresist is coated on the lower surface of the monocrystalline silicon wafer 1 by a photoresist spraying method or a spin coating method in which spin coating and drying are alternately performed a plurality of times, and the first deep groove 11 is etched and photoetched on the lower surface of the monocrystalline silicon wafer 1, thereby completing the manufacture of the pressure sensitive membrane 17 ((j) in fig. 1).
In the specific implementation of the bonding step (7), bonding the pressure sensitive membrane and the substrate to form a vacuum reference cavity and a micro-channel closed pipeline, so as to manufacture a pressure sensing chip;
specifically, a second deep groove corresponding to the first deep groove 11, a cooling liquid water inlet 13 and a cooling liquid water outlet 14 are etched on a bonding substrate 15; the bonded substrate 15 is vacuum bonded to the single crystal silicon wafer 1 to form a closed chip microchannel 12 and a vacuum reference chamber 16 ((k) in fig. 1), a schematic top view of which is shown in fig. 1 (l). Methods of vacuum bonding include, but are not limited to, silicon-silicon bonding, high temperature glass-based anodic bonding, glass solder bonding, metal thermocompression bonding, transient liquid phase bonding, BCB bonding, and the like. After bonding, a closed pipeline of the micro-flow channel in the vacuum reference cavity 16 and the ultra-high temperature pressure sensing chip is formed and is connected with the micro-flow channel in the tube shell micro-flow channel 32, the micro-flow channel in the low temperature co-fired ceramic adapter plate 35 and the external micro-pump cooler 33 to form a surrounding micro-flow channel cooling packaging structure which is distributed around the chip and can drive cooling liquid to circulate.
In the pressure sensing chip completed according to the above steps, the periphery and upper surface of each semiconductor resistor 8 constituting the wheatstone bridge are filled with silicon dioxide/polysilicon/silicon nitride covered with the passivation layer 9, and the lower surface has the membrane silicon dioxide layer 5, so that each semiconductor resistor 8 is insulated from each other, and there is no problem of high temperature leakage current failure. And p-type is higher than 3E18 cm due to the semiconductor resistance -3 And thus intrinsic excitation is suppressed in a high temperature environment, a positive temperature coefficient can be maintained. In addition, the high temperature resistant composite metal lead interconnection structure ensures the high temperature reliability of the metal-semiconductor contact. Therefore, the high-temperature pressure sensing chip provided by the invention can achieve the same high-temperature working capacity by using a common and low-cost monocrystalline silicon wafer under the condition of not depending on an SOI wafer. The micro-flow channel embedded with the pressure sensing chip can radiate heat of the chip, so that the chip can work in an external environment with higher temperature.
Fig. 2 (a) shows a lead-out mode of the chip micro flow channel 12 when the lower surface of the pressure sensitive membrane 17 is bonded to the substrate 15. Fig. 2 (b) shows the way in which the micro flow channel 12 is led out when the upper surface of the pressure sensitive membrane 17 is bonded to the substrate 19 with TSV and sealing ring (i.e. leadless flip-chip package structure). During bonding, bonding pad 10 of pressure sensitive diaphragm 17 is aligned with tin micro bump 21 on TSV 20, and diaphragm seal ring 18 of pressure sensitive diaphragm is aligned with tin seal ring 23 on substrate seal ring 22.
The present application provides an ultra-high temperature pressure sensing system based on a surrounding micro-fluidic channel cooling package, and FIG. 3 shows an embodiment of an ultra-high temperature pressure sensing system employing wire bonding and hydraulic conduction packaging; FIG. 4 illustrates an embodiment of an ultra-high temperature pressure sensing system employing leadless flip-chip packaging; fig. 5 illustrates a monolithically integrated embodiment employing a silicon-based pressure sensing die or other high temperature pressure sensing die (e.g., such as SOI, sapphire, silicon carbide, etc. pressure sensing die) and an integrated circuit die.
As shown in fig. 3, in the embodiment of the ultra-high temperature pressure sensing system employing wire bonding and hydraulic conduction packaging, the temperature sensor 24 is monolithically integrated on the pressure sensing chip 25 and is sealed in the inner metal tube shell 28 with the pressure sensing metal film 27 by the hydraulic medium 26, and the signal is led out by connecting the bonding pad 10 with the binding post 29 by wire bonding and leading out to the outside and accessing the electric instrument 30. The inner metal shell 28 is disposed in an outer metal shell 31, and the outer metal shell 31 contains shell micro-channels 32 for cooling fluid to flow and is distributed around the pressure sensing die 25. The cartridge microchannel 32 is connected to an external micropump cooler 33.
As shown in fig. 4, in the embodiment of the ultra-high temperature pressure sensing system employing leadless flip-chip packaging, the temperature sensor 24 is monolithically integrated on the pressure sensing chip 25, flip-chip bonded on the low temperature co-fired ceramic interposer 35, and flip-chip bonded on the inner metal shell 28. The signal is led out by flip-chip bonding the bonding pad 10 with the bonding pad of the low-temperature co-fired ceramic adapter plate 35 and the inner metal tube shell 28, and led out to the outside to be connected with the electric instrument 30. The inner metal shell 28 is placed in the outer metal shell 31, and the outside of the pressure sensor chip 25 and the inside of the outer metal shell 31 are sealed and fixed using a high-temperature sealant 36. The outer metal shell 31 contains shell micro-channels 32 for cooling liquid to flow and is distributed around the pressure sensing chip 25. The cartridge microchannel 32 is connected to an external micropump cooler 33.
In a monolithically integrated embodiment employing a silicon-based pressure sensing die or other high temperature pressure sensing die and integrated circuit die, the integrated circuit die 37 with integrated temperature sensor and pressure sensing die 25 are flip-chip bonded together on a low temperature co-fired ceramic interposer 35 and then on an inner metal package 28, as shown in fig. 5. The signal is led out by flip-chip bonding the bonding pad 10 with the bonding pad of the low-temperature co-fired ceramic adapter plate 35 and the inner metal tube shell 28, and led out to the outside to be connected with the electric instrument 30. The inner metal shell 28 is placed in the outer metal shell 31, and the outside of the pressure sensor chip 25 and the inside of the outer metal shell 31 are sealed and fixed using a high-temperature sealant 36. The outer metal shell 31 contains shell micro-channels 32 for cooling liquid to flow and is distributed around the pressure sensing chip 25. The cartridge microchannel 32 is connected to an external micropump cooler 33. The low-temperature co-fired ceramic adapter plate 35 is provided with a micro-channel and is connected with the shell micro-channel 32.
The ultra-high temperature pressure sensing system based on the surrounding micro flow channel cooling package operates on the principle that external pressure is conducted to the pressure sensing chip through the holes 34, but the micro flow channel surrounding the chip provides the effect of isolating the external temperature and reducing the temperature surrounding the chip. The temperature sensor 24 near the pressure sensing chip 25 can monitor the ambient temperature in real time and control the circulation power of the cooling liquid in the micro-pump cooler 33 driving the micro-channel, so that the pressure sensing chip surrounded by the micro-channel can work in a relatively stable temperature lower than the external environment no matter how the external environment changes, thereby forming real-time closed-loop temperature control. Therefore, the system can work in an ultra-high temperature environment which is higher than the maximum working temperature of the silicon-based pressure sensing chip by more than 1000 ℃.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof.
Claims (10)
1. The ultra-high temperature pressure sensing chip based on monocrystalline silicon and micro-channel cooling is characterized in that the preparation process of the ultra-high temperature pressure sensing chip comprises the following steps:
(1) Etching the lower surface of the monocrystalline silicon wafer to form a silicon cavity structure, and oxidizing the inner wall of the silicon cavity structure to form a silicon dioxide layer;
(2) Photoetching and etching the upper surface corrosion barrier layer and the silicon layer below the upper surface corrosion barrier layer to form a resistor separation structure;
(3) Manufacturing piezoresistive semiconductor resistors on the upper surface of a wafer, and arranging the piezoresistive semiconductor resistors side by side to form a Wheatstone bridge structure;
(4) A passivation layer grows in the gap of the resistor separation structure and on the upper surface of the semiconductor resistor bridge;
(5) Heavily doping the ohmic contact area of the semiconductor resistor bridge and manufacturing a high-temperature-resistant composite metal lead interconnection structure with an adhesion layer, a thermal diffusion barrier layer and a conductive layer;
(6) Etching a first deep groove on the lower surface of a monocrystalline silicon wafer to form a pressure sensing diaphragm with the first deep groove on the lower surface, and etching a corresponding second deep groove on a substrate;
(7) The pressure sensitive membrane is bonded with the substrate to form a vacuum reference cavity and a micro-channel closed pipeline, so that the pressure sensing chip is manufactured.
2. The ultra-high temperature pressure sensing chip of claim 1, wherein step (1) comprises:
respectively growing an upper surface corrosion barrier layer and a lower surface corrosion barrier layer on the upper surface and the lower surface of the monocrystalline silicon wafer;
photoetching the lower surface corrosion barrier layer on the lower surface of the monocrystalline silicon wafer to expose a silicon substrate window on the lower surface;
etching monocrystalline silicon in the silicon substrate window by a wet chemical method along the depth direction by taking the etching barrier layer on the upper surface of the wafer and the etching barrier layer outside the lower surface silicon substrate window as masks to form a C-shaped silicon cavity;
and oxidizing the silicon exposed from the inner wall of the C-shaped silicon cavity by using a dry oxygen oxidation method to form a silicon cavity silicon dioxide layer.
3. The ultra-high temperature pressure sensing chip of claim 1, wherein step (2) specifically comprises:
and coating photoresist on the lower surface of the monocrystalline silicon wafer by using a photoresist spraying method or a photoresist throwing method which is alternately performed by spin coating and drying for multiple times, photoetching and etching the upper surface corrosion barrier layer and the silicon layer below the upper surface corrosion barrier layer until the silicon dioxide layer is exposed, so as to form a resistor separation structure.
4. The ultra-high temperature pressure sensing chip of claim 1, wherein step (3) comprises:
removing the upper surface corrosion barrier layer and the lower surface corrosion barrier layer, coating photoresist on the lower surface of the monocrystalline silicon wafer for protection by using a photoresist spraying method or a photoresist throwing method which is alternately performed by spin coating and drying for multiple times, and photoetching the shape of the semiconductor resistor on the upper surface of the monocrystalline silicon wafer; etching monocrystalline silicon by taking the photoresist with the shape of the semiconductor resistor as a mask;
and p-type ion implantation is carried out on the monocrystalline silicon wafer by taking the photoresist in the shape of the semiconductor resistor as a mask, photoresist is removed, and annealing is carried out to form the semiconductor resistor, wherein each semiconductor resistor is distributed on the outer surface of the silicon cavity structure and is distributed to form a Wheatstone bridge structure.
5. The ultra-high temperature pressure sensing chip of claim 1, wherein step (4) comprises:
dry-oxygen oxidation, namely generating a silicon dioxide thin layer of 30-100 nm on the surfaces of the monocrystalline silicon wafer and the resistor separation structure;
generating a silicon dioxide layer with the thickness of 500 nm-2 mu m on the surface of the monocrystalline silicon wafer and the resistor separation structure by using low-pressure chemical vapor deposition for insulating filling and covering;
and depositing a silicon nitride layer with the passivation function of 50-200 nm.
6. The ultra-high temperature pressure sensor chip of claim 5, wherein prior to depositing the silicon nitride layer, one or more of plasma enhanced chemical vapor deposited silicon dioxide, low pressure chemical vapor deposited polysilicon is used to continue depositing a thick film on the wafer upper surface and chemical mechanical polishing is used to form a flat and insulating upper surface, depending on the performance requirements of the pressure sensor.
7. The ultra-high temperature pressure sensing chip of claim 1, wherein step (5) comprises:
photoetching and etching a passivation layer above the ohmic contact area of the semiconductor resistor to form an ohmic contact window;
carrying out heavy doping ion implantation and annealing on the silicon in the ohmic contact window;
and manufacturing the high-temperature-resistant composite metal lead interconnection structure on the upper surfaces of the ohmic contact window and the passivation layer by using a sputtering method.
8. The ultra-high temperature pressure sensing chip of claim 1, wherein in the step (6), before the first deep groove is etched on the lower surface of the monocrystalline silicon wafer, photoresist is coated on the lower surface of the monocrystalline silicon wafer by a photoresist spraying method or a photoresist throwing method in which spin coating and drying are alternately performed for a plurality of times.
9. The ultra-high temperature pressure sensing chip of claim 1, wherein step (7) comprises:
vacuum bonding is carried out on the pressure sensitive membrane and the substrate, and the vacuum bonding method is selected from silicon-silicon bonding, high-temperature-resistant glass-based anode bonding, glass solder bonding, metal hot-pressing bonding, transient liquid phase bonding and BCB bonding;
after bonding, a closed pipeline of the micro-channel in the vacuum reference cavity and the ultra-high temperature pressure sensing chip is formed and is connected with the micro-channel in the shell micro-channel, the micro-channel in the low temperature co-fired ceramic adapter plate and an external micro-pump cooler to form a surrounding micro-channel cooling packaging structure which is distributed around the chip and can drive cooling liquid to circulate.
10. An ultra-high temperature pressure sensing system based on surrounding micro-channel cooling packaging is characterized in that the ultra-high temperature pressure sensing system is based on a monolithic integrated structure based on an ultra-high temperature pressure sensing chip, a silicon-based pressure sensing chip or other high temperature pressure sensing chips and integrated circuit chips, and is obtained by adopting wire bonding and hydraulic conduction packaging or leadless flip packaging.
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