CN115842040A - SiC power device terminal structure with N-type equipotential rings - Google Patents

Abstract

The invention discloses a SiC power device terminal structure with N-type equipotential rings, which comprises a substrate, wherein the substrate is arranged on a drain metal layer, a drift layer is arranged on the substrate, a source region, a transition region and a terminal region are sequentially arranged on the drift layer from the center to the edge, a first ohmic contact metal of a cell structure of the active region, a second ohmic contact metal of the transition region and a third ohmic contact metal of the terminal region are all electrically communicated with a source electrode of the active region, and a gate runway electrode of the transition region is electrically communicated with a gate electrode of the active region. The invention does not need additional process steps and has good compatibility with different cellular structures and terminal structures.

Description

SiC power device terminal structure with N-type equipotential rings

Technical Field

The invention belongs to the technical field of SiC power devices, and particularly relates to a terminal structure of a SiC power device with N-type equipotential rings.

Background

Compared with Si material, the 4H-SiC material has the following main advantages in power device application: the forbidden band width is large, the forbidden band width of 4H-SiC is 2.9 times of that of Si, and the maximum working temperature and the radiation resistance of the device are far higher than those of a Si-based device; the critical breakdown field intensity is high, the critical breakdown field intensity of the SiC material is about 10 times of that of Si, and the on-resistance of a drift region of a power device is small on the premise of meeting the voltage requirement; the electronic saturation velocity is high, the electronic saturation velocity of SiC is twice that of Si, the starting and the shutdown processes of the SiC device can be completed more quickly, and the SiC device is more suitable for high-frequency application; the heat conductivity of SiC is 3.3 times that of Si, so that the SiC-based power device has better heat dissipation, and can effectively reduce heat dissipation devices of a power electronic system, thereby further realizing the miniaturization of the system. In addition, the technological process of the SiC power device is good in compatibility of the Si-based device, so that the SiC power device is a powerful substitute for the Si-based power device in the advanced scientific and technological fields of rail transit, new energy automobiles, photovoltaic inverters, renewable energy power generation, military industry, national defense and the like.

The power device is usually manufactured by a process of connecting a plurality of cell structures in parallel on a semiconductor wafer, the surface voltages of the cell structures in an active area are approximately the same, but the voltages between a terminal (outermost end) and a substrate are greatly different, so measures are required to reduce the surface electric field and improve the breakdown voltage. This technique is referred to as junction termination. The junction termination technology is characterized in that an extension structure is arranged at the edge of an active region, a main junction depletion region is widened outwards to improve the voltage-resistant level of a device, and a grid electrode of a power device is prevented from being broken down, so that the purpose of protecting a chip device is achieved.

In the preparation process of the silicon carbide power device terminal, due to the existence of a longer transition region, the reasonable method is to add an equipotential ring in front of the field ring and clamp the front end of the field ring to the zero potential of the source electrode through ohmic contact. However, the equipotential ring injection region that is mainstream at present is P-type doped, and the ohmic contact quality of the P-type doped is not as good as that of the N-type doped for the silicon carbide process, and the added equipotential ring also introduces extra drain-source capacitance in the terminal region.

Disclosure of Invention

The invention aims to solve the technical problems that in order to overcome the defects in the prior art, the terminal structure of the SiC power device with the N-type equipotential rings is provided, and the technical problems that the ohmic contact quality is poor and the drain-source capacitance of a terminal area is increased are solved.

The invention adopts the following technical scheme:

a SiC power device terminal structure with N-type equipotential rings comprises a substrate, wherein the substrate is arranged on a drain metal layer, a drift layer is arranged on the substrate, a source region, a transition region and a terminal region are sequentially arranged on the drift layer from the center to the edge, a first ohmic contact metal of a cellular structure of the active region, a second ohmic contact metal of the transition region and a third ohmic contact metal of the terminal region are all in electrical communication with a source electrode of the active region, and a gate track electrode of the transition region is in electrical communication with a gate electrode of the active region;

the transition region sequentially comprises a drain electrode, an N + substrate and an N-type drift region from bottom to top, the N-type drift region sequentially comprises an oxide layer and polycrystalline silicon of adjacent cell structures, a P-region and an N + region of adjacent cells from the center to two ends, a second ohmic contact metal and a P + main ring, and a field oxide layer, a grid runway, grid runway metal and a passivation layer are arranged on the P + main ring.

Specifically, the cellular structure is a silicon carbide MOSFET or a silicon carbide IGBT.

Further, when the cellular structure is a silicon carbide MOSFET, the cellular structure sequentially comprises a drain electrode, an N + substrate, an N type drift region, a P region, an N + region, a P + region, an oxide layer, polycrystalline silicon and first ohmic contact metal from bottom to top.

Specifically, the primitive cell structure is hexagonal, bar-shaped or rectangular.

Specifically, the substrate is a first conductivity type silicon carbide substrate, and the drift layer is a first conductivity type.

Specifically, the gate track and the second ohmic contact metal are isolated by a passivation layer.

Specifically, the polysilicon of the gate track and the polysilicon gate of the active region are formed simultaneously and connected through a polysilicon bridge.

Further, the second ohmic contact metal covers the P + region, the N + region/P + region, or the N + region of the cell structure.

Specifically, the terminal area comprises a P area, the P area is connected with a P + main ring of the transition area, an N + area, a third ohmic contact metal and a P + ring are arranged above the P area, and a field oxide layer, an N + stop ring and a passivation layer are arranged above the P + ring.

Specifically, the termination region is a JTE structure or a field limiting ring structure.

Compared with the prior art, the invention at least has the following beneficial effects:

when the SiC power device terminal structure is used for voltage resistance, because the length of a P + main ring in a transition region reaches dozens of micrometers, and the corner part of a chip even reaches about one hundred micrometers, potential difference possibly exists on two sides (an active region side and a field ring side) of the P + main ring, so that the electric field distribution of the terminal part is influenced, the breakdown voltage of the device is reduced, and the blocking characteristic is poor. In view of the above effect, it is a common practice to open a window on the passivation layer at the end of the P + main ring, connect to the source metal of the device through an ohmic contact process, and clamp it to zero potential, which will effectively improve the blocking characteristic and reliability of the device. However, the P-type ohmic contact process of the SiC material is unstable compared to the N-type ohmic contact process, which results in relatively larger contact resistance and poorer ohmic contact quality. In view of this problem, the present invention additionally performs a P-and N + implantation at the end of the P + main ring (field ring side) based on the above design, and connects the N + ring to the source metal through ohmic contact, so that it is clamped to zero potential, called N + equipotential ring. Because N type ohmic contact technology quality is higher, the contact resistance difference in each region of equipotential ring is less, makes the electric field distribution of device terminal part more even, blocks the characteristic more stable, and the reliability is better.

Furthermore, no extra process flow is needed to be added to the N + equipotential ring, and the injection parameters of the N + equipotential ring and the ohmic contact process parameters are consistent with the manufacturing process of the active region part of the device;

further, an N + injection window on the side of the P + main ring active region is enlarged to cover the source ohmic contact window; therefore, ohmic contacts on two sides of the P + main ring are both N-type ohmic contacts, and the consistency is better. Equivalently, the P + main ring is not directly coupled to the source of the device any more, but a one-way conducting PN diode can reduce the drain-source capacitance of the transition region of the device.

Furthermore, for a terminal structure without a gate runway, a longer transition region is still needed at the corner of a device, P-/N + injection is carried out below the whole transition region, and the transition region in front of a field ring is clamped to zero potential by using N + equipotential rings, so that the electric field distribution of the transition region of the device is more uniform, and the blocking characteristic of the device is improved.

Furthermore, the transition region sequentially comprises a drain electrode, an N + substrate and an N-type drift region from bottom to top, the N-type drift region sequentially comprises an oxide layer and polycrystalline silicon of adjacent cell structures, a P-region and an N + region of adjacent cells, a second ohmic contact metal and a P + main ring from the center to two ends, all structural designs are compatible with the manufacturing process of the active region, and no additional process step is needed.

Furthermore, the invention only aims at the transition region, and does not need to change the process steps and the process parameters of the active region of the device, so that the invention can be compatible with different cell structures, such as SiC MOSFETs and SiC IGBTs with different voltage-resistant grades.

Furthermore, the invention only aims at the transition region, and does not need to change the process steps and the process parameters of the terminal region, so that the invention can be compatible with different terminal structures, including JTE structures and field limiting ring structures.

In conclusion, the N-type equipotential ring adopted by the invention has good ohmic contact quality, can effectively and uniformly distribute the electric field in the transition region during voltage resistance, improves the blocking characteristic of a device, and can also reduce the drain-source electrode capacitance of the transition region; the method does not need additional process steps, and has good compatibility with different cell structures and terminal structures.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

FIG. 1 is a schematic diagram of a front side top view of a conventional silicon carbide MOSFET chip;

FIG. 2 is a schematic cross-sectional view of a silicon carbide MOSFET chip of the present invention;

FIG. 3 is a schematic diagram of a second cross-sectional configuration of a silicon carbide MOSFET chip in accordance with the present invention;

fig. 4 is a schematic diagram of a third cross-sectional configuration of a silicon carbide MOSFET chip in accordance with the present invention.

101, a terminal; 102. an active region; 103. a gate electrode; 104. a source electrode; 201. a first substrate; 202. a first drift layer; 203. a first drain metal layer; 210. a first active region; 211. a first well region; 212. a first source region; 213. a first enhancement zone; 214. a first gate oxide layer; 215. a first gate electrode; 216. a first gate insulating layer; 217. a first source metal layer; 218. a second well region; 219. a second source region; 220. a first transition zone; 221. a second enhancement zone; 222. a third well region; 223. a third source region; 224. a third source metal layer; 225. a first field oxide layer; 226. a first grid track; 227. a first gate track insulating layer; 228. a gate runner metal layer; 229. a second source metal layer; 230. a first termination region; 231. a first field limiting ring; 232. a second field oxide layer; 233. a first cutoff ring; 301. a second substrate; 302. a second drift layer; 303. a second drain metal layer; 310. a second active region; 311. a fourth well region; 312. a fourth source region; 313. a third enhancement zone; 314. a second gate oxide layer; 315. a second gate electrode; 316. a second gate insulating layer; 317. a fourth source metal layer; 318. a fifth well region; 319. a fifth source region; 320. a second transition zone; 321. a fourth enhancement region; 322. a sixth well region; 323. a sixth source region; 324. a sixth source metal layer; 325. a third field oxide layer; 326. a second grid track; 327. a second gate track insulating layer; 328. a second gate track metal layer; 329. a fifth source metal layer; 330. a second termination region; 331. a second field limiting ring; 332. a fourth field oxide layer; 333. a second stop ring; 401. a third substrate; 402. a third drift layer; 403. a third drain metal layer; 410. a third active region; 411. a seventh well region; 412. a seventh source region; 413. a fifth enhancement zone; 414. a third gate oxide layer; 415. a third gate electrode; 416. a third gate insulating layer; 417. a seventh source metal layer; 418. an eighth well region; 419. an eighth source region; 420. a third termination region; 421. an eighth source metal layer; 422. a sixth enhancement zone; 423. a third field limiting ring; 424. a fifth field oxide layer; 425. a third stop ring.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "one side", "one end", "one side", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Various structural schematics according to the disclosed embodiments of the invention are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of various regions, layers and their relative sizes and positional relationships shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, according to actual needs.

Referring to fig. 1, a terminal 101 and an active region 102 are fabricated on the same substrate, a metal layer and a passivation layer are covered on the upper surface of the terminal, a designed field ring, a transition region and other terminals are disposed below the surface of the terminal 101, and a cellular portion is disposed below the surface of the terminal 102; the gate electrode 103 is a gate metal window exposed by the passivation layer of the terminal 101 and the active region 102, and a polysilicon gate is arranged below the surface of the gate electrode 103 and connected to the gate of the cell; the source electrode 104 is a source metal window where the passivation layers of the terminal 101 and the active region 102 are exposed, and the source electrode 104 includes two symmetric source electrodes, each connected to the source of the cell.

The invention provides a SiC power device terminal structure with N-type equipotential rings, which solves the problems of poor ohmic contact quality and increased drain-source capacitance of a terminal area on the premise of not increasing or adjusting a process flow.

The invention relates to a SiC power device terminal structure with N-type equipotential rings, which comprises a substrate, a drift layer, an active region, a transition region and a terminal region, wherein the drift layer is arranged on the substrate; the drift layer is located above the substrate, and an active region, a transition region and a terminal region are sequentially arranged on the drift layer from the center to the edge.

The substrate is a first conductivity type silicon carbide substrate and the drift layer is of the first conductivity type.

Optionally, the cell structure of the active region is a silicon carbide MOSFET or a silicon carbide IGBT.

When the cellular structure of the SiC power device is a silicon carbide MOSFET, the SiC power device sequentially comprises a drain electrode, an N + substrate, an N-type drift region, a P region, an N + region, a P + region, an oxide layer, polycrystalline silicon and first ohmic contact metal from bottom to top;

the transition region sequentially comprises a drain electrode, an N + substrate and an N-type drift region from bottom to top,

the drift region sequentially comprises an oxide layer and polysilicon of adjacent cells, a P-region and an N + region of the adjacent cells, second ohmic contact metal, a P + main ring, a field oxide layer, a gate runway and gate runway metal and an upper passivation layer from the center to two ends.

The terminal region is positioned above the drift region and comprises a P region connected with the P + main ring, an N + region above the P region, third ohmic contact metal, a P + ring, a field oxide layer above the P + ring, an N + stop ring and a passivation layer.

Ohmic contact metals of the cellular structure, the transition region and the terminal region are all electrically communicated with a source electrode of the active region, and electrodes of the gate runway are electrically communicated with a gate electrode of the active region.

The polysilicon of the gate track in the transition region and the polysilicon gate of the active region are formed simultaneously and connected through a polysilicon bridge.

The gate track and the ohmic contact metal are isolated by a passivation layer.

The second ohmic contact metal of the transition region can cover P +, N +/P +, or N +.

The transition zone may remove the runway area.

The primitive cell structure is hexagonal, strip-shaped or rectangular.

The terminal region is of a JTE structure or a field limiting ring structure.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The N-type doping and the P-type doping mentioned in the embodiments of the present invention are relative, and may also be referred to as a first doping and a second doping, i.e., the interchanging of N-type and P-type is also applicable to the device.

In the embodiment of the present invention, the structure of the MOSFET device is exemplified by SiC.

Example 1

As shown in fig. 2, the present embodiment provides a SiC MOSFET device with an N + equipotential ring, which includes a first substrate 201, a first drift layer 202, a first drain metal layer 203, a first active region 210, a first transition region 220, and a first termination region 230.

Illustratively, the first substrate 201 is an N + silicon carbide substrate.

The first drift layer 202 is an N-type drift layer and is located above the first substrate 201. The doping concentration and the thickness of the first drift layer 202 are adjusted according to different chip withstand voltage capabilities.

The first drain metal layer 203 is located under the first substrate 201, forming an ohmic contact with the first substrate 201.

The first active region 210, the first transition region 220 and the first termination region 230 are all disposed on the first drift layer 202, the first transition region 220 being located between the first active region 210 and the first termination region 230.

The first active region 210 includes several cell structures, for example, only one cell structure is shown in fig. 3, and the cell structure includes a first well region 211, a first source region 212, a first enhancement region 213, a first gate oxide layer 214, a first gate electrode 215, a gate insulation layer 216, a first source metal layer 217, a second well region 218, a second source region 219, and a second source metal layer 229.

The first well region 211 is P-type and located on both sides of the cell structure and in the surface of the first drift layer 202, and the upper surface of the first well region 211 is flush with the upper surface of the first drift layer 202.

The first source region 212 is an N-type source region and is located in the surface of the first well region 211, and an upper surface of the first source region 212 is flush with an upper surface of the first drift layer 202. The width of the first source region 212 is smaller than that of the first well region 211, a channel (not shown) is formed between the width difference near the center of the cell structure and the first gate oxide layer 214, and the area between two adjacent channels is a JFET region (not shown).

The first enhancement region 213 is a P-type enhancement region, and the first enhancement region 213 and the first source region 212 are disposed side by side in the surface of the first well region 211 and contact an end of the first source region 212 away from the center of the cell structure. The upper surface of the first enhancement region 213 is flush with the upper surface of the first drift layer 202, and one end of the first enhancement region 213 away from the center of the cell structure is flush with one end of the first well region 211 away from the center of the cell structure, that is, one side of the surface of the first well region 211 away from the center of the cell structure is completely covered by the first enhancement region 213. The ion doping concentration of the first enhancement region 213 is greater than that of the first well region 211.

The planar gate is located at the center of the unit cell and comprises a first gate oxide layer 214 and a first gate electrode 215.

Wherein the first gate oxide layer 214 is located above the first drift layer 202 and simultaneously contacts with the surfaces of the first source region 212, the first well region 211 and the first drift layer 202 to form a conductive channel, and the thickness of the first gate oxide layer 214 is about 50Nm. The first gate 215 is located above the first gate oxide layer 214, and the first gate 215 is a polysilicon gate.

The first source metal layer 217 is positioned over the source region 212 and the first enhancement region 213, and simultaneously forms a good ohmic contact with the first source region 212 and the first enhancement region 213. Wherein the first source metal 217 cannot contact the first drift layer 202. The first source metal 217 may be a metal having low contact resistivity, such as aluminum, nickel, or the like. The first source metal 217 is isolated from the gate insulating layer 214 and the first gate electrode 215 by an interlayer dielectric layer 216.

The second well region 218 is P-type and located at the boundary of the cell structure and the transition region, and the second well region 218 and the first well region 211 are formed by the same ion implantation process, so that the upper surface of the second well region 218 is flush with the first well region 211 and the depth and the doping concentration are the same.

The second source region 219 is an N-type source region and is located in the surface of the second well region 218, and the upper surface of the second source region 219 is flush with the upper surface of the first drift layer 202. The width of the second source region 219 is smaller than the width of the second well region 218, and a channel (not shown) is formed between the width difference near the center of the cell structure and the first gate oxide layer 214. The second source regions 219 are formed by the same ion implantation process as the first source regions 212, so that the upper surfaces of the second source regions 219 are flush with the first source regions 212 and the depths and doping concentrations are the same.

The second source metal layer 229 is located above the second source region 219, has a width smaller than that of the second source region 219, and has a width difference between the left and right sides. The second source metal layer 229 forms a good ohmic contact with the second source region 219. The second source metal layer 229 may be a metal having low contact resistivity, such as aluminum, nickel, or the like.

A gate insulating layer 216 is formed on the upper surfaces of the first and second source regions 212 and 219 to isolate the first gate electrode 215 from the first and second source metal layers 217 and 229 and to cover the first gate electrode 215.

The first transition region 220 includes a second enhancement region 221, a third well region 222, a third source region 223, a third source metal layer 224, a first field oxide layer 225, a first gate runner 226, a first gate runner insulating layer 227, and a first gate runner metal layer 228.

The second enhancement region 221 is a P-type enhancement region and is located in the surface of the first drift layer 202, the upper surface of the second enhancement region 221 is flush with the upper surface of the first drift layer 202, the ion doping concentration of the second enhancement region 221 is the same as that of the first enhancement region 213, and the depth of the second enhancement region 221 is the same as that of the first enhancement region 213.

The third well region 222 is a P-type well region, the upper surface of which is flush with the first drift layer 202, and the ion doping concentration and depth of the third well region 222 are the same as those of the first well region 211.

The upper surface of the third source region 223 is flush with the third well region 222, and the width of the third source region is smaller than that of the third well region. The depth and doping concentration of the third source region 223 are the same as those of the first source region 212.

The third source metal layer 224 is located above the third source region 223, and has a width smaller than that of the third source region 223, and the left and right sides have a width difference. The third source metal layer 224 forms a good ohmic contact with the third source region 223. The third source metal layer 224 may be a metal having low contact resistivity, such as aluminum or nickel.

The first field oxide layer 225 is located above the second enhancement region 221, and has a thickness of 1 μm, and is horizontally interposed between the second source metal 229 and the third source metal layer 224.

The first gate runner 226 is located above the first field oxide layer 225, has a width smaller than that of the first field oxide layer 225, and has a width difference between the left and right sides. The gate runner 228 and the first gate 215 are formed by the same process, and are polysilicon gates with uniform thickness.

The first gate runner metal layer 228 is located on the upper surface of the first gate runner 226, has a smaller width than the first gate runner 226, and has a difference in width between both sides. The gate track metal layer can be made of metals with low contact resistivity such as nickel, titanium and the like, is different from the active area metal layer, and is finished by a two-step process.

The first gate runner insulating layer 227 extends from the surface of the first field oxide layer 225 to above the first gate runner 226, and covers both sides of the first gate runner 226 where the first gate runner metal layer 228 is not covered.

The first termination region 230 includes a first field limiting ring 231, a second field oxide layer 232, and a first stop ring 233.

The first field limiting ring 231 is a plurality of injection rings arranged in the first drift layer 202 at intervals, and is a P-type heavily doped region. The upper surface of the first field limiting ring 231 is flush with the upper surface of the first drift layer 202, and the ion doping concentration of the first field limiting ring 231 may be the same as that of the first enhancement region 213, or may be a heavily doped region with other concentrations.

The second field oxide layer 232 is disposed on the upper surface of the first field limiting ring 231 and adjacent to the third source metal layer 224. The second field oxygen layer and the first field oxygen layer are generated in the same step of process, and the thickness of the second field oxygen layer and the thickness of the first field oxygen layer are both 1 mu m.

The upper surface of the first stop ring 233 is flush with the first drift layer 202 and is located at the edge of the device. The first stop ring 233 is heavily doped N-type, and has the same ion doping concentration and depth as the source region.

Example 2

Referring to fig. 3, the present embodiment provides a SiC MOSFET device with N + equipotential rings, which includes a second substrate 301, a second drift layer 302, a second drain metal layer 303, a second active region 310, a second transition region 320, and a second termination region 330.

The second active region 310 includes a fourth well region 311, a fourth source region 312, a third enhancement region 313, a second gate oxide layer 314, a second gate 315, a second gate insulating layer 316, a third source metal layer 317, a fifth well region 311, a fourth source region 312, and a fourth source metal layer 329.

The second transition region 320 includes a fourth enhancement region 321, a sixth well region 311, a seventh source region 323, a third source metal layer 324, a third field oxide layer 325, a second gate runner 326, a second gate runner insulating layer 327, and a second gate runner metal layer 328.

The second termination region 330 includes a second field limiting ring 331, a fourth field oxide layer 332, and a second stop ring 333.

The structure of the second active region 310 and the second transition region 320 in embodiment 2 is slightly different from that in embodiment 1, and mainly includes the fifth well region 311, the fourth source region 312, the fourth enhancement region 321, the fifth source metal layer 329, and the third field oxide layer 325, but other regions are completely the same, and are not repeated.

The fifth well region 311 is P-type, the upper surface of the fifth well region 311 is flush with the upper surface of the second drift layer 302, and the ion doping concentration and the ion doping depth are the same as those of the fourth well region 311.

The fourth source region 312 is an N-type source region and is located in the fifth well region 311, and an upper surface of the fourth source region 312 is flush with an upper surface of the second drift layer 302. The width of the fourth source region 312 is smaller than that of the fifth well region 311, and a channel (not shown) is formed between the width difference near the center of the cell structure and the first gate oxide layer 214, and the width of the side far from the center of the cell structure is flush. The fourth source region 312 and the fourth source region 312 are formed by the same ion implantation process, and the ion doping concentration and the ion doping depth are equal.

Fourth enhancement region 321 is a P-type enhancement region located within the surface of drift 302, adjacent to the second well region and the second source region. The upper surface of the fourth enhancement region 321 is flush with the upper surface of the second drift layer 302, and the ion doping concentration and depth of the fourth enhancement region 321 are the same as those of the third enhancement region 313.

The fifth source metal layer 329 is located above the junction of the fourth source region 312 and the fourth enhancement region 321, and partially overlaps the fourth source region 312 in the direction close to the cell structure and partially overlaps the fourth enhancement region 321 in the direction close to the transition region.

The third field oxide layer 325 is located above the second enhancement region 221, has a thickness of 1 μm, and is adjacent to the fifth source metal layer 329.

Example 3

As shown in fig. 4, the present embodiment provides a SiC MOSFET device with an N + equipotential ring, which includes a third substrate 401, a third drift layer 402, a third drain metal layer 403, a third active region 410, and a third termination region 420.

The third active region 410 includes a seventh well region 411, a seventh source region 412, a fifth enhancement region 413, a third gate oxide layer 414, a third gate 415, a third gate insulating layer 416, a seventh source metal layer 417, an eighth well region 418, and an eighth source region 419.

The third termination region 420 includes a sixth enhancement region 422, a third field limiting ring 423, a second field oxide layer 424, and a third stop ring 425.

The main difference between embodiment 3 and embodiment 1 is that the transition region is eliminated, and the third termination region 420 is slightly changed, and the sixth enhancement region 422 is mainly added, and other structures are completely the same, and are not described herein again.

A sixth enhancement region 422, which is a P-type enhancement region, is located under the fifth field oxide 424, within the surface of the third drift layer 402, adjacent to the eighth well region 418 and the eighth source region 419. The upper surface of the sixth enhancement region 422 is flush with the upper surface of the third drift layer 402, and the ion doping concentration and depth of the sixth enhancement region 422 are the same as those of the fifth enhancement region 413.

In summary, the SiC power device terminal structure with the N-type equipotential ring clamps the tail end of the main ring to zero potential during voltage withstanding, and meanwhile, the N + equipotential ring can improve the ohmic contact quality above the equipotential ring, reduce the source-drain capacitance of the transition region, and has good compatibility with the existing design and process.

The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims (10)

1. A SiC power device terminal structure with N-type equipotential rings is characterized by comprising a substrate, wherein the substrate is arranged on a drain metal layer, a drift layer is arranged on the substrate, a source region, a transition region and a terminal region are sequentially arranged on the drift layer from the center to the edge, a first ohmic contact metal of a cell structure of the active region, a second ohmic contact metal of the transition region and a third ohmic contact metal of the terminal region are all in electrical communication with a source electrode of the active region, and a gate runway electrode of the transition region is in electrical communication with a gate electrode of the active region;

the transition region sequentially comprises a drain electrode, an N + substrate and an N-type drift region from bottom to top, the N-type drift region sequentially comprises an oxide layer and polycrystalline silicon of adjacent cell structures, a P-region and an N + region of adjacent cells from the center to two ends, a second ohmic contact metal and a P + main ring, and a field oxide layer, a grid runway, grid runway metal and a passivation layer are arranged on the P + main ring.

2. The SiC power device termination structure with equipotential rings of the N-type according to claim 1, in which the cell structure is a silicon carbide MOSFET or a silicon carbide IGBT.

3. The SiC power device termination structure with equipotential rings of the N-type of claim 2, wherein the cell structure, when a silicon carbide MOSFET is used, includes, in order from bottom to top, a drain, an N + substrate, an N-type drift region, a P region, an N + region, a P + region, an oxide layer, polysilicon, and the first ohmic contact metal.

4. A SiC power device termination structure with equipotential rings of the N-type according to claim 1, 2 or 3, characterized in that the cell structure is hexagonal, bar-shaped or rectangular.

5. The SiC power device termination structure with equipotential rings of the N-type according to claim 1, wherein the substrate is a silicon carbide substrate of the first conductivity type and the drift layer is of the first conductivity type.

6. The SiC power device termination structure with equipotential rings of the N-type according to claim 1, in which the gate runner and the second ohmic contact metal are separated by a passivation layer.

7. The SiC power device termination structure with equipotential rings of the N-type according to claim 1, wherein the polysilicon of the gate runner is formed simultaneously with the polysilicon gate of the active region and connected by a polysilicon bridge.

8. The SiC power device termination structure with equipotential rings of the N-type according to claim 5, wherein the second ohmic contact metal covers the P + region, the N + region/the P + region, or the N + region of the cell structure.

9. The SiC power device termination structure with equipotential rings of the N-type according to claim 1, wherein the termination region includes a P region connected to the P + main ring of the transition region, an N + region, a third ohmic contact metal, and a P + ring are disposed over the P region, and a field oxide layer, an N + stop ring, and a passivation layer are disposed over the P + ring.

10. The SiC power device termination structure with equipotential rings of the N-type according to claim 1 or 9, characterized in that the termination region is a JTE structure or a field limiting ring structure.

Images