CN115841942A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN115841942A
CN115841942A CN202210127975.5A CN202210127975A CN115841942A CN 115841942 A CN115841942 A CN 115841942A CN 202210127975 A CN202210127975 A CN 202210127975A CN 115841942 A CN115841942 A CN 115841942A
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Prior art keywords
layer
concave
semiconductor device
barrier metal
gate pad
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CN202210127975.5A
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井上绘美子
西川幸江
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Publication of CN115841942A publication Critical patent/CN115841942A/zh
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Abstract

本发明实施方式提供提高了栅极焊盘的密合性的半导体装置及其制造方法。实施方式的半导体装置具备硅基板、第1层、第2层、阻挡金属和栅极焊盘。上述第1层由上述硅基板上所具备的氧化膜形成。上述第2层是在上述第1层的上表面中至少选择性地具有凹凸部的层，上述凹凸部具有比在以平面状形成该层的情况下产生的凹凸深的凹凸。上述阻挡金属在上述第2层2的上表面按照上述凹凸部的形状而形成。上述栅极焊盘介由上述阻挡金属与上述硅基板密合。

Description

半导体装置及半导体装置的制造方法
关联申请
本申请享有以日本专利申请2021-153436号(申请日：2021年9月21日)作为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置及半导体装置的制造方法。
背景技术
IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极晶体管)作为功率器件而车载用、电车用、或在产业设备等中作为开关元件等被广泛使用。该IGBT在形成漂移、集电极等的硅基板上形成氧化膜、层间膜等，在其上部介由阻挡金属形成用于施加栅极电压的栅极焊盘。如果仅单纯地在阻挡金属上具备栅极焊盘，则栅极焊盘经常从金属剥离。为了应对其，有通过在层间膜中形成多晶硅、并在该多晶硅与阻挡金属的界面处形成硅化物来提高密合性的技术，但即使是该情况下，密合性有时也不充分。因此，期望技术的进一步提高。
发明内容
一实施方式提供提高了栅极焊盘的密合性的半导体装置及其制造方法。
根据一实施方式，半导体装置具备硅基板、第1层、第2层、阻挡金属和栅极焊盘。上述第1层由上述硅基板上所具备的氧化膜形成。上述第2层是在上述第1层的上表面中至少选择性地具有凹凸部的层，上述凹凸部具有比在以平面状形成该层的情况下产生的凹凸深的凹凸。上述阻挡金属在上述第2层2的上表面按照上述凹凸部的形状而形成。上述栅极焊盘介由上述阻挡金属与上述硅基板密合。
附图说明
图1是示意性表示一实施方式的半导体装置的一部分的截面图。
图2～11是示意性表示一实施方式的半导体装置的工艺的截面图。
图12是示意性表示一实施方式的半导体装置的一部分的截面图。
图13是示意性表示一实施方式的半导体装置的一部分的截面图。
图14是示意性表示一实施方式的半导体装置的一部分的截面图。
图15是示意性表示一实施方式的半导体装置的一部分的截面图。
图16、17是示意性表示一实施方式的半导体装置的工艺的截面图。
图18是示意性表示一实施方式的半导体装置的一部分的截面图。
图19是示意性表示一实施方式的半导体装置的一部分的截面图。
图20是示意性表示一实施方式的半导体装置的一部分的截面图。
图21是示意性表示一实施方式的半导体装置的一部分的截面图。
图22～27是示意性表示一实施方式的凹凸部的例子的俯视图。
具体实施方式
以下，参照附图对实施方式进行说明。本申请由于是对栅极焊盘的形成进行说明的申请，因此要留意关于形成于硅基板内的半导体的图示及说明省略。此外，在附图中，为了变得容易理解结构，有时变更要素彼此的大小的比率、长宽比或角度等，但实施方式的内容并不限定于这些比率，由适宜的大小构成。此外，作为有棱角的形状而记载的部位也可以是在该角处由蚀刻等工艺上的规格或设计上的构成等变圆的形状。此外，虽然使用了上表面这样的表述，但其表示在一般的半导体工艺中作为铅直方向上侧的面。此外，对凹凸部进行了说明，但各图中的该凹凸部的槽的个数表示为不限定的一个例子，可以任意地变更。
(第1实施方式)
图1是示意性表示第1实施方式的半导体装置的一部分的截面图。
半导体装置1例如为IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)。半导体装置1具备硅基板10、氧化膜12、层间膜14、多晶硅16、阻挡金属18和栅极焊盘20。半导体装置1通过对形成于硅基板10上的半导体层介由栅极焊盘20施加电压而作为功率器件发生动作。
硅基板10是形成各种半导体层的基板，例如形成漂移层、集电极层。作为不限定的一个例子，在半导体装置1为n沟道IGBT的情况下，通过从栅极焊盘20介由氧化膜12施加电压而在形成于n型的漂移层的上部的p型半导体层中形成沟道。集电极电流从集电极经由p型半导体层、n型漂移层及沟道流向形成于硅基板10上的发射极电极。当然，为p沟道IGBT的情况也基于对栅极焊盘20施加的电压而适宜地输出集电极电流。
氧化膜12是作为第1层而形成于硅基板10上的栅极绝缘膜，例如通过将Si热氧化而得到的热氧化膜(SiO2)来形成。此外，作为其他例子，也可以通过将Si热氮化而得到的热氮化膜(SiON)来代替。
层间膜14是形成于氧化膜12上的层间绝缘膜，将配置于硅基板10上的布线分离。该层间膜14例如为在SiO2膜中掺杂有氟等的绝缘膜。
多晶硅16在硅基板10的氧化膜12上按照在层间膜14中选择性地与阻挡金属18相接触的方式形成。在制造半导体装置1的工艺中，形成该多晶硅16与阻挡金属18的材料的硅化物。通过形成硅化物，提高硅基板10与阻挡金属18(及栅极焊盘20)之间的密合性。在本实施方式中，通过该层间膜14和多晶硅16来形成第2层2。
阻挡金属18是形成于多晶硅16(第2层2的规定区域)与栅极焊盘20之间的金属膜。阻挡金属18是为了防止栅极焊盘20中使用的金属材料的扩散、或防止相互反应而形成的金属膜。阻挡金属18例如使用与多晶硅16形成硅化物、并且与栅极焊盘20的密合性良好的材料。
该栅极焊盘20作为栅极电极发生动作，控制通过输入该栅极焊盘20的电压而在半导体装置1中流动的电流。栅极焊盘20例如也可以使用Al、AlSi、AlCu、AlSiCu、Cu、Au、W、WSi、Ti、TiSi等。
根据栅极焊盘20的材料，适宜地选择阻挡金属18的材料。关于阻挡金属18，例如如果栅极焊盘20为Al、AlSi，则也可以使用Ti、TiN，如果栅极焊盘20为Cu，则也可以使用Ta、TaN。此外，并不限定于这些材料，只要适宜由具有下述所示的特性的材料来形成即可。以下，作为一个例子，将栅极焊盘20设定为AlSi、将阻挡金属18设定为Ti或TiN而进行说明。
在本实施方式中，多晶硅16与阻挡金属18并非以平面作为界面而相接触，在该截面中，具有选择性地形成的凹凸部100。该凹凸部100的高度h与在平面上形成多晶硅的情况下产生的凹凸(～150nm左右)相比充分大。例如，h也可以为300～600nm左右，与在形成多晶硅16的情况下产生的凹凸相比充分大地形成。即，在多晶硅16中形成的凹凸部100具有与在平坦地形成多晶硅16的情况下可能产生的凹凸的深度相比充分深的深度。
需要说明的是，在阻挡金属18中，也可以在形成于阻挡金属18中的凹凸部的至少侧壁的区域中成膜出不填埋凹凸的程度的W等金属膜。
按照其形状，栅极焊盘20也具有凹凸而形成。通过像这样形成栅极焊盘20，能够利用锚固效应来抑制硅基板10与栅极焊盘20间的接合剥离。此外，通过在界面处形成硅化物，能够进一步抑制接合剥离。此外，在栅极焊盘20与阻挡金属18的接触面中形成W等金属膜的情况下，通过该金属膜，能够进一步提高密合性。这些特征在以下的实施方式中也同样。
对于本实施方式的半导体装置1的制造工艺使用图2～图11进行说明。
首先，如图2中所示的那样，按照在硅基板10内适宜地动作的方式通过各种工艺来形成半导体层，在该硅基板10的上表面形成氧化膜12。然后，在该氧化膜12的上表面形成多晶硅16。对于该工艺，通过一般的工艺来执行。
接着，如图3中所示的那样，在多晶硅16的上表面选择性地形成掩模30。该掩模30按照在硅基板10中配置栅极电极的区域，按照在该区域上形成多晶硅16的方式形成。在光刻的情况下，掩模30为光致抗蚀剂。
接着，如图4中所示的那样，对多晶硅16进行蚀刻。该蚀刻也可以通过RIE(反应离子蚀刻，Reactive Ion Etching)或CDE(化学干式蚀刻，Chemical Dry Etching)来执行。
接着，如图5中所示的那样，将一度在图3的工艺中形成的掩模30除去，形成新的掩模32。该掩模32按照在多晶硅16上适宜地产生凹凸部的方式选择性地形成。
接着，如图6中所示的那样，执行多晶硅16的第二次的蚀刻(例如CDE)。该蚀刻工艺并非将多晶硅16通过蚀刻而除去至与氧化膜12的边界面为止，而是按照形成适宜深度的凹形状的凹陷的方式执行。即，并非像一般的CDE工艺那样将掩模的开口部中的蚀刻对象的材料完全除去，而是在除去至材料的途中的时候该工艺结束。通过经由该工艺，形成图1中所示的凹凸部100。
接着，如图7中所示的那样，除去掩模32后，在氧化膜12及多晶硅16的上表面形成层间膜14。
接着，如图8中所示的那样，基于形成栅极焊盘的区域来形成掩模34。该掩模34是为了确保将多晶硅16与栅极焊盘电连接的层间膜14中的接触区域而形成。
接着，如图9中所示的那样，通过RIE处理将层间膜14选择性地除去，形成接触区域。
接着，如图10中所示的那样，将掩模34除去后，在层间膜14及多晶硅16的上表面将阻挡金属18成膜。
接着，如图11中所示的那样，在阻挡金属18的上表面，成膜出形成栅极焊盘20的导体。然后，通过将该导体及阻挡金属按照在适宜的区域中残留的方式除去剩余的部分，制造出图1中所示的半导体装置1。
作为一个例子，也可以在图2中按照多晶硅16成为1000nm、在图5中按照掩模32的开口部的宽度成为450nm、在图6中按照多晶硅16的凹部的深度成为300nm、宽度成为500nm的方式执行工艺，但并不限定于这些大小。
(第2实施方式)
图12是示意性表示第2实施方式的半导体装置的一部分的截面图。
半导体装置1在凹凸部100中具备插塞22。进而，在栅极焊盘20的接触区域的侧壁中，也可以在阻挡金属18与栅极焊盘20之间具备金属膜24。
插塞22例如为由W形成的插塞，按照填充凹凸部100的方式形成。即，按照使起因于阻挡金属18中形成的凹凸部100的凹凸区域变得平坦的方式形成W。
栅极焊盘20形成于通过插塞22而平坦化的上表面。由于下表面平坦，因此在栅极焊盘20的成膜后，栅极焊盘20的接触区域的上表面也平坦地形成。
凹凸部100的宽度例如也可以与第1实施方式同样地设定为宽度500nm、深度300nm，深度也可以在300～600nm等范围内发生变化。
为了形成插塞22，多晶硅16的凹凸部100也可以按照宽度与第1实施方式相比不发生变化的方式形成。
为了像这样形成，在本实施方式中，例如，通过RIE来执行图6的工艺。在该RIE处理之后，将阻挡金属18成膜，之后，例如使用W来成膜出插塞22及金属膜24。之后，按照适宜地形成插塞22及金属膜24的方式图案化，再次通过RIE对整面进行回蚀。通过将W等金属成膜后在接触区域中对整面进行回蚀，形成插塞22，通过该回蚀工艺同样地在接触区域的侧壁上形成金属膜24。根据需要，也可以将该金属膜24除去，但即使存在也没有特别问题。
根据本实施方式，与第1实施方式同样地能够利用锚固效应来抑制接合剥离。进而，通过将多晶硅的凹部用插塞埋入，从而形成于其上表面的栅极焊盘20的上表面被平坦化。通过将栅极焊盘20的上表面平坦化，能够提高接合中的引线的密合性。
需要说明的是，作为一个例子将插塞22的宽度设定为500nm，但并不限定于此，只要是能够适宜地形成插塞的宽度即可。
(第3实施方式)
图13是示意性表示第3实施方式的半导体装置的一部分的截面图。
对于凹凸部100，也可以设定为沿着其侧壁而具备插塞22的构成。即，与第2实施方式不同，并非将沿着凹凸部100的阻挡金属18的凹部填充，也可以沿着该凹部的侧壁而具备插塞22。因此，如果与第2实施方式相比，则也可以增大凹凸部100的宽度。凹凸部100的宽度例如可以设定为5μm，但并不限定于此，可以设定为阻挡金属18中的凹部不被金属(例如W)填充的程度的宽度。
该半导体装置1的工艺除了将凹凸部100的宽度扩展以外，与第2实施方式大致同样。但是，在成膜出插塞22的工艺中，以不填充阻挡金属18的凹部的程度形成金属。
通过像这样在与阻挡金属相接触的多晶硅的表面形成凹凸，能够利用锚固效应来抑制接合剥离。
(第4实施方式)
图14是示意性表示第4实施方式的半导体装置的一部分的截面图。
形成于多晶硅16中的凹凸部100也可以是至少在其最下表面中与氧化膜12相接触的形态。在本实施方式的半导体装置1中，也可以在阻挡金属18的凹部的侧壁、及阻挡金属18中的栅极焊盘20的接触区域的侧壁区域中形成金属膜24。凹凸部100的宽度例如可以设定为5μm，但并不限定于此。
该半导体装置1的工艺通过在图5的工艺中将掩模的图案宽度适宜扩展、在图6的工艺中对多晶硅16仅以其高度量通过CDE进行蚀刻来安装。之后的工艺与第1实施方式同样。
通过像这样在与阻挡金属18相接触的多晶硅16的表面中形成凹凸，能够利用锚固效应来抑制接合剥离。
(第5实施方式)
图15是示意性表示第5实施方式的半导体装置的一部分的截面图。
在该半导体装置1中，在第2层2中，在多晶硅16的上表面通过层间膜14来形成凹凸部100。通过层间膜14而形成的凹凸部100在其下表面中按照多晶硅16与阻挡金属18相接触的方式形成。例如，该凹部的宽度为500nm。
而且，阻挡金属18在起因于凹凸部100的凹部中按照填充该凹部的方式形成插塞22。
对该半导体装置1的工艺进行说明。图2～图4的工艺与第1实施方式同样。之后，不进行图5和图6的工艺，而执行图7的层间膜14的形成工艺。作为一个例子，也可以以1000nm的高度形成层间膜14。
图16及图17是示意性表示紧接其后的工艺的截面图。
在形成层间膜14之后，如图16中所示的那样基于使用层间膜14而形成凹凸部的图案来形成掩模34。
接着，如图17中所示的那样，通过RIE对层间膜14进行蚀刻。如果是上述的例子，则通过对层间膜14进行1000nm蚀刻，从而在凹部的下表面中，能够按照使阻挡金属18能够与多晶硅16相接触的方式形成利用了层间膜14的凹凸部。
之后的工艺与第2实施方式同样。
通过像这样在与阻挡金属18相接触的第2层2的表面形成凹凸，能够利用锚固效应来抑制接合剥离。此外，在本实施方式中，通过将层间膜14的凹部利用插塞22埋入，从而形成于其上的栅极焊盘20的上表面被平坦化。通过将栅极焊盘20的上表面平坦化，能够提高接合中的引线的密合性。层间膜的凹部的冲裁宽度例如为500nm，但只要是限定于其的形成插塞22的值则可以取任意的值。
(第6实施方式)
图18是示意性表示第6实施方式的半导体装置的一部分的截面图。
在该半导体装置1中，在第2层2中，与第5实施方式同样地使用层间膜14来形成凹凸部100。然后，在阻挡金属18的上表面中，在由该凹凸部100产生的凹部的侧壁上形成有金属膜24。
该半导体装置1的工艺是将上述的第5实施方式与第3实施方式组合而成的工艺。即，在第5实施方式的层间膜14的蚀刻中，变更掩模34的图案，例如按照第2层2中的凹部的冲裁宽度成为5μm的方式配置掩模34。之后与第5实施方式同样地对层间膜14进行蚀刻。紧接着该蚀刻，与第3实施方式同样地，执行在阻挡金属18的凹部的侧壁上形成金属膜24的工艺。
通过像这样在与阻挡金属18相接触的第2层2的表面形成凹凸，能够利用锚固效应来抑制接合剥离。
(第7实施方式)
图19是示意性表示第7实施方式的半导体装置的一部分的截面图。
在该半导体装置1中，在第2层2中，与第5实施方式同样地使用层间膜14来形成凹凸部100。然后，在至少1个层间膜14之间的凹凸部100中，在阻挡金属18的上表面中形成插塞22，在未形成插塞22的凹凸部100中，在侧壁中在阻挡金属18的侧壁中形成金属膜24。阻挡金属18的凹部的下表面与多晶硅16相接触。
在层间膜14的凹凸部100中，作为一个例子，凹部的冲裁宽度为500nm和5μm，但并不限定于此。在冲裁宽度为500nm的凹部中，形成于阻挡金属18中的凹部具有插塞22。在冲裁宽度为5μm的凹部中，在阻挡金属18的侧壁上形成有金属膜24。
该半导体装置1的工艺通过变更形成凹凸部100的掩模的图案，能够利用与第5实施方式同样的工艺来实现。
通过像这样在与阻挡金属18相接触的层间膜14的表面中形成凹凸，能够利用锚固效应来抑制接合剥离。在本实施方式中，示出了将层间膜的凹部的宽度设定为500nm和5μm的情况，但只要分别是能够形成插塞22的值、及不形成插塞22而形成金属膜24的值则可以取任意的值。
(第8实施方式)
图20是示意性表示第8实施方式的半导体装置的一部分的截面图。
该半导体装置1是第2层2具备层间膜14及多晶硅16而构成。凹凸部100以两阶段形成。更具体而言，凹凸部100通过形成于多晶硅16中的凹部和在多晶硅16的上表面中使用层间膜14而形成的凸部来形成。
在凹凸部100中介由阻挡金属18而形成插塞22。与该插塞22和阻挡金属18的上表面相接触地形成栅极焊盘20。
该半导体装置1的工艺通过在图5～图6中进行RIE等各向同性的蚀刻、及在图8～图9中按照利用层间膜14来形成凹凸的方式进行掩模的图案化来安装。
作为未限定数值的一个例子，层间膜14的凹部的冲裁宽度为500nm以下，高度为1400nm左右。需要说明的是，凹凸部100的下表面也可以按照与氧化膜12相接触的方式形成。
通过像这样在与阻挡金属相接触的多晶Si、层间膜的表面中形成凹凸，能够利用锚固效应来抑制接合剥离。此外，通过在多晶硅16及层间膜14的凹部中埋入插塞22，从而形成于其上的栅极焊盘20的表面被平坦化。通过将栅极焊盘20的表面平坦化，能够提高接合中的引线的密合性。示出了多晶硅16和层间膜14的凹部的冲裁宽度设定为500nm的情况，但只要是形成插塞22的值则可以取任意的值。
(第9实施方式)
图21是示意性表示第9实施方式的半导体装置的一部分的截面图。
该半导体装置1与第8实施方式同样地是第2层2具备层间膜14及多晶硅16而构成。凹凸部100以两阶段形成。更具体而言，凹凸部100通过形成于多晶硅16中的凹部和在多晶硅16的上表面中使用层间膜14而形成的凸部来形成。
作为未限定数值的一个例子，多晶硅16的凹部的冲裁宽度为500nm以下，该多晶硅16的凹部被插塞22埋入。此外，多晶硅16的凹部的高度为300～600nm左右，具有比多晶硅16成膜后的表面的凹凸(150nm左右)深的形状。
此外，层间膜14的凹部的冲裁宽度为5μm，在层间膜14的凹部的侧壁上形成有金属膜24。
该半导体装置1的工艺与第8实施方式同样。在第8实施方式中说明的工艺中，通过适当控制图8中的掩模的图案化的宽度，能够制造出本实施方式的半导体装置1。
作为未限定数值的一个例子，在氧化膜12的上表面将多晶硅16以1000nm进行成膜。然后，通过适宜的蚀刻工艺，按照在多晶硅16中形成宽度为500nm的冲裁图案、具有500nm的宽度的方式进行蚀刻。其结果是，在多晶硅16的表面中形成高度为300nm、宽度为500nm的凹部。
接着，将层间膜14以1000nm成膜后，在多晶硅16的凹部之上，形成宽度为5μm的冲裁图案，对层间膜14进行蚀刻。其结果是，在层间膜14的表面中形成宽度为5μm的凹部。
之后，通过形成阻挡金属18、插塞22、金属膜24及栅极焊盘20，能够制造出本实施方式的半导体装置1。需要说明的是，与第8实施方式同样地，凹凸部100的下表面也可以按照与氧化膜12相接触的方式形成。
通过像这样在与阻挡金属18相接触的多晶硅16及层间膜14的表面中形成凹凸，能够利用锚固效应来抑制接合剥离。示出了多晶硅的凹部的冲裁宽度为500nm的情况，但只要是形成插塞22的值则可以取任意的值。此外，示出了将层间膜14的凹部的冲裁宽度设定为5μm的情况，但只要是不形成插塞22的值则可以取任意的值。
(第10实施方式)
在上述的各实施方式中，对凹凸部100的截面进行了说明，但在本实施方式中对俯视图中的各种形态进行说明。在各个图中，在俯视图中示出了形成于第2层2中的凹凸部100的形状。图22～图27是表示形成于第2层2中的凹凸部100的形状的俯视图的几个不限定的例子的图。
如图22中所示的那样，凹凸部100也可以在第2层2中以条纹形状形成。
如图23中所示的那样，凹凸部100也可以在第2层2中以分别具有宽度的四边形的形状形成。
如图24中所示的那样，凹凸部100也可以在第2层2中以具有宽度的涡旋形状形成。需要说明的是，该涡旋形状由四边形构成，但也可以是其他的多边形形状，还可以是不具有角的圆形的涡旋形状(例如具有宽度的螺旋形状)。
如图25中所示的那样，凹凸部100也可以在第2层2中以格子花纹的形状形成。
如图26中所示的那样，凹凸部100也可以在第2层2中以蜂窝形状形成。
如图27中所示的那样，凹凸部100也可以在第2层2中以具有宽度的八边形状形成。
在任一例子中，多晶硅16及层间膜14的凹凸图案可以考虑接合方向，设定为高效使用了锚固效应的配置。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子提出的，并不意图限定发明的范围。这些新颖的实施方式可以以其他的各种方式来实施，在不脱离发明的主旨的范围内，可以进行各种省略、置换、变更。这些实施方式、其变形包含于发明的范围、主旨内，同时包含于权利要求书中记载的发明和其同等的范围内。
例如，上述的实施方式全部作为IGBT进行了说明，但也可以为MOSFET。此外，并不限定于此。本申请中的实施方式作为不限定的几个例子，在具有绝缘膜和介由绝缘膜而施加电压的电极的半导体装置中，此外，对于平面型、沟槽型中的任一型，都可以适用于该电极的形成。

Claims (9)

1.一种半导体装置，其具备：
硅基板；
第1层，其由所述硅基板的上表面所具备的氧化膜形成；
第2层，其是在所述第1层的上表面中至少选择性地具有凹凸部的层，所述凹凸部具有比在以平面状形成该层的情况下产生的凹凸深的凹凸；
阻挡金属，其在所述第2层的上表面按照所述凹凸部的形状而形成；和
栅极焊盘，其介由所述阻挡金属与所述硅基板密合。
2.根据权利要求1所述的半导体装置，其为IGBT(Insulated Gate BipolarTransistor，绝缘栅双极晶体管)、或MOSFET(Metal-Oxide-Semiconductor Field-EffectTransistor，金属-氧化物-半导体场效应晶体管)。
3.根据权利要求1或权利要求2所述的半导体装置，其中，所述第2层具备：
多晶硅，其选择性地形成于所述第1层的上表面；和
层间膜，其至少形成于所述第1层的上表面的未形成所述多晶硅的区域中，
所述凹凸部在所述多晶硅的上表面中形成。
4.根据权利要求1或权利要求2所述的半导体装置，其中，所述第2层具备：
多晶硅，其选择性地形成于所述第1层的上表面；和
层间膜，其至少形成于所述第1层的上表面的未形成所述多晶硅的区域中，
所述凹凸部通过在所述多晶硅的上表面中选择性地配置的所述层间膜来形成。
5.根据权利要求1或权利要求2所述的半导体装置，其进一步具备金属的插塞，该金属的插塞在所述阻挡金属的上表面中至少形成于按照所述凹凸部而形成的所述阻挡金属的凹凸的侧壁上，
所述栅极焊盘在至少一部分的区域中介由所述插塞而形成于所述阻挡金属的上表面。
6.根据权利要求5所述的半导体装置，其中，所述插塞将按照所述凹凸部而形成的所述阻挡金属的凹凸填充而平坦地形成，
所述栅极焊盘介由所述插塞而形成于所述阻挡金属的上表面。
7.根据权利要求1或权利要求2所述的半导体装置，其中，所述凹凸部在俯视图中以条纹形状、四边形状、涡旋形状、格子形状、蜂窝形状或八边形状形成。
8.一种半导体装置的制造方法，其中，在硅基板的上表面形成作为氧化膜的第1层；
在所述第1层的上表面形成第2层；
在所述第2层的上表面形成基于凹凸部的图案的掩模；
通过基于所述掩模的蚀刻处理在所述第2层中形成所述凹凸部；
将所述掩模除去；
在所述第2层的上表面将阻挡金属成膜；
在所述阻挡金属的上表面将形成栅极焊盘的金属成膜。
9.根据权利要求8所述的半导体装置的制造方法，其中，在所述阻挡金属的成膜与形成所述栅极焊盘的金属的成膜之间，将与形成所述阻挡金属的金属及形成所述栅极焊盘的金属不同的金属在至少形成有沿着所述凹凸部而形成的所述阻挡金属的区域的侧壁上进行成膜。
CN202210127975.5A 2021-09-21 2022-02-11 半导体装置及半导体装置的制造方法 Pending CN115841942A (zh)

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