CN115841842B - Memory testing method, system and computer readable storage medium - Google Patents
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Abstract
The invention provides a memory test method, a system and a computer readable storage medium, wherein the method is applied to a memory test system, a unified extensible firmware interface is installed on the memory test system, and the method comprises the following steps: receiving the information of the tested memory through a unified extensible firmware interface; receiving a first test instruction; obtaining a custom test configuration according to the first test instruction and the tested memory information; configuring the tested memory according to the self-defined test configuration; and testing the configured tested memory to obtain a test result. According to the invention, the memory can be tested without entering an operating system, the test time is saved, meanwhile, specific test parameters aiming at the tested object can be flexibly configured according to different tested objects, and the coverage and flexibility of the memory test are improved.
Description
Technical Field
The present invention relates to the field of memory testing technologies, and in particular, to a memory testing method, a memory testing system, and a computer readable storage medium.
Background
With the increasing degree of digitization, the demands of production design on servers and storage devices are increasing, and the reliability of the memory in the devices directly affects the reliability of the device as a whole. A large number of memory requirements and advanced manufacturing processes place higher demands on memory testing.
There is a related art method for testing a memory under a BIOS (Basic Input Output System ) that is performed under the BIOS. The test algorithm is built in the source code of the BIOS, and when a new test algorithm is required or an existing test algorithm is required to be modified, the BIOS is required to be modified. The memory test on the BIOS cannot directly communicate with the host computer through the network, so that after entering the operating system, configuration of other tests and collection of logs are required, which not only lengthens the overall test time, but also increases the test cost because the operating system has to configure a hard disk for the test.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a memory testing method, a memory testing system and a computer readable storage medium, which can realize direct communication with a host under the premise of not entering an operating system, thereby saving testing cost and improving testing efficiency.
In a first aspect, an embodiment of the present invention provides a memory testing method, applied to a memory testing system, where a unified extensible firmware interface is installed on the memory testing system, the method includes:
receiving the information of the tested memory through the unified extensible firmware interface;
Receiving a first test instruction;
obtaining a custom test configuration according to the first test instruction and the tested memory information;
configuring the tested memory according to the custom test configuration;
and testing the configured tested memory to obtain a test result.
In some embodiments, the configuring the tested memory according to the custom test configuration includes: obtaining a custom algorithm, preset voltage and preset time sequence according to the custom test configuration; and configuring parameters of the tested memory according to the self-defining algorithm, the preset voltage and the preset time sequence.
In some embodiments, the testing the configured tested memory to obtain a test result includes testing the tested memory according to a preset default algorithm to obtain feedback information; obtaining a second test instruction according to the feedback information; invoking the custom algorithm according to the second test instruction; and testing the tested memory according to the self-defined algorithm to obtain a test result.
In some embodiments, after the configuring the tested memory according to the custom test configuration, the method further includes: and storing the custom test configuration to a database.
In some embodiments, the measured memory information includes memory bit information, memory temperature, memory serial presence detect information, memory current timing configuration, and voltage configuration.
In some embodiments, the method further comprises: and when the test fails, algorithm information, memory fault address information and temperature information are obtained according to the test result.
In some embodiments, the method further comprises: obtaining the memory fault address information according to the test result; and retesting the corresponding fault part memory according to the memory fault address information.
In some embodiments, the method further comprises: and generating a test log according to the test result.
In a second aspect, an embodiment of the present invention provides a memory test system, where a unified extensible firmware interface is installed on the memory test system, the system includes:
the information module is used for receiving the information of the tested memory through the unified extensible firmware interface;
The receiving module is used for receiving a first test instruction;
The processing module is used for obtaining custom test configuration according to the first test instruction and the tested memory information;
the configuration module is used for configuring the tested memory according to the custom test configuration;
and the test module is used for testing the configured tested memory to obtain a test result.
In some embodiments, the first test instruction includes controlling the start of the test, the end of the test, and adjustments to temperature, voltage, and timing.
In a third aspect, an embodiment of the present invention provides a computer readable storage medium storing a computer program, where the computer program implements the memory testing method according to the first aspect when the computer program is executed by a processor.
The embodiment of the invention comprises the following steps: firstly, the tested memory information is received through a unified extensible firmware interface installed on a memory test system. And then receiving a first test instruction for starting the memory test, and obtaining the custom test configuration according to the first test instruction and the information of the tested memory, so as to perform parameter configuration before testing on the tested memory according to the custom test configuration. After configuration is completed, the tested memory is tested, and a corresponding test result is obtained. According to the scheme provided by the embodiment of the invention, the information of the tested memory and the custom test configuration are obtained through unifying the extensible firmware interface, so that the parameter configuration and the memory test are carried out on the tested memory, and the memory occupation caused by the need of entering an operating system in the memory test carried out under the BIOS is avoided. The method can realize the test of the memory without entering an operating system, saves test time, can flexibly configure specific test parameters aiming at the tested object according to different tested objects, and improves the coverage and flexibility of the memory test.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and do not limit the invention.
FIG. 1 is a flow chart of a memory testing method according to an embodiment of the present invention;
FIG. 2 is a flow chart of a parameter configuration provided by an embodiment of the present invention;
FIG. 3 is a flow chart of a call custom algorithm provided by an embodiment of the present invention;
FIG. 4 is a flow chart of retesting provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a memory test process according to an embodiment of the present invention;
Fig. 6 is a block diagram of a memory test system according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It should be noted that although functional block division is performed in a block diagram and logical order is shown in a flowchart, in some cases, steps shown or described may be performed in a different order than block division in a block, or order in a flowchart. The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
The memory testing method and the application scenario described in the embodiments of the present invention are for more clearly describing the technical solution provided by the embodiments of the present invention, and do not constitute a limitation on the technical solution provided by the embodiments of the present invention, and as a person skilled in the art can know that, with the evolution of the memory testing field and the appearance of a new application scenario, the technical solution provided by the embodiments of the present invention is applicable to similar technical problems.
As shown in fig. 1, fig. 1 is a flowchart of a memory testing method according to an embodiment of the present invention. It is to be understood that the first aspect of the present invention provides a memory testing method, including but not limited to step S100, step S200, step S300, step S400 and step S500.
Step S100, receiving the tested memory information through the unified extensible firmware interface.
Step S200, a first test instruction is received.
Step S300, obtaining the self-defined test configuration according to the first test instruction and the tested memory information.
Step S400, according to the self-defined test configuration, the tested memory is configured.
Step S500, testing the configured tested memory to obtain a test result.
It will be appreciated that in the present method, the memory information under test is first received via a unified extensible firmware interface installed on the memory test system. Then, a first test instruction for starting the memory test is received. Since a plurality of different combinations between the first test instruction and the tested memory information are preset in the system, the combinations respectively correspond to different custom test configurations. Therefore, the system can call the corresponding custom test configuration according to the first test instruction and the information of the tested memory, so that the parameter configuration before the tested memory is tested according to the custom test configuration. After configuration is completed, the tested memory is tested, and a corresponding test result is obtained. According to the memory testing method, the testing process is executed under the unified extensible firmware interface (Unified Extensible FIRMWARE INTERFACE, UEFI) platform, an operating system is not required to be accessed, hard disk storage is not required, and testing time is saved; meanwhile, the method can realize configuration of relevant parameters such as voltage and time sequence, and the testing capability is stronger compared with a memory testing method under an operating system platform. Compared with the memory test method on the BIOS, the method not only can flexibly configure according to different tested objects, but also can call an extended memory algorithm, so that more test algorithm tests independent of the BIOS are realized; the coverage and flexibility of the test are improved.
It should be noted that UEFI is a personal computer system specification, which is used to define a software interface between an operating system and system firmware, and is used as an alternative to BIOS. The extensible firmware interface is responsible for powering on self-tests, contacting the operating system, and providing an interface to connect the operating system to the hardware. Is a personal computer system specification that defines a software interface between an operating system and system firmware as an alternative to BIOS. The extensible firmware interface is responsible for powering on self-tests, contacting the operating system, and providing an interface to connect the operating system to the hardware. The UEFI interface provided by the invention can independently call and configure the testing algorithm under the UEFI, and the memory testing algorithm and hardware are decoupled and can adapt to different CPU models under the same architecture, so that the coverage of the test is increased.
It is understood that the measured memory information in the present invention includes, but is not limited to, bit information, SPD (SERIAL PRESENCE DETECT ) information, temperature, voltage, timing, and other parameter information. The bit information is used for representing whether the memory is normally powered on after being inserted into the memory slot; SPD information is stored in an erasable and writable eeprom (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY, electrically erasable and programmable read-only memory) on the memory module, in which a lot of important information of the memory, such as the chip and module manufacturer, operating frequency, operating voltage, speed, capacity, voltage and row and column address bandwidth, etc. parameters of the memory are recorded. The SPD information is generally written into the eporom chip by the memory module manufacturer according to the actual performance of the memory chip before shipment.
It can be understood that after the test is completed, the system generates a test log according to the current test result, where the test log includes whether the test algorithm passes, algorithm information used when the test fails, memory failure address information when the test fails, and parameters such as temperature, voltage, and time sequence when the test fails.
It should be noted that, the first test instruction provided in this embodiment includes a configuration indicating a start of a test, an end of the test, and parameters such as a temperature, a voltage, a timing, and the like. The content of the first test instruction is not particularly limited in the present invention.
As shown in fig. 2, fig. 2 is a flowchart of parameter configuration provided in an embodiment of the present invention. It will be appreciated that step S400 in the embodiment shown in fig. 1 includes, but is not limited to, step S410 and step S420.
Step S410, obtaining a custom algorithm, a preset voltage and a preset time sequence according to the custom test configuration.
Step S420, the parameters of the tested memory are configured according to the self-defining algorithm, the preset voltage and the preset time sequence.
It can be understood that, after the custom test configuration is obtained, step S410 is required to be executed, and the custom algorithm, the preset voltage and the preset time sequence carried in the configuration information are obtained in the custom test configuration. After obtaining the parameters to be configured, step S420 is executed, where the custom algorithm is stored in the system for use in the subsequent test, and the preset voltage and the preset time sequence are set to the current voltage value and the time sequence value of the tested memory. Different combinations of the tested memory information and the test instructions correspond to different custom test configurations respectively, so that flexible configuration according to different tested objects is realized, and the test accuracy is improved.
As shown in fig. 3, fig. 3 is a flowchart of a call custom algorithm provided in an embodiment of the present invention. It should be understood that the step S500 in the embodiment shown in fig. 1 specifically includes, but is not limited to, step S510, step S520, step S530, and step S540.
Step S510, testing the tested memory according to a preset default algorithm to obtain feedback information.
Step S520, obtaining a second test instruction according to the feedback information.
Step S530, calling a self-defined algorithm according to the second test instruction.
Step S540, testing the tested memory according to the self-defined algorithm to obtain a test result.
It can be understood that after the memory test is started, step S510 is first executed to test the tested memory according to a default algorithm preset in the system, and obtain feedback information. The feedback information obtained at this time is a result obtained according to a default algorithm preset by the system, and only the memory performance can be preliminarily reflected, but the specific condition of the current memory cannot be accurately reflected, so that the feedback information also needs to be sent to the host end, a second test instruction from the host end is obtained, and at this time, the custom algorithm in the custom test configuration is called according to the requirement in the second test instruction. Because the custom algorithm is stored in the system and is a testing algorithm independent of the BIOS, the custom algorithm can be directly called to test the tested memory, and a testing result is obtained. The test result obtained at this time uses the second test instruction after the feedback information adjustment and the parameters specially configured according to the information of the tested memory, so that the tested memory can be flexibly tested, and the test capability is stronger compared with the memory test method under the operating system platform.
As shown in fig. 4, fig. 4 is a flowchart of retesting according to an embodiment of the present invention. It can be understood that the memory testing method provided by the present invention further includes, but is not limited to, step S610 and step S620.
Step S610, obtaining the memory fault address information according to the test result.
Step S620, retesting the corresponding fault part memory according to the memory fault address information.
It can be understood that after the test is completed, the host side determines whether to retest a portion of the memory according to the test result. Firstly, step S610 is executed to obtain the memory failure address information in the current test according to the test result, and step S620 is executed to retest the memory of the corresponding failure portion according to the memory failure address information.
It should be noted that, the system is preset with a starting condition related to retesting. For example, three tests are required for each address in the memory in one test, and the preset condition in the system is "when a fault is detected at least twice in three tests of a certain address, the test is performed again on the part of the memory. The invention is not limited to specific conditions for retesting.
As shown in fig. 5, fig. 5 is a schematic diagram illustrating a memory test process according to an embodiment of the invention. It is understood that the memory testing method provided by the present invention further includes, but is not limited to, step S710, step S720, step S730, step S740, step S750, step S760, step S770, and step S780.
In step S710, the memory test system is powered on.
In step S720, the tested memory information before the memory test is obtained.
Step S730, the tested memory information is sent to the host, and the test configuration instruction of the host is obtained.
Step S740, performing algorithm configuration, voltage configuration and timing configuration on the memory test.
Step S750, restarting the memory test system, and performing memory algorithm test to obtain feedback information.
Step 760, the feedback information is sent to the host, and the test instruction is acquired, and the custom algorithm is invoked.
Step S770, performing a test by using a custom algorithm, and sending the obtained test result to the host.
In step S780, a test completion command from the host is received.
It is understood that when the memory needs to be tested, step S710 is first performed to power up the memory test system. In this step, the system will call and run a unified extensible firmware interface package (UEFI package) pre-stored on the host side. And then executing step S720, cleaning the current test environment through the unified extensible firmware interface, and acquiring the current tested memory information. After obtaining the tested memory information, steps S730 to S740 are executed, the tested memory information is sent to the host, then a test configuration instruction from the host is received, and the configuration of parameters such as a custom algorithm, voltage, time sequence and the like is performed on the current memory test according to the test configuration instruction. After the configuration is completed, the system stores the configuration information of the time. Step S750 is executed, the memory test system is restarted, and the default algorithm preset in the system is used for testing the memory, so that corresponding feedback information is obtained. And then executing steps 760 to 770, sending the feedback information to the host, receiving the test instruction sent by the host, calling the custom algorithm to test the memory, and sending the obtained test result to the host. Finally, the host end judges whether to retest part of the memory according to the test result, if the test result meets retest conditions, the steps S740 to S770 are re-executed for the part of the memory which has faults, namely retest is carried out; if the test result reflects that the memory state is normal, the host sends a test ending instruction to complete the test.
As shown in fig. 6, fig. 6 is a block diagram of a memory test system according to an embodiment of the present invention. It is to be understood that the second aspect of the present invention proposes a memory test system 100, which includes, but is not limited to, an information module 110, a receiving module 120, a processing module 130, a configuration module 140, and a test module 150. The information module 110 is configured to receive the measured memory information through a unified extensible firmware interface; a receiving module 120, configured to receive a first test instruction; the processing module 130 is configured to obtain a custom test configuration according to the first test instruction and the tested memory information; the configuration module 140 is configured to configure the tested memory according to the custom test configuration; and the test module 150 is used for testing the configured tested memory to obtain a test result. The system obtains the information of the tested memory and the custom test configuration through unifying the extensible firmware interface, so that the parameter configuration and the memory test are carried out on the tested memory, and the memory occupation caused by the need of entering an operating system in the memory test carried out under the BIOS is avoided. The method can realize communication with an external host computer and testing of the memory without entering an operating system, saves testing time, can flexibly configure specific testing parameters for the tested object according to different tested objects, and improves coverage and flexibility of the memory test.
It will be appreciated that the first test instructions presented in this embodiment include, but are not limited to, control of test initiation, test termination, and adjustments to temperature, voltage, and timing.
In addition, the embodiment of the invention provides a memory test system. The memory test system may include a terminal device and an HTTP server. The memory test system includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the memory test method in the above embodiments when executing the computer program.
The memory is used as a non-transitory computer readable storage medium for storing non-transitory software programs and non-transitory computer executable programs, such as the memory test method in the above embodiments of the invention. The processor implements the memory testing method in the above-described embodiments of the present invention by running a non-transitory software program and instructions stored in the memory.
It should be noted that, the storage medium proposed by the present invention can record in real time during the test process. When abnormal conditions such as power failure occur in the test process, the test process is interrupted, and the storage medium can store the information of the latest test point before interruption. When the system is powered on again, the test system restores to the nearest test point to continue the test task according to the test point information stored in the storage medium.
The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the memory data area may store data and the like required to perform the memory test method in the above-described embodiments. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. It should be noted that the memory may alternatively include a memory located remotely from the processor, and these remote memories may be connected to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The non-transitory software program and instructions required to implement the memory test method in the above embodiments are stored in the memory and when executed by the one or more processors, perform the memory test method in the above embodiments, for example, perform at least one of method steps S100 through S500 in fig. 1, method steps S410 through S420 in fig. 2, method steps S510 through S540 in fig. 3, method steps S610 through S620 in fig. 4, and method steps S710 through S780 in fig. 5, described above.
The present invention also provides a computer-readable storage medium storing computer-executable instructions for causing a computer to perform a memory testing method as in the above-described embodiments, for example, at least one of the method steps S100 to S500 in fig. 1, the method steps S410 to S420 in fig. 2, the method steps S510 to S540 in fig. 3, the method steps S610 to S620 in fig. 4, and the method steps S710 to S780 in fig. 5, which are described above.
The above described apparatus embodiments are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the embodiments described above, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention.
Claims (3)
1. A memory test method applied to a memory test system, wherein a unified extensible firmware interface is installed on the memory test system, the method comprising:
receiving the information of the tested memory through the unified extensible firmware interface;
Receiving a first test instruction;
obtaining a custom test configuration according to the first test instruction and the tested memory information;
configuring the tested memory according to the custom test configuration;
Testing the configured tested memory to obtain a test result;
The configuring the tested memory according to the custom test configuration comprises the following steps:
obtaining a custom algorithm, preset voltage and preset time sequence according to the custom test configuration;
Configuring parameters of the tested memory according to the self-defining algorithm, the preset voltage and the preset time sequence;
The testing of the configured tested memory to obtain a test result comprises the following steps:
testing the tested memory according to a preset default algorithm to obtain feedback information;
obtaining a second test instruction according to the feedback information;
invoking the custom algorithm according to the second test instruction;
testing the tested memory according to the self-defined algorithm to obtain a test result;
After the tested memory is configured according to the custom test configuration, the method further comprises:
Storing the custom test configuration to a database;
The tested memory information comprises memory bit information, memory temperature, memory serial presence detection information, current time sequence configuration and voltage configuration of a memory;
The method further comprises the steps of:
when the test fails, algorithm information, memory fault address information and temperature information are obtained according to the test result;
The method further comprises the steps of:
obtaining the memory fault address information according to the test result;
Retesting the corresponding fault part memory according to the memory fault address information;
The method further comprises the steps of:
and generating a test log according to the test result.
2. A memory test system having a unified extensible firmware interface installed thereon, the system comprising:
the information module is used for receiving the information of the tested memory through the unified extensible firmware interface;
The receiving module is used for receiving a first test instruction;
The processing module is used for obtaining custom test configuration according to the first test instruction and the tested memory information;
the configuration module is used for configuring the tested memory according to the custom test configuration;
The test module is used for testing the configured tested memory to obtain a test result;
The first test instruction comprises control of test start, test end and adjustment of temperature, voltage and time sequence;
configuring the tested memory according to the self-defined test configuration, comprising:
Obtaining a custom algorithm, preset voltage and preset time sequence according to the custom test configuration;
configuring parameters of the tested memory according to a custom algorithm, preset voltage and preset time sequence;
Testing the configured tested memory to obtain a test result, wherein the test result comprises the following steps:
testing the tested memory according to a preset default algorithm to obtain feedback information;
obtaining a second test instruction according to the feedback information;
calling a custom algorithm according to the second test instruction;
Testing the tested memory according to a custom algorithm to obtain a test result;
After configuring the tested memory according to the custom test configuration, the method further comprises:
Storing the custom test configuration to a database;
The tested memory information comprises memory bit information, memory temperature, memory serial presence detection information, current time sequence configuration and voltage configuration of the memory;
The method further comprises the steps of:
When the test fails, algorithm information, memory fault address information and temperature information are obtained according to the test result;
The method further comprises the steps of:
obtaining memory fault address information according to the test result;
retesting the corresponding fault part memory according to the memory fault address information;
The method further comprises the steps of:
and generating a test log according to the test result.
3. A computer readable storage medium, storing a computer program which, when executed by a processor, implements the memory testing method of claim 1.
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