CN115841842A - Memory test method, system and computer readable storage medium - Google Patents
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Abstract
The invention provides a memory test method, a system and a computer readable storage medium, wherein the method is applied to a memory test system, a unified extensible firmware interface is installed on the memory test system, and the method comprises the following steps: receiving the tested memory information through a unified extensible firmware interface; receiving a first test instruction; obtaining a user-defined test configuration according to the first test instruction and the tested memory information; configuring the tested memory according to the user-defined test configuration; and testing the configured tested memory to obtain a test result. The invention can realize the test of the memory without entering an operating system, saves the test time, can flexibly configure specific test parameters aiming at the tested object according to the difference of the tested object, and improves the coverage and the flexibility of the memory test.
Description
Technical Field
The present invention relates to the field of memory testing technologies, and in particular, to a memory testing method and system, and a computer-readable storage medium.
Background
With the increase of the digitization degree, the requirements of production design on a server and a storage device are higher and higher, and the reliability of the memory in the device directly influences the overall reliability of the device. The large memory requirements and advanced manufacturing processes place higher demands on memory testing.
In the related art, there is a memory test method which is performed under a BIOS (Basic Input Output System) and is built in the BIOS. The testing algorithm is built in the source code of the BIOS, and when the testing algorithm needs to be added or the existing testing algorithm needs to be modified, the BIOS needs to be modified. The memory test on the BIOS cannot directly perform network communication with the host, and therefore, configuration of other tests and collection of logs are required after the operating system is entered, which not only lengthens the overall test time, but also increases the test cost because the operating system must configure a hard disk for the operating system.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
Embodiments of the present invention provide a memory testing method, system and computer-readable storage medium, which can implement direct communication with a host without entering an operating system, save testing cost, and improve testing efficiency.
In a first aspect, an embodiment of the present invention provides a memory test method, which is applied to a memory test system, where a unified extensible firmware interface is installed on the memory test system, and the method includes:
receiving the tested memory information through the unified extensible firmware interface;
receiving a first test instruction;
obtaining a user-defined test configuration according to the first test instruction and the tested memory information;
configuring the tested memory according to the self-defined test configuration;
and testing the configured tested memory to obtain a test result.
In some embodiments, the configuring the tested memory according to the custom test configuration includes: obtaining a custom algorithm, a preset voltage and a preset time sequence according to the custom test configuration; and configuring the parameters of the tested memory according to the self-defined algorithm, the preset voltage and the preset time sequence.
In some embodiments, the testing the configured tested memory to obtain the test result includes testing the tested memory according to a preset default algorithm to obtain feedback information; obtaining a second test instruction according to the feedback information; calling the self-defined algorithm according to the second test instruction; and testing the tested memory according to the custom algorithm to obtain a test result.
In some embodiments, after configuring the tested memory according to the custom test configuration, the method further includes: and storing the custom test configuration to a database.
In some embodiments, the measured memory information includes memory bit information, memory temperature, memory serial presence detect information, current timing configuration and voltage configuration of the memory.
In some embodiments, the method further comprises: and when the test fails, obtaining algorithm information, memory fault address information and temperature information according to the test result.
In some embodiments, the method further comprises: obtaining the memory fault address information according to the test result; and according to the memory fault address information, retesting the corresponding fault part of the memory.
In some embodiments, the method further comprises: and generating a test log according to the test result.
In a second aspect, an embodiment of the present invention provides a memory test system, where a unified extensible firmware interface is installed on the memory test system, and the system includes:
the information module is used for receiving the tested memory information through the unified extensible firmware interface;
the receiving module is used for receiving a first test instruction;
the processing module is used for obtaining a self-defined test configuration according to the first test instruction and the tested memory information;
the configuration module is used for configuring the tested memory according to the user-defined test configuration;
and the test module is used for testing the configured tested memory to obtain a test result.
In some embodiments, the first test instruction includes control of test start, test end, and adjustments to temperature, voltage, and timing.
In a third aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the memory testing method according to the first aspect is implemented.
The embodiment of the invention comprises the following steps: firstly, the tested memory information is received through a unified extensible firmware interface installed on a memory test system. And then receiving a first test instruction for starting the memory test, and obtaining a custom test configuration according to the first test instruction and the tested memory information, so as to configure the parameters of the tested memory before the test according to the custom test configuration. And after the configuration is finished, testing the tested memory and obtaining a corresponding test result. According to the scheme provided by the embodiment of the invention, the tested memory information and the custom test configuration are obtained through the unified extensible firmware interface, so that the parameter configuration and the memory test are carried out on the tested memory, and the memory occupation caused by the need of entering the operating system in the memory test under the BIOS is avoided. The method can realize the test of the memory without entering an operating system, saves the test time, can flexibly configure specific test parameters aiming at the tested object according to the difference of the tested object, and improves the coverage and the flexibility of the memory test.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a flowchart of a memory testing method according to an embodiment of the present invention;
FIG. 2 is a flow chart of parameter configuration provided by an embodiment of the present invention;
FIG. 3 is a flow chart of invoking a custom algorithm provided by an embodiment of the present invention;
FIG. 4 is a flow chart of a retest provided by an embodiment of the present invention;
FIG. 5 is a diagram illustrating a memory test process according to an embodiment of the present invention;
fig. 6 is a block diagram of a memory test system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that although functional block partitions are illustrated in block diagrams and logical sequences are illustrated in flowcharts, in some cases, steps shown or described may be performed in a different block partition or sequence in flowcharts. The terms first, second and the like in the description and in the claims, as well as in the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
The memory testing method and the application scenario described in the embodiments of the present invention are for more clearly illustrating the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided in the embodiments of the present invention, and it is known to those skilled in the art that the technical solutions provided in the embodiments of the present invention are also applicable to similar technical problems along with the evolution of the memory testing field and the emergence of new application scenarios.
As shown in fig. 1, fig. 1 is a flowchart of a memory testing method according to an embodiment of the present invention. It is understood that the first aspect of the present invention provides a memory testing method, including but not limited to step S100, step S200, step S300, step S400, and step S500.
Step S100, receiving the tested memory information through the unified extensible firmware interface.
Step S200, receiving a first test instruction.
And step S300, obtaining a custom test configuration according to the first test instruction and the tested memory information.
And step S400, configuring the tested memory according to the user-defined test configuration.
Step S500, testing the configured tested memory to obtain a test result.
It is understood that the memory information under test is first received by the unified extensible firmware interface installed on the memory test system in the method. And then receiving a first test instruction for starting the memory test. The system is preset with various different combinations between the first test instruction and the tested memory information, and the combinations respectively correspond to different custom test configurations. Therefore, the system can call the corresponding custom test configuration according to the first test instruction and the tested memory information, so as to configure the parameters of the tested memory before testing according to the custom test configuration. And after the configuration is finished, testing the tested memory and obtaining a corresponding test result. According to the memory testing method provided by the invention, the testing process is executed under a Unified Extensible Firmware Interface (UEFI) platform, an operating system is not required to be accessed, and hard disk storage is not required, so that the testing time is saved; meanwhile, the method can realize the configuration of relevant parameters such as voltage, time sequence and the like, and the testing capability is stronger compared with that of a memory testing method under an operating system platform. Compared with a memory test method on the BIOS, the method not only can carry out flexible configuration according to different tested objects, but also can carry out extended memory algorithm calling, thereby realizing more test algorithm tests independent of the BIOS; the coverage and flexibility of the test are improved.
It should be noted that UEFI is a specification of a personal computer system, which is used to define a software interface between an operating system and system firmware, as an alternative to BIOS. The extensible firmware interface is responsible for power-on self-test, contacting the operating system, and providing an interface to connect the operating system to the hardware. The system specification of the personal computer is used for defining a software interface between an operating system and system firmware as a replacement scheme of a BIOS. The extensible firmware interface is responsible for power-on self-test, contacting the operating system, and providing an interface to connect the operating system to the hardware. The UEFI interface provided by the invention can independently call and configure the test algorithms under the UEFI, and the memory test algorithms are decoupled from hardware and can be adapted to different CPU models under the same architecture, so that the test coverage is increased.
It is understood that the measured memory information mentioned in the present invention includes, but is not limited to, presence information, SPD (serial presence detect) information, and parameter information such as temperature, voltage, and timing. The in-place information is used for representing whether the memory is normally powered on after being inserted into the memory slot; SPD information is stored in an Erasable Programmable read only memory (eeprom) on the memory module, and records many important information of the memory, such as chip and module manufacturers of the memory, operating frequency, operating voltage, speed, capacity, voltage, and row and column address bandwidth. SPD information is typically written into an eeprom chip by a memory module manufacturer according to the actual performance of the memory chip before the memory module manufacturer leaves the factory.
It can be understood that, after the test is completed, the system will generate a test log according to the current test result, and the test log includes whether the test algorithm passes or not, the algorithm information used when the test fails, the memory fault address information when the test fails, and the conditions of the parameters such as temperature, voltage, and timing sequence when the test fails.
It should be noted that the first test command proposed in this embodiment includes a configuration indicating the start of the test, the end of the test, and parameters such as temperature, voltage, and timing. The present invention does not specifically limit the content of the first test instruction.
As shown in fig. 2, fig. 2 is a flowchart of parameter configuration according to an embodiment of the present invention. It is understood that step S400 in the embodiment shown in fig. 1 further includes, but is not limited to, step S410 and step S420.
And S410, obtaining a custom algorithm, a preset voltage and a preset time sequence according to the custom test configuration.
Step S420, configuring parameters of the memory to be tested according to the custom algorithm, the preset voltage and the preset time sequence.
It can be understood that, after the custom test configuration is obtained, step S410 needs to be executed to obtain the custom algorithm, the preset voltage and the preset time sequence carried in the configuration information in the custom test configuration. After the parameters to be configured are obtained, step S420 is executed to store the custom algorithm in the system for subsequent testing, and set the preset voltage and the preset time sequence as the current voltage value and the time sequence value of the tested memory. Different combinations of the tested memory information and the test instruction respectively correspond to different user-defined test configurations, so that flexible configuration is realized according to different tested objects, and the test accuracy is improved.
As shown in fig. 3, fig. 3 is a flowchart of invoking a custom algorithm according to an embodiment of the present invention. It is understood that step S500 in the embodiment shown in fig. 1 specifically includes, but is not limited to, step S510, step S520, step S530, and step S540.
Step S510, testing the tested memory according to a preset default algorithm to obtain feedback information.
And step S520, obtaining a second test instruction according to the feedback information.
And step S530, calling a custom algorithm according to the second test instruction.
And S540, testing the tested memory according to the custom algorithm to obtain a test result.
It can be understood that, after the memory is initially tested, step S510 is first executed to test the tested memory according to a default algorithm preset in the system and obtain the feedback information. The feedback information obtained at this time is a result obtained according to a default algorithm preset by the system, and only the memory performance can be preliminarily reflected, but the specific situation of the current memory cannot be accurately reflected, so that the feedback information needs to be sent to the host side, a second test instruction from the host side is obtained, and then the custom algorithm in the custom test configuration is called according to the requirement in the second test instruction. Because the custom algorithm is stored in the system and is a test algorithm independent of the BIOS, the custom algorithm can be directly called to test the tested memory to obtain a test result. The test result obtained at this time uses the second test instruction after the feedback information adjustment and the parameters specially configured according to the tested memory information, so that the tested memory can be flexibly detected, and the test capability of the method is stronger compared with a memory test method under an operating system platform.
As shown in fig. 4, fig. 4 is a flowchart of retesting provided in the embodiment of the present invention. It can be understood that the memory test method provided by the present invention further includes, but is not limited to, step S610 and step S620.
Step S610, obtaining the memory fault address information according to the test result.
Step S620, retest the corresponding failed memory according to the memory failure address information.
It can be understood that after the test is completed, the host determines whether or not to retest a part of the memory according to the test result. Firstly, step S610 is executed, the memory failure address information in the current test is obtained according to the test result, and step S620 is executed, and the memory of the corresponding failure part is retested according to the memory failure address information.
It should be noted that the system is preset with a start condition for retesting. For example, each address in the memory needs to be tested three times in one test, and the preset condition in the system is "when a fault is detected at least twice in three tests for a certain address, the part of the memory is tested again". The present invention does not limit the specific conditions for retesting.
As shown in fig. 5, fig. 5 is a schematic diagram of a memory test processing procedure according to an embodiment of the present invention. It is understood that the memory test method provided by the present invention further includes, but is not limited to, step S710, step S720, step S730, step S740, step S750, step S760, step S770, and step S780.
In step S710, the memory test system is powered on.
Step S720, obtaining the tested memory information before the memory test.
Step S730, sending the tested memory information to the host, and obtaining a test configuration instruction from the host.
Step S740, performing algorithm configuration, voltage configuration and timing configuration on the memory test.
Step S750, restart the memory test system, and perform the memory algorithm test to obtain the feedback information.
And step S760, sending the feedback information to the host side, acquiring a test instruction and calling a custom algorithm.
And step S770, testing by using a custom algorithm, and sending the obtained test result to a host terminal.
Step S780, receiving a test completion instruction from the host.
It can be understood that, when the memory needs to be tested, step S710 needs to be executed first to power up the memory test system. In this step, the system calls a unified extensible firmware interface software package (UEFI software package) pre-stored in the host and runs it. Then, step S720 is executed, the current testing environment is cleaned through the unified extensible firmware interface, and the current tested memory information is obtained. After the tested memory information is obtained, steps S730 to S740 are executed, the tested memory information is sent to the host, then a test configuration instruction from the host is received, and the configuration of parameters such as a custom algorithm, voltage, timing sequence and the like is performed on the memory test according to the test configuration instruction. And after the configuration is finished, the system stores the current configuration information. And step S750 is executed, the memory test system is restarted, and the memory is tested by using a default algorithm preset in the system, and corresponding feedback information is obtained. And then executing steps S760 to S770, sending the feedback information to the host, receiving a test instruction sent by the host, calling a custom algorithm to test the memory, and sending the obtained test result to the host. Finally, the host end judges whether the partial memory needs to be retested according to the test result, if the test result meets the retesting condition, the steps S740 to S770 are executed again aiming at the partial memory with the fault, namely the retesting is carried out; and if the test result reflects that the memory state is normal, the host end sends a test ending instruction to finish the test.
As shown in fig. 6, fig. 6 is a block diagram of a memory test system according to an embodiment of the present invention. It is understood that the second aspect of the present invention provides a memory test system 100, which includes, but is not limited to, an information module 110, a receiving module 120, a processing module 130, a configuration module 140, and a test module 150. The information module 110 is configured to receive the measured memory information through a unified extensible firmware interface; a receiving module 120, configured to receive a first test instruction; the processing module 130 is configured to obtain a custom test configuration according to the first test instruction and the measured memory information; the configuration module 140 is configured to configure the memory under test according to the custom test configuration; and the test module 150 is configured to test the configured tested memory to obtain a test result. The system acquires the information of the tested memory and self-defined test configuration through the unified extensible firmware interface, so that parameter configuration and memory test are carried out on the tested memory, and memory occupation caused by the need of entering an operating system in the memory test under the BIOS is avoided. The method can realize communication with an external host and test of the memory without entering an operating system, saves test time, can flexibly configure specific test parameters aiming at the tested object according to different tested objects, and improves the coverage and flexibility of memory test.
It is understood that the first test command proposed in the present embodiment includes, but is not limited to, controlling the start of the test, the end of the test, and adjusting the temperature, voltage, and timing.
In addition, the embodiment of the invention provides a memory test system. The memory test system can comprise a terminal device and an HTTP server. The memory test system comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, and the memory test method in the embodiment is realized when the processor executes the computer program.
The memory is used as a non-transitory computer readable storage medium for storing non-transitory software programs and non-transitory computer executable programs, such as the memory test method in the above embodiments of the present invention. The processor implements the memory test method in the above embodiments of the present invention by running the non-transitory software program and the instructions stored in the memory.
It should be noted that the storage medium proposed by the present invention may be recorded in real time during the testing process. When abnormal conditions such as power failure and the like occur in the test process, the test process is interrupted, and the storage medium can store the information of the nearest test point before the interruption. When the system is powered on again, the test system restores to the nearest test point to continue the test task according to the test point information stored in the storage medium.
The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data and the like required for executing the memory test method in the above-described embodiments. Further, the memory may include high speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid state storage device. It should be noted that the memory may optionally include memory located remotely from the processor, and that such remote memory may be coupled to the terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The non-transitory software program and instructions required for implementing the memory test method in the above embodiments are stored in the memory, and when executed by one or more processors, the memory test method in the above embodiments is executed, for example, at least one of the method steps S100 to S500 in fig. 1, the method steps S410 to S420 in fig. 2, the method steps S510 to S540 in fig. 3, the method steps S610 to S620 in fig. 4, and the method steps S710 to S780 in fig. 5 described above is executed.
The present invention also provides a computer-readable storage medium storing computer-executable instructions for causing a computer to execute the memory testing method in the above-described embodiments, for example, to execute at least one of the method steps S100 to S500 in fig. 1, the method steps S410 to S420 in fig. 2, the method steps S510 to S540 in fig. 3, the method steps S610 to S620 in fig. 4, and the method steps S710 to S780 in fig. 5 described above.
The above-described embodiments of the apparatus are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may also be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, and the present invention is not limited to the embodiments described above, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.
Claims (11)
1. A memory test method is applied to a memory test system, a unified extensible firmware interface is installed on the memory test system, and the method comprises the following steps:
receiving the tested memory information through the unified extensible firmware interface;
receiving a first test instruction;
obtaining a user-defined test configuration according to the first test instruction and the tested memory information;
configuring the tested memory according to the self-defined test configuration;
and testing the configured tested memory to obtain a test result.
2. The method according to claim 1, wherein the configuring the memory under test according to the custom test configuration comprises:
obtaining a custom algorithm, a preset voltage and a preset time sequence according to the custom test configuration;
and configuring the parameters of the tested memory according to the custom algorithm, the preset voltage and the preset time sequence.
3. The method according to claim 2, wherein the testing the configured tested memory to obtain the test result comprises:
testing the tested memory according to a preset default algorithm to obtain feedback information;
obtaining a second test instruction according to the feedback information;
calling the self-defined algorithm according to the second test instruction;
and testing the tested memory according to the custom algorithm to obtain a test result.
4. The memory test method according to claim 2, after configuring the memory under test according to the custom test configuration, further comprising:
and storing the custom test configuration to a database.
5. The method according to claim 3, wherein the tested memory information comprises memory bit information, memory temperature, memory serial presence detect information, current timing configuration and voltage configuration of the memory.
6. The memory test method of claim 3, further comprising:
and when the test fails, obtaining algorithm information, memory fault address information and temperature information according to the test result.
7. The memory test method of claim 6, further comprising:
obtaining the memory fault address information according to the test result;
and according to the memory fault address information, retesting the corresponding fault part of the memory.
8. The memory test method of claim 6, further comprising:
and generating a test log according to the test result.
9. A memory test system having a unified extensible firmware interface installed thereon, the system comprising:
the information module is used for receiving the tested memory information through the unified extensible firmware interface;
the receiving module is used for receiving a first test instruction;
the processing module is used for obtaining a self-defined test configuration according to the first test instruction and the tested memory information;
the configuration module is used for configuring the tested memory according to the user-defined test configuration;
and the test module is used for testing the configured tested memory to obtain a test result.
10. The memory test system of claim 9, wherein the first test command comprises control of test start, test end, and adjustments to temperature, voltage, and timing.
11. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the memory testing method according to any one of claims 1 to 8.
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| CN114765051A (en) * | 2021-01-12 | 2022-07-19 | 长鑫存储技术有限公司 | Memory test method and device, readable storage medium and electronic equipment |
| CN113851183A (en) * | 2021-09-24 | 2021-12-28 | 深圳忆联信息系统有限公司 | Solid state disk testing method and device based on UEFI environment and computer equipment |
| CN114461458A (en) * | 2021-11-12 | 2022-05-10 | 苏州浪潮智能科技有限公司 | Server memory test method, system, terminal and storage medium |
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