TWI764342B - Startup status detection system and method thereof - Google Patents

Abstract

A startup status detection system and method are provided in the present invention. The startup status detection system includes a first logic processing module, a storing module, and a second logic processing module. The first logic processing module provides a startup-control signal to the second logic processing module to make the second logic processing module load a startup program stored in the storing module. The second logic processing module is configured to provide an idle signal which is a first electrical level and provide a successful signal which is a second electrical level when the second logic processing module loads the startup program successfully. The first logic processing module is configured to make the second logic processing module reloads the startup program when the first logic processing module is not received the successful signal within a status detection time.

Description

Startup state detection system and method thereof

The present invention relates to an activation state detection system and a method thereof, and more particularly, to an activation state detection system and a method thereof applied to a communication device.

With the advancement of technology, network cards have become an indispensable communication device for existing network equipment, such as server hosts, monitoring equipment, Uninterruptible Power Supply (USP), gateways, etc. , the user can manage through the independent web interface of the above-mentioned device. In order to meet the needs of users, the industry has also added many functions to the network card, so they have designed a smart network card, which can increase the field programmable The network card with the function of Field Programmable Gate Array (FPGA, hereinafter referred to as FPGA) (ie FPGA-enhanced network card) has become the mainstream of the market.

Among them, the FPGA-enhanced smart network card can provide backward compatibility, especially for hypervisor compatibility, and because it is compatible with existing network APIs and interface protocols, existing applications can be used. Programming interface and driver without further design.

Generally speaking, when the FPGA-enhanced smart network card is started, the internal FPGA needs to load a firmware file of about 1 GigaByte (GB) size stored in the external storage module, and read and execute the firmware file. During the process, if it fails, the system will not recognize the smart network card and cause system problems. Even if the system is shut down and restarted, the network card cannot be activated, but it must be completely powered off and then restarted to be successful. Restarting the network card will cause great inconvenience to users when a large number of users encounter these problems in the computer room. Therefore, the existing technology still has room for improvement.

In view of the fact that in the prior art, communication devices such as smart network cards generally need to be powered off to restart successfully, which causes inconvenience to users. One of the main objectives of the present invention is to provide an activation state detection system and a method thereof, which solve the problems mentioned in the prior art through signal transmission between two logic processing modules.

In order to solve the problems of the prior art, the necessary technical means adopted by the present invention is to provide a startup state detection system, which is applied to a communication device and includes a first logic processing module, a storage module and a second logic module. Processing modules. The first logic processing module includes an activation control unit and an activation state detection unit, and the activation control unit is used for sending an activation control signal. The activation state detection unit is electrically connected to the activation control unit and has a state detection time.

The storage module stores a start-up program, and the second logic processing module is communicatively connected to the start-up control unit, the start-up state detection unit and the storage module, and is used for sending an idle state of a first potential in an idle state The signal is used to read and execute the activation program when receiving the activation control signal, so as to send an execution success signal of a second potential different from the first potential in an execution success state.

Wherein, when the activation state detection unit receives an execution success signal of the second potential within the state detection time, it determines that the second logic processing module successfully executes the activation program, and determines that the communication device is in a successful activation state; When the state detection unit still receives the idle signal of the first potential outside the state detection time, it determines that the second logic processing module is in a failure state of activation, and sends a restart signal of a third potential to the start-up control unit, so that the start-up control unit re-sends the start-up control signal, so that the second logic processing module re-reads and executes the start-up program.

On the basis of the above necessary technical means, an auxiliary technical means derived from the present invention is that the communication device is a network card, the first logic processing module is a Complex Programmable Logic Device (CPLD) and a One of the System on a Chip (SOC), the second logic processing module is a Field Programmable Gate Array (Field Programmable Gate Array, FPGA). The first potential and the third potential are a low potential marked as 0, the second potential is a high potential marked as 1, and the state detection time is 1200 milliseconds.

On the basis of the above necessary technical means, an auxiliary technical means derived from the present invention is that the second logic processing module further includes a processing unit and an execution state judgment unit. The processing unit is communicatively connected to the activation control unit, the activation control unit and the storage module, and is used for sending an idle signal in an idle state, and is used to read and execute the activation program when the activation control signal is received, so that the execution is successful. In the state, a successful execution signal is sent. The execution state judgment unit is electrically connected to the processing unit and the activation state detection unit, and is provided with a state judgment table including the corresponding relationship between the idle state and the first potential and the corresponding relationship between the execution successful state and the second potential. When receiving the execution success signal, according to the state judgment table, the execution success signal of the second level is sent to the start-up state detection unit, and when the idle signal is received, according to the state judgment table, the first level is idle according to the state judgment table. The signal is sent to the activation state detection unit.

In order to solve the problem of the prior art, the necessary technical means adopted by the present invention is to provide an activation state detection method, which is implemented by using the above-mentioned activation state detection system. The control unit sends an activation control signal; then the second logic processing module is used to receive the activation control signal, so as to read and execute the activation program; When the logic processing module is in the successful execution state, the execution success signal of the second potential is sent. When the judgment result is yes, the activation state detection unit is used to determine that the second logic processing module has successfully executed the activation program, and determine The communication device is in a successful startup state; when the determination result is no, the startup state detection unit is used to send the restart signal of the third potential to the startup control unit, so that the startup control unit re-sends the startup control signal, and accordingly Make the second logic processing module re-read and execute the startup program.

On the basis of the above necessary technical means, an auxiliary technical means derived from the present invention is that the communication device is a network card, the first logic processing module is a Complex Programmable Logic Device (CPLD) and a One of the System on a Chip (SOC), the second logic processing module is a Field Programmable Gate Array (Field Programmable Gate Array, FPGA). The first potential and the third potential are a low potential marked as 0, the second potential is a high potential marked as 1, and the state detection time is 1200 milliseconds.

Continuing from the above, in the startup state detection system and method provided by the present invention, since the execution success signal of the second potential different from the first potential is not received within the state detection time, the first logic The processing module can directly trigger the second logic processing module to read and execute the startup program again, so that the user does not need to power off the communication device to restart the communication device, thus greatly improving the convenience of the user. and can improve the working stability of the communication device.

The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. The advantages and features of the present invention will become more apparent from the following description and the scope of the claims. It should be noted that the drawings are all in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

Please refer to the first figure. The first figure is a block diagram of a startup state detection system provided by a preferred embodiment of the present invention. As shown in the figure, the activation state detection system 1 provided by the present invention is applied to a communication device 2. The communication device 2 is, for example, a network card, but is not limited to this. The aforementioned network card is, for example, an existing smart network card. . In addition, the communication connection described in the preferred embodiment of the present invention refers to a wired communication connection, but in other embodiments, it can be a wireless communication connection, which depends on practical design.

The startup state detection system 1 includes a first logic processing module 11 , a storage module 12 and a second logic processing module 13 . The first logic processing module 11 may be, for example, a complex programmable logic device (Complex Programmable Logic Device). One of Logic Device, CPLD, hereinafter referred to as CPLD) and a system on a chip (System on a Chip, SOC) is a CPLD in a preferred embodiment of the present invention, but other implementations are not limited to this. The first logic processing module 11 includes an activation control unit 111 and an activation state detection unit 112, wherein the activation control unit 111 and the activation state detection unit 112 may be existing processors, and the activation state detection unit 112 is an electrical It is connected to the activation control unit 111 and has a state detection time, for example, the state detection time is 1200 milliseconds, but other embodiments are not limited to this.

The storage module 12 stores a startup program 121. The storage module 12 is, for example, a read-only memory. The read-only memory may be, for example, a flash memory (Flash Read-Only Memory, Flash ROM), and The startup program 121 is, for example, firmware, but other embodiments are not limited thereto.

The second logic processing module 13 is communicatively connected to the startup control unit 111 , the startup state detection unit 112 and the storage module 12 , and may be, for example, a Field Programmable Gate Array (FPGA, hereinafter abbreviated as FPGA) FPGA), but other embodiments are not limited to this.

Specifically, the second logic processing module 13 of the preferred embodiment of the present invention further includes a processing unit 131 and an execution state determination unit 132. The processing unit 131 is communicatively connected to the activation control unit 111, the activation state detection unit 112 and the Storage module 12 . The execution state determination unit 132 is electrically connected to the processing unit 131 and the activation state detection unit 112, and is provided with a corresponding relationship including an idle (Idle) state and a first level, and an execution success state and a second level The state judgment table 1321 of the corresponding relationship. In addition, the processing unit 131 and the execution state determination unit 132 can be, for example, existing processors.

It should be mentioned that the idle state of the present invention can also be a standby state, and the successful execution state will be described in detail below. The first potential is a low potential marked as 0, and the second potential is marked as a low potential. is a high potential of 1, therefore, the state judgment table 1321 can be, for example, the following table: state potential idle state 0 execution success status 1

The activation control unit 111 of the first logic processing module 11 is used to send an activation control signal S1, and the second logic processing module 13 is used to send an idle signal S3 of a first potential in an idle state. For example, Since the second logic processing module 13 is an FPGA, in practice, the FPGA has a setting pin (eg CONFIG_DONE), and the signals sent by the setting pin are all low-level signals marked as 0 in an idle state.

When receiving the activation control signal S1, the second logic processing module 13 reads and executes the activation program 121, so as to send an execution success signal S2 with a second potential different from the first potential in an execution success state . Among them, it should be mentioned that the execution success state defined in this case is that the FPGA successfully loads the startup program 121 and completes the execution, so that the communication device 2 is successfully started, and the execution success signal S2 is sent out. bit, but not limited to this in other embodiments.

When the activation state detection unit 112 receives the execution success signal S2 of the second potential within the state detection time, it determines that the second logic processing module 13 successfully executes the activation program 121, and determines that the communication device 2 is a successful activation state. The successful activation state is the state in which the communication device 2 is successfully activated and operated.

When the activation state detection unit 112 still receives the idle signal S3 of the first potential outside the state detection time, it determines that the second logic processing module 13 is in a failure state of activation, and sets one to a third potential. The restart signal S4 is sent to the start-up control unit 111 , so that the start-up control unit 111 re-sends the start-up control signal S1 , so that the second logic processing module 13 re-reads and executes the start-up program 121 .

Among them, it should be mentioned that the above-mentioned third potential is a low potential marked as 0, and generally speaking, if the activation state detection unit 112 has not received the execution success signal S2 within the state detection time, it is During the state detection time, it is not detected that the above-mentioned setting pin is not converted from low level to high level (the flag is converted from 0 to 1), in this state, it is determined that the second logic processing module 13 is executing the startup program 121 An error was encountered and the startup failed status.

In other embodiments, the second logic processing module 13 can also be set to actively send a low-level feedback signal to the activation state detection unit 112 when an error occurs in the execution of the activation program 121 , so that the activation state detection unit 112 The restart signal S4 is sent to the startup control unit 111 to trigger the second logic processing module 13 to reload the startup program 121 .

In addition, in the preferred embodiment of the present invention, the second logic processing module 13 is further processed by the processing unit 131 and the execution state judging unit 132 to specifically confirm which potential signal is sent. For example, the processing unit 131 sends the idle signal S3 in the idle state, and reads and executes the activation program 121 when receiving the activation control signal S1, thereby sending the execution success signal S2 in the execution success state.

When the execution status determination unit 132 receives the execution success signal S2, it compares the execution success signal S2 as the second potential (ie, the high potential marked as 1) according to the status determination table 1321, and will be the execution success of the second potential. The signal S2 is sent to the activation state detection unit 112, and other operations are the same, and will not be repeated here.

The state determination unit 132 is executed and when the idle signal S3 is received, it is compared according to the state determination table 1321 that the idle signal S3 is the first level (ie, the low level of 0), and the idle signal S3 of the first level is sent to the The activation state detection unit 112 enables the activation state detection unit 112 to transmit the restart signal S4 to the activation control unit 111 to trigger the second logic processing module 13 to reload the activation program 121 .

Please refer to the second figure. The second figure is a flow chart of the startup state detection method provided by the preferred embodiment of the present invention. A preferred embodiment of the present invention also provides a startup state detection method, which is implemented by using the startup state detection system shown in the first figure, and includes the following steps S101 to S105.

Step S101 : using the activation control unit 111 of the first logic processing module 11 to send the activation control signal S1 .

Step S102 : using the second logic processing module 13 to receive the activation control signal S1 , so as to read and execute the activation program 121 .

Step S103: Use the activation state detection unit 112 to determine whether the execution success signal S2 of the second potential sent by the second logic processing module 13 in the execution success state is received within the state detection time.

Step S104 : Use the activation state detection unit 112 to determine that the second logic processing module 13 has successfully executed the activation program 121 , and determine that the communication device 2 is in a successful activation state.

Step S105: Using the activation state detection unit 112 to send the restart signal S4 for the third potential to the activation control unit 111, so that the activation control unit 111 re-sends the activation control signal S1, so that the second logic processing module 13 Read and execute the startup program 121 again.

The operations of the second logic processing module 13 in the above steps S102 to S105 can be further performed by the processing unit 131 and the execution state determination unit 132 respectively, and the detailed description of each step has been described in the above paragraphs mentioned, so I won't go into details.

To sum up, after using the startup state detection and the method provided by the present invention, the first logic processing module does not receive the second potential that is different from the first potential within the state detection time and the execution is successful When the signal occurs, the second logic processing module can be directly triggered to read and execute the startup program again, so that the user does not need to power off the communication device to restart the communication device, thus greatly improving the convenience of the user. and can improve the working stability of the communication device.

Through the detailed description of the preferred embodiments above, it is hoped that the features and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various modifications and equivalent arrangements within the scope of the claimed scope of the present invention.

1: Start the state detection system 11: The first logic processing module 111: Start the control unit 112: Start state detection unit 12: Storage Module 121: start the program 13: The second logic processing module 131: Processing unit 132: Execution state judgment unit 1321: Status judgment table 2: Communication device S1: start control signal S2: Execution success signal S3: Idle signal S4: restart signal S101-S105: Steps

The first figure is a block diagram showing a start-up state detection system provided by a preferred embodiment of the present invention; and The second figure is a flow chart of the startup state detection method provided by the preferred embodiment of the present invention.

1: Start the state detection system 11: The first logic processing module 111: Start the control unit 112: Start state detection unit 12: Storage Module 121: start the program 13: The second logic processing module 131: Processing unit 132: Execution state judgment unit 1321: Status judgment table 2: Communication device S1: start control signal S2: Execution success signal S3: Idle signal S4: restart signal

Claims (10)

An activation state detection system is applied to a communication device, and includes: a first logic processing module, including: an activation control unit for sending an activation control signal; and an activation state detection unit, It is electrically connected to the activation control unit and has a state detection time; a storage module stores a activation program; and a second logic processing module is communicatively connected to the activation control unit and the activation state The detection unit and the storage module are used for sending an idle signal of a first potential in an idle state, and for reading and executing the data stored in the storage module when receiving the activation control signal The activation program is used to send out an execution success signal of a second potential different from the first potential in an execution success state; wherein, the activation state detection unit receives an execution success signal within the state detection time When the execution success signal of the second potential is used, it is judged that the second logic processing module has successfully executed the activation program, and the communication device is judged to be in a successful activation state; the activation state detection unit is in the state detection time When the idle signal of the first potential is still received outside, it is determined that the second logic processing module is in a startup failure state, and a restart signal of a third potential is sent to the startup control unit, Thereby, the activation control unit re-sends the activation control signal, so that the second logic processing module re-reads and executes the activation program. The activation state detection system according to claim 1, wherein the communication device is a network card. The startup state detection system of claim 1, wherein the first logic processing module is a Complex Programmable Logic Device (CPLD) and a System on a Chip (SOC) In one of them, the second logic processing module is a Field Programmable Gate Array (FPGA). The startup state detection system according to claim 1, wherein the second logic processing module further comprises: a processing unit, communicatively connected to the startup control unit, the startup control unit and the storage module, for storing The idle signal is sent out in the idle state, and is used to read and execute the activation program when the activation control signal is received, so as to send the execution success signal in the execution success state; and an execution state judgment unit, It is electrically connected to the processing unit and the activation state detection unit, and is provided with a state judgment table including the corresponding relationship between the idle state and the first potential and the corresponding relationship between the execution successful state and the second potential , for sending the execution success signal of the second potential to the startup state detection unit according to the state judgment table when the execution success signal is received, and for receiving the idle signal according to the state The judgment table sends the idle signal of the first potential to the activation state detection unit. The startup state detection system of claim 4, wherein the first potential and the third potential are low potentials marked as 0, and the second potential is a high potential marked as 1. The startup state detection system according to claim 1, wherein the state detection time is 1200 milliseconds. A startup state detection method is implemented using the startup state detection system as described in claim 1, and includes the following steps: (a) using the activation control unit of the first logic processing module to send the activation control signal; (b) using the second logic processing module to receive the activation control signal to read and execute the activation program; (c) using the activation state detection unit to determine whether the execution success signal of the second potential sent by the second logic processing module in the execution success state is received within the state detection time; (d) when the determination result of the step (c) is yes, use the activation state detection unit to determine that the second logic processing module successfully executes the activation program, and determine that the communication device is in the activation success state; and (e) When the determination result of the step (c) is no, use the activation state detection unit to send the restart signal for the third potential to the activation control unit, so that the activation control unit re-sends the The activation control signal causes the second logic processing module to re-read and execute the activation program. The startup state detection method according to claim 7, wherein the communication device is a network card, the first logic processing module is a Complex Programmable Logic Device (CPLD) and a system unit. One of the chips (System on a Chip, SOC), the second logic processing module is a Field Programmable Gate Array (Field Programmable Gate Array, FPGA). The startup state detection method as claimed in claim 7, wherein the first potential and the third potential are low potentials marked as 0, and the second potential is a high potential marked as 1. The activation state detection method according to claim 7, wherein the state detection time is 1200 milliseconds.

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