CN115825703B - 1-type three-level module testing method and equipment - Google Patents
1-type three-level module testing method and equipment Download PDFInfo
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Abstract
The invention discloses a method and equipment for testing a 1-type three-level module, and relates to the field of three-level module testing. When the ith IGBT chip is tested, one IGBT chip connected with the ith IGBT chip is turned on, the turned-on IGBT chip can be similar to a conducting wire, the turned-on IGBT chip releases a double pulse signal to the ith IGBT chip, then test current is conducted to the positive electrode of the ith IGBT chip, the positive electrode can bear the test current, the defect that the test is inaccurate due to the fact that a PIN cannot pass through 150A high current is overcome, each IGBT chip in the 1 type three-level module is tested in sequence according to the process, and the safety test of the 1 type three-level module is realized.
Description
Technical Field
The invention relates to the field of three-level module testing, in particular to a 1-type three-level module testing method and equipment.
Background
For modern society, "electric energy" is a critical existence with which the world after the night curtain has been reduced can be lit. IGBTs (Insulated Gate Bipolar Transistor, insulated gate bipolar transistors) play an important role in the conversion of electrical energy. The power conversion and transmission device is a core device for energy conversion and transmission, can take an IGBT as a CPU of a power electronic device, and can improve the power utilization efficiency and quality by performing power conversion through the IGBT, thereby achieving the effects of energy conservation and environmental protection.
The dynamic characteristics are also called switching characteristics, and the switching characteristics of the IGBT are divided into two major parts: firstly, the switching speed is mainly indicated by the time of each part in the switching process; the other is losses during switching.
Through testing the IGBT module, the performance of the IGBT chip is comprehensively evaluated, and the IGBT module plays an important role in guaranteeing long-term safe and reliable operation of the IGBT and the whole device.
The IGBT chip has 3 polarities, and consists of a grid electrode (G), a collector electrode (C) and an emitter electrode (E) respectively. As shown in fig. 1, the 1-type three-level module has a total of 4 IGBT chips (T1, T2, T3, T4) and 6 FRD chips (D1, D2, D3, D4, D5, D6) inside. However, the emitter (E1) of the chip T1 is present as the collector of the chip T2, and the emitter (E3) of the chip T3 is present as the collector of the chip T4. However, only one PIN of 0.64×0.64×15.5 is used as a linking point of the upper half bridge and the lower half bridge between every two chips, the PIN cannot pass through a large current of 150A, and if the test is forced, the test waveform is extremely inaccurate, so that the judgment of the module is affected. And because of the specificity of the type 1 three-level module, many suppliers in the market have no clear idea how to dynamically test the type 1 three-level module. If the dynamic test is performed on the type 1 three-level module, the risk of the frying machine may be caused by insufficient performance of the chip.
Disclosure of Invention
The invention aims to provide a method and equipment for testing a type 1 three-level module, so as to realize safe and accurate testing of the type 1 three-level module.
In order to achieve the above object, the present invention provides the following solutions:
a test method of a type 1 three-level module comprises the following steps:
testing each IGBT chip in the 1-type three-level module in sequence; the 1-type three-level module comprises a plurality of IGBT chips which are connected in sequence;
when the ith IGBT chip is tested, one IGBT chip connected with the ith IGBT chip in the 1-type three-level module is turned on; wherein i is a positive integer, i is more than or equal to 1 and less than or equal to N, and N is the number of IGBT chips in the 1-type three-level module;
after releasing a double pulse signal to the ith IGBT chip, the on IGBT chip passes a test current to the anode of the ith IGBT chip and flows out from the cathode of the ith IGBT chip;
measuring a voltage waveform diagram and a current waveform diagram of an ith IGBT chip;
and determining the performance of the ith IGBT chip according to the voltage waveform diagram and the current waveform diagram.
A type 1 three-level module test apparatus comprising: a power supply box;
the front of the power supply box is provided with a plurality of probe areas, and the probe areas are in one-to-one correspondence with IGBT chips in the type 1 three-level module; each probe area is connected inside the power box according to a testing method of the corresponding IGBT chip; the test method of the IGBT chip is the test method of the type 1 three-level module;
when one IGBT chip in the type 1 three-level module is tested, the type 1 three-level module is connected with a probe area corresponding to the test IGBT chip.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a test method and device for a 1-type three-level module, wherein when an i-th IGBT chip is tested, one IGBT chip connected with the i-th IGBT chip is turned on, the turned-on IGBT chip can be similar to a wire, the turned-on IGBT chip releases a double pulse signal to the i-th IGBT chip, then test current is conducted to the positive electrode of the i-th IGBT chip, the positive electrode can bear the test current, the defect that a PIN needle cannot pass through 150A high current to cause inaccurate test is overcome, each IGBT chip in the 1-type three-level module is tested in sequence according to the process, and the safety test of the 1-type three-level module is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional three-level module type 1;
FIG. 2 is a flow chart of a test method for a type 1 three-level module according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a test fixture according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a power supply box according to an embodiment of the present invention;
FIG. 5 is a schematic view of a probe area on the front side of a power box according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a power supply probe on the back of a power supply box according to an embodiment of the present invention;
fig. 7 is a diagram of actual measurement waveforms provided in an embodiment of the present invention.
Symbol description: the test fixture comprises a 1-test fixture, a 2-copper probe, a 3-1 type three-level module, a 4-power box, a 5-power box front surface, a 6-power box back surface, a 7-left side test adapter and an 8-right side test adapter.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a method and equipment for testing a type 1 three-level module, so as to realize safe and accurate testing of the type 1 three-level module.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
The test method for the type 1 three-level module provided by the embodiment of the invention, as shown in fig. 2, comprises the following steps:
and S1, testing each IGBT chip in the type 1 three-level module in sequence. The 1-type three-level module comprises a plurality of IGBT chips which are connected in sequence.
Step S2, when testing the ith IGBT chip, switching on one IGBT chip connected with the ith IGBT chip in the 1-type three-level module; wherein i is a positive integer, i is more than or equal to 1 and less than or equal to N, and N is the number of IGBT chips in the 1-type three-level module.
And S3, after the turned-on IGBT chip releases a double pulse signal to the ith IGBT chip, a test current is conducted to the positive electrode of the ith IGBT chip, and flows out from the negative electrode of the ith IGBT chip.
The magnitude of the test current is equal to the nominal current of the IGBT chip.
And S4, measuring a voltage waveform diagram and a current waveform diagram of the ith IGBT chip.
And S5, determining the performance of the ith IGBT chip according to the voltage waveform diagram and the current waveform diagram.
The specific structure of the 1 type three-level module is as follows:
the type 1 three-level module includes: chip T1, chip T2, chip T3, chip T4, chip D5 and chip D6. The chip T1, the chip T2, the chip T3 and the chip T4 are all IGBT chips, and the chip D5 and the chip D6 are all FRD chips. The collector C1 of the chip T1 is used as the positive electrode of the 1-type three-level module, and the emitter E1 of the chip T1 is connected with the collector C2 of the chip T2. The collector C3 of the chip T3 is connected with the emitter E2 of the chip T2, the emitter E3 of the chip T3 is connected with the collector C4 of the chip T4, and the emitter E4 of the chip T4 serves as the negative electrode of the 1-type three-level module. The linking point of the emitter E1 of the chip T1 and the collector C2 of the chip T2 is connected with the cathode of the chip D5, the linking point of the emitter E3 of the chip T3 and the collector C4 of the chip T4 is connected with the anode of the chip D6, and the anode of the chip D5 is connected with the cathode of the chip D6. The linking point of the anode of the chip D5 and the cathode of the chip D6 is used as the N pole of the type 1 three-level module, and the linking point of the emitter E2 of the chip T2 and the collector C3 of the chip T3 is used as the U phase of the type 1 three-level module.
Referring to fig. 1, the type 1 three-level module further includes: chip D1, chip D2, chip D3 and chip D4. Chip D1, chip D2, chip D3 and chip D4 are all FRD chips. Chip D1 is connected between collector C1 and emitter E1 of chip T1, chip D2 is connected between collector C2 and emitter E2 of chip T2, chip D3 is connected between collector C3 and emitter E3 of chip T3, and chip D4 is connected between collector C4 and emitter E4 of chip T4.
The method for testing 4 IGBT chips in the type 1 three-level module is described in detail below.
(1) When i is 1, the ith IGBT chip is a chip T1, and the process of testing the chip T1 is as follows:
shorting the gate G3 and emitter E3 of the chip T3, and shorting the gate G4 and emitter E4 of the chip T4; the purpose is to protect the chip T3 and the chip T4 from being opened by mistake during the test of the chip T1;
the positive electrode of a 15V power supply is connected with the grid G2 of the chip T2, and the negative electrode of the 15V power supply is connected with the U of the type 1 three-level module, so that the chip T2 is turned on; the reason for connecting the negative pole of a 15V power supply to the U phase is: the U-phase power terminals are more and can bear 150A current; after the chip T2 is turned on, the chip T2 can be similar to a wire;
after the chip T2 releases a double pulse signal to the chip T1, 150A current is conducted to the positive electrode of the 1 type three-level module, and the 150A current flows out of the U phase after passing through the chip T1 and the chip T2;
measuring a voltage waveform diagram and a current waveform diagram of the chip T1 through an oscilloscope;
the performance of the chip T1 is determined from the voltage waveform diagram and the current waveform diagram.
(2) When i is 2, the ith IGBT chip is a chip T2, and the process of testing the chip T2 is as follows:
shorting the gate G1 and emitter E1 of the chip T1, and shorting the gate G4 and emitter E4 of the chip T4; the purpose is to protect the chip T1 and the chip T4 from being opened by mistake during the test of the chip T2;
connecting the positive electrode of a 15V power supply with the grid electrode G3 of the chip T3, and connecting the negative electrode of the 15V power supply with the emitter E3 of the chip T3 to enable the chip T3 to be turned on; the chip T3 can be similar to a wire after being opened;
after the chip T3 releases a double pulse signal to the chip T2, 150A current is conducted to the N pole of the 1 type three-level module, and the 150A current flows out from the U phase after passing through the chip D5 and the chip T2; the reason why the N-pole serves as the positive electrode of the chip T2 to pass the 150A current is: the number of the power terminals is large, and 150A current can be born;
measuring a voltage waveform diagram and a current waveform diagram of the chip T2 through an oscilloscope;
and determining the performance of the chip T2 according to the voltage waveform diagram and the current waveform diagram.
(3) When i is 3, the ith IGBT chip is a chip T3, and the process of testing the chip T3 is as follows:
shorting the gate G1 and emitter E1 of the chip T1, and shorting the gate G4 and emitter E4 of the chip T4;
connecting the positive electrode of a 15V power supply with the grid electrode G2 of the chip T2, and connecting the negative electrode of the 15V power supply with the emitter E2 of the chip T2 to enable the chip T2 to be turned on;
after the chip T2 releases a double pulse signal to the chip T3, 150A current is communicated with U of the type 1 three-level module, and the 150A current flows out from N pole of the type 1 three-level module after passing through the chip T3 and the chip D6;
measuring a voltage waveform diagram and a current waveform diagram of the chip T3 through an oscilloscope;
and determining the performance of the chip T3 according to the voltage waveform diagram and the current waveform diagram.
(4) When i is 4, the ith IGBT chip is a chip T4, and the process of testing the chip T4 is as follows:
shorting the gate G1 and emitter E1 of the chip T1, and shorting the gate G2 and emitter E2 of the chip T2;
connecting the positive electrode of a 15V power supply with the grid electrode G3 of the chip T3, and connecting the negative electrode of the 15V power supply with the emitter E3 of the chip T3 to enable the chip T3 to be turned on;
after the chip T3 releases a double pulse signal to the chip T4, 150A current is communicated with U of the type 1 three-level module, and the 150A current flows out from the cathode of the type 1 three-level module after passing through the chip T3 and the chip T4;
measuring a voltage waveform diagram and a current waveform diagram of the chip T4 through an oscilloscope;
the performance of the chip T4 is determined from the voltage waveform diagram and the current waveform diagram.
In order to implement the method, the invention also designs a type 1 three-level module testing device, as shown in fig. 4, which comprises: and a power supply box 4.
The front of the power supply box 4 is provided with a plurality of probe areas, and the probe areas are in one-to-one correspondence with IGBT chips in the type 1 three-level module 3; each probe region is wired inside the power box 4 according to the test method of the corresponding IGBT chip; the test method of the IGBT chip is the test method of the type 1 three-level module. When one IGBT chip in the type 1 three-level module 3 is tested, the type 1 three-level module 3 is connected with a probe area corresponding to the test IGBT chip.
As shown in fig. 5, each probe region includes a plurality of female heads, and the female heads are in one-to-one correspondence with the polarities of the type 1 three-level modules 3; all the female heads of each probe area are connected with the type 1 three-level module 3 through the left test adapter 7 when the type 1 three-level module 3 is tested.
As shown in fig. 6, a power probe is disposed on the back of the power box 4, and the power probe is connected with the dynamic testing device through the right testing adapter 8, and is used for supplying or disconnecting a testing current to the inside of the power box 4 under the control of the dynamic testing device.
As shown in fig. 3, the type 1 three-level module test apparatus further includes: the jig 1 is tested. The test fixture 1 is used for leading out each polarity of the type 1 three-level module 3 through the copper probe 2; the copper probes 2 are connected to the probe area on the front side of the power box 4 when testing the type 1 three-level module 3.
The test fixture 1 includes: a pressing device and a copper probe 2. The copper probe 2 is arranged at the bottom of the pressing device; the type 1 three-level module 3 is located below the copper probe 2. The pressing device is used for downwards moving the copper probe 2, so that the respective polarities of the copper probe 2 and the type 1 three-level module 3 are connected.
The power supply box 4 is mainly connected with a 15V external power supply and the front and back power supply boxes of fig. 5 and 6 are connected through a female connector. The front and back power supply boxes are communicated, so that the replacement of T1/T2/T3/T4 is convenient, and the mass production test is also convenient. The polarities of the modules are led out through the copper probes 2, the power supply box 4 is provided with a female connector, the left test adapter 7 (male connector) of the power supply box 4 is connected into a power line in the power supply box 4 through the female connector according to the following wiring mode, and the power supply box is led out to dynamic test equipment from the back 6 of the power supply box through the right test adapter 8 (male connector). For example: after the test T1 is completed, the test adapter is converted to T2, T3 and T4 for testing respectively. Ensuring that the product can be dynamically tested.
The wiring mode inside the power supply box 4 is as follows:
T1: [G1]-[G] [E1]-[E] [G2]-[+15V] [E2]-[0V] [+]-[+] [U]-[-] [G3]-[E3] [G4]-[E4]
T2: [G2]-[G] [E2]-[E] [G3]-[+15V] [E3]-[0V] [N]-[+] [U]-[-] [G1]-[E1] [G4]-[E4]
T3: [G3]-[G] [E3]-[E] [G2]-[+15V] [E2]-[0V] [U]-[+] [N]-[-] [G1]-[E1] [G4]-[E4]
T4: [G4]-[G] [E4]-[E] [G3]-[+15V] [E3]-[0V] [U]-[+] [-]-[-] [G1]-[E1] [G2]-[E2]
the test result of one IGBT chip in the type 1 three-level module 3 is shown in fig. 7. In fig. 7, (1) (2) (3) (4) represents the voltage between the collector and the emitter, (5) (6) (7) (8) (9) represents the voltage between the gate and the emitter, and (10) (11) (12) (13) represents the current between the collector and the emitter.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (5)
1. The test method of the type 1 three-level module is characterized by comprising the following steps of:
testing each IGBT chip in the 1-type three-level module in sequence; the type 1 three-level module includes: 4 IGBT chips and 2 FRD chips; the plurality of IGBT chips comprise a chip T1, a chip T2, a chip T3 and a chip T4; the plurality of FRD chips include a chip D5 and a chip D6; the collector C1 of the chip T1 is used as the positive electrode of the 1-type three-level module, and the emitter E1 of the chip T1 is connected with the collector C2 of the chip T2; the collector C3 of the chip T3 is connected with the emitter E2 of the chip T2, the emitter E3 of the chip T3 is connected with the collector C4 of the chip T4, and the emitter E4 of the chip T4 is used as the negative electrode of the 1-type three-level module; the link point of the emitter E1 of the chip T1 and the collector C2 of the chip T2 is connected with the cathode of the chip D5, the link point of the emitter E3 of the chip T3 and the collector C4 of the chip T4 is connected with the anode of the chip D6, and the anode of the chip D5 is connected with the cathode of the chip D6; the linking point of the anode of the chip D5 and the cathode of the chip D6 is used as the N pole of the 1-type three-level module, and the linking point of the emitter E2 of the chip T2 and the collector C3 of the chip T3 is used as the U phase of the 1-type three-level module;
the process of testing the chip T1 is as follows:
shorting the gate G3 and emitter E3 of the chip T3, and shorting the gate G4 and emitter E4 of the chip T4;
the positive electrode of a 15V power supply is connected with the grid G2 of the chip T2, and the negative electrode of the 15V power supply is connected with the U of the type 1 three-level module, so that the chip T2 is turned on;
after the chip T2 releases a double pulse signal to the chip T1, 150A current is conducted to the positive electrode of the 1 type three-level module, and the 150A current flows out of the U phase after passing through the chip T1 and the chip T2;
measuring a voltage waveform diagram and a current waveform diagram of the chip T1 through an oscilloscope;
determining the performance of the chip T1 according to the voltage waveform diagram and the current waveform diagram;
the process of testing the chip T2 is as follows:
shorting the gate G1 and emitter E1 of the chip T1, and shorting the gate G4 and emitter E4 of the chip T4;
connecting the positive electrode of a 15V power supply with the grid electrode G3 of the chip T3, and connecting the negative electrode of the 15V power supply with the emitter E3 of the chip T3 to enable the chip T3 to be turned on;
after the chip T3 releases a double pulse signal to the chip T2, 150A current is conducted to the N pole of the 1 type three-level module, and the 150A current flows out from the U phase after passing through the chip D5 and the chip T2;
measuring a voltage waveform diagram and a current waveform diagram of the chip T2 through an oscilloscope;
determining the performance of the chip T2 according to the voltage waveform diagram and the current waveform diagram;
the process of testing the chip T3 is as follows:
shorting the gate G1 and emitter E1 of the chip T1, and shorting the gate G4 and emitter E4 of the chip T4;
connecting the positive electrode of a 15V power supply with the grid electrode G2 of the chip T2, and connecting the negative electrode of the 15V power supply with the emitter E2 of the chip T2 to enable the chip T2 to be turned on;
after the chip T2 releases a double pulse signal to the chip T3, 150A current is communicated with U of the type 1 three-level module, and the 150A current flows out from N pole of the type 1 three-level module after passing through the chip T3 and the chip D6;
measuring a voltage waveform diagram and a current waveform diagram of the chip T3 through an oscilloscope;
determining the performance of the chip T3 according to the voltage waveform diagram and the current waveform diagram;
the process of testing the chip T4 is as follows:
shorting the gate G1 and emitter E1 of the chip T1, and shorting the gate G2 and emitter E2 of the chip T2;
connecting the positive electrode of a 15V power supply with the grid electrode G3 of the chip T3, and connecting the negative electrode of the 15V power supply with the emitter E3 of the chip T3 to enable the chip T3 to be turned on;
after the chip T3 releases a double pulse signal to the chip T4, 150A current is communicated with U of the type 1 three-level module, and the 150A current flows out from the cathode of the type 1 three-level module after passing through the chip T3 and the chip T4;
measuring a voltage waveform diagram and a current waveform diagram of the chip T4 through an oscilloscope;
the performance of the chip T4 is determined from the voltage waveform diagram and the current waveform diagram.
2. A type 1 three-level module test apparatus, comprising: a power supply box;
the front of the power supply box is provided with a plurality of probe areas, and the probe areas are in one-to-one correspondence with IGBT chips in the type 1 three-level module; each probe area is connected inside the power box according to a testing method of the corresponding IGBT chip; the test method of the IGBT chip is the test method of the type 1 three-level module of claim 1;
when one IGBT chip in the type 1 three-level module is tested, the type 1 three-level module is connected with a probe area corresponding to the test IGBT chip.
3. The type 1 three-level module testing apparatus of claim 2, wherein each probe region includes a plurality of female heads, the female heads being in one-to-one correspondence with polarities of the type 1 three-level modules; all the female heads of each probe area are connected with the type 1 three-level module through a test adapter when the type 1 three-level module is tested;
the back of the power supply box is provided with a power supply probe, the power supply probe is connected with dynamic test equipment through another test adapter, and the power supply probe is used for supplying or disconnecting test current to the inside of the power supply box under the control of the dynamic test equipment.
4. The type 1 three-level module testing apparatus of claim 2, further comprising: a test fixture;
the test fixture is used for leading out each polarity of the type 1 three-level module through the copper probe; and the copper probe is connected with a probe area on the front surface of the power supply box when the type 1 three-level module is tested.
5. The type 1 three level module testing apparatus of claim 4, wherein the test fixture comprises: a pressing device and a copper probe;
the copper probe is arranged at the bottom of the pressing device; the type 1 three-level module is positioned below the copper probe;
the pressing device is used for downwards moving the copper probe to enable the copper probe to be communicated with each polarity of the type 1 three-level module.
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