CN115825703A - 1-type three-level module testing method and device - Google Patents
1-type three-level module testing method and device Download PDFInfo
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Abstract
The invention discloses a test method and a test device for a 1-type three-level module, and relates to the field of three-level module test. When an ith IGBT chip is tested, one IGBT chip connected with the ith IGBT chip is switched on, the switched-on IGBT chip can be similar to one wire, the switched-on IGBT chip releases a double-pulse signal to the ith IGBT chip, then test current is switched on to the positive pole of the ith IGBT chip, the positive pole can bear the test current, the defect that a PIN needle cannot pass through 150A heavy current to cause inaccurate test is overcome, each IGBT chip in the type 1 three-level module is tested in sequence according to the process, and the safety test of the type 1 three-level module is realized.
Description
Technical Field
The invention relates to the field of three-level module testing, in particular to a 1-type three-level module testing method and equipment.
Background
For modern society, "power" is a vital existence with which to light the world after the night comes. An IGBT (Insulated Gate Bipolar Transistor) plays an important role in power conversion. The IGBT is a core device for energy conversion and transmission, can be used as a CPU of a power electronic device, performs power conversion through the IGBT, can improve the power utilization efficiency and quality, and achieves the effects of energy conservation and environmental protection.
The dynamic characteristic is also called as switching characteristic, and the switching characteristic of the IGBT is divided into two parts: firstly, the switching speed is the time of each part in the switching process; the other is the loss during switching.
By testing the IGBT module, the performance of the IGBT chip can be comprehensively evaluated, and the IGBT chip and the whole device can be safely and reliably operated for a long time.
The IGBT chip has 3 polarities and is composed of a grid (G), a collector (C) and an emitter (E) respectively. As shown in fig. 1, the type 1 three-level module has 4 IGBT chips (T1, T2, T3, T4) and 6 FRD chips (D1, D2, D3, D4, D5, D6) in total. However, the emitter (E1) of the chip T1 is present as the collector of the chip T2, and the emitter (E3) of the chip T3 is present as the collector of the chip T4. However, only one PIN of 0.64 × 0.64 × 15.5 is used as a link point of the upper half bridge and the lower half bridge between every two chips, the PIN cannot pass through a large current of 150A, and if a test is forced, a test waveform is extremely inaccurate, and judgment on a module is influenced. And because of the particularity of type 1 tri-level modules, many vendors on the market do not know how to dynamically test type 1 tri-level modules. If the dynamic test for the type 1 tri-level module is not properly operated, the risk of explosion may be caused because the performance of the chip itself is not sufficient.
Disclosure of Invention
The invention aims to provide a method and equipment for testing a 1-type three-level module, so as to realize safe and accurate test of the 1-type three-level module.
In order to achieve the purpose, the invention provides the following scheme:
a type 1 three-level module test method comprises the following steps:
sequentially testing each IGBT chip in the type 1 three-level module; the type 1 three-level module comprises a plurality of IGBT chips which are connected in sequence;
when an ith IGBT chip is tested, one IGBT chip connected with the ith IGBT chip in the type 1 three-level module is switched on; wherein i is a positive integer, i is more than or equal to 1 and less than or equal to N, and N is the number of IGBT chips in the 1-type three-level module;
after the turned-on IGBT chip releases a double-pulse signal to the ith IGBT chip, the testing current is conducted to the positive electrode of the ith IGBT chip and flows out from the negative electrode of the ith IGBT chip;
measuring a voltage waveform diagram and a current waveform diagram of the ith IGBT chip;
and determining the performance of the ith IGBT chip according to the voltage waveform diagram and the current waveform diagram.
A type 1 three-level module test apparatus comprising: a power supply box;
the front surface of the power supply box is provided with a plurality of probe areas, and the probe areas correspond to the IGBT chips in the type 1 three-level module one by one; each probe area is connected inside the power box according to the testing method of the corresponding IGBT chip; the testing method of the IGBT chip is the testing method of the type 1 three-level module;
when one IGBT chip in the 1 type three-level module is tested, the 1 type three-level module is connected with a probe area corresponding to the tested IGBT chip.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a 1-type three-level module testing method and equipment, wherein when an ith IGBT chip is tested, one IGBT chip connected with the ith IGBT chip is switched on, the switched-on IGBT chip can be similar to a wire, the switched-on IGBT chip releases a double-pulse signal to the ith IGBT chip, then a testing current is conducted to the anode of the ith IGBT chip, the anode can bear the testing current, the defect that a PIN needle cannot pass through 150A large current to cause inaccurate testing is overcome, each IGBT chip in the 1-type three-level module is sequentially tested according to the process, and the safety testing of the 1-type three-level module is realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a conventional type 1 three-level module;
FIG. 2 is a flowchart of a type 1 tri-level module testing method according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a test fixture according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a power supply box according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a probe area on the front surface of the power supply box according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a power probe at the back of the power box according to an embodiment of the invention;
fig. 7 is a diagram of a measured waveform provided in an embodiment of the present invention.
Description of the symbols: the test device comprises a test fixture 1, a copper probe 2, a type 3-1 tri-level module, a power box 4, a power box 5, a power box front side 6, a power box back side 7, a left side test adapter and a right side test adapter.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a method and equipment for testing a 1-type three-level module, so as to realize safe and accurate test of the 1-type three-level module.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The method for testing a type 1 tri-level module provided by the embodiment of the invention, as shown in fig. 2, comprises the following steps:
and S1, sequentially testing each IGBT chip in the type 1 three-level module. The type 1 three-level module comprises a plurality of IGBT chips which are connected in sequence.
S2, when the ith IGBT chip is tested, one IGBT chip connected with the ith IGBT chip in the type 1 three-level module is switched on; wherein i is a positive integer, i is more than or equal to 1 and less than or equal to N, and N is the number of IGBT chips in the 1-type three-level module.
And S3, after the turned-on IGBT chip releases a double-pulse signal to the ith IGBT chip, the testing current is conducted to the positive electrode of the ith IGBT chip and flows out from the negative electrode of the ith IGBT chip.
The magnitude of the test current is equal to the magnitude of the nominal current of the IGBT chip.
And S4, measuring a voltage waveform diagram and a current waveform diagram of the ith IGBT chip.
And S5, determining the performance of the ith IGBT chip according to the voltage waveform diagram and the current waveform diagram.
The specific structure of the type 1 three-level module is as follows:
the type 1 three-level module includes: chip T1, chip T2, chip T3, chip T4, chip D5, and chip D6. Chip T1, chip T2, chip T3 and chip T4 are the IGBT chip, and chip D5 and chip D6 are the FRD chip. The collector C1 of the chip T1 serves as the positive electrode of the 1-type three-level module, and the emitter E1 of the chip T1 is connected to the collector C2 of the chip T2. Collector C3 of die T3 is connected to emitter E2 of die T2, emitter E3 of die T3 is connected to collector C4 of die T4, and emitter E4 of die T4 serves as the negative electrode of the 1-type three-level module. The junction of emitter E1 of die T1 and collector C2 of die T2 is connected to the cathode of die D5, the junction of emitter E3 of die T3 and collector C4 of die T4 is connected to the anode of die D6, and the anode of die D5 is connected to the cathode of die D6. The linking point of the anode of the die D5 and the cathode of the die D6 serves as the N-pole of the type 1 tri-level module, and the linking point of the emitter E2 of the die T2 and the collector C3 of the die T3 serves as the U-phase of the type 1 tri-level module.
Referring to fig. 1,1, the model 5363 further includes: chip D1, chip D2, chip D3, and chip D4. The chip D1, the chip D2, the chip D3 and the chip D4 are all FRD chips. Chip D1 is connected between collector C1 and emitter E1 of chip T1, chip D2 is connected between collector C2 and emitter E2 of chip T2, chip D3 is connected between collector C3 and emitter E3 of chip T3, and chip D4 is connected between collector C4 and emitter E4 of chip T4.
The method for testing 4 IGBT chips in a type 1 three-level module respectively is described in detail below.
(1) When i is 1, the ith IGBT chip is a chip T1, and the process of testing the chip T1 is as follows:
the grid G3 and the emitter E3 of the chip T3 are in short circuit, and the grid G4 and the emitter E4 of the chip T4 are in short circuit; the purpose is to protect the chip T3 and the chip T4 from being switched on by mistake when testing the T1;
connecting the positive electrode of a 15V power supply with the grid G2 of the chip T2, and connecting the negative electrode of the 15V power supply with the U of the 1-type three-level module to switch on the chip T2; the reason for connecting the negative pole of a 15V power supply to the U phase is that: the U-phase power terminals are more and can bear 150A current; the chip T2 can be similar to a wire after being turned on;
after the chip T2 releases a double-pulse signal to the chip T1, a current of 150A is conducted to the anode of the 1-type three-level module, and the current of 150A flows out of the U phase after passing through the chip T1 and the chip T2;
measuring a voltage waveform diagram and a current waveform diagram of the chip T1 by an oscilloscope;
the performance of the chip T1 is determined from the voltage waveform diagram and the current waveform diagram.
(2) When i is 2, the ith IGBT chip is a chip T2, and the process of testing the chip T2 is as follows:
the grid G1 and the emitter E1 of the chip T1 are in short circuit, and the grid G4 and the emitter E4 of the chip T4 are in short circuit; the purpose is to protect the chip T1 and the chip T4 from being switched on by mistake when testing the T2;
connecting the positive electrode of a 15V power supply with a grid G3 of a chip T3, and connecting the negative electrode of the 15V power supply with an emitter E3 of the chip T3 to switch on the chip T3; the chip T3 can be similar to a wire after being turned on;
after the chip T3 releases a double-pulse signal to the chip T2, 150A current is conducted to the N pole of the 1-type three-level module, and the 150A current flows out of the U phase after passing through the chip D5 and the chip T2; the reason why the current of 150A flows through the N-pole as the positive electrode of the chip T2 is as follows: the power terminals are more and can bear 150A current;
measuring a voltage waveform diagram and a current waveform diagram of the chip T2 by an oscilloscope;
the performance of the chip T2 is determined from the voltage waveform diagram and the current waveform diagram.
(3) When i is 3, the ith IGBT chip is a chip T3, and the process of testing the chip T3 is as follows:
the grid G1 and the emitter E1 of the chip T1 are in short circuit, and the grid G4 and the emitter E4 of the chip T4 are in short circuit;
connecting the positive electrode of a 15V power supply with the grid G2 of the chip T2, and connecting the negative electrode of the 15V power supply with the emitter E2 of the chip T2 to switch on the chip T2;
after the chip T2 releases a double-pulse signal to the chip T3, 150A current is communicated to the U of the 1-type three-level module, and the 150A current flows out of the N pole of the 1-type three-level module after passing through the chip T3 and the chip D6;
measuring a voltage waveform diagram and a current waveform diagram of the chip T3 by an oscilloscope;
the performance of the chip T3 is determined from the voltage waveform diagram and the current waveform diagram.
(4) When i is 4, the ith IGBT chip is a chip T4, and the process of testing the chip T4 is as follows:
the grid G1 and the emitter E1 of the chip T1 are in short circuit, and the grid G2 and the emitter E2 of the chip T2 are in short circuit;
connecting the positive electrode of a 15V power supply with the grid G3 of the chip T3, and connecting the negative electrode of the 15V power supply with the emitter E3 of the chip T3 to enable the chip T3 to be switched on;
after the chip T3 releases a double-pulse signal to the chip T4, the current 150A is communicated with the U of the 1-type three-level module, and the current 150A flows out of the negative electrode of the 1-type three-level module after passing through the chip T3 and the chip T4;
measuring a voltage waveform diagram and a current waveform diagram of the chip T4 by an oscilloscope;
the performance of the chip T4 is determined from the voltage waveform diagram and the current waveform diagram.
In order to implement the method, the invention also designs a type 1 three-level module test device, as shown in fig. 4, comprising: and a power supply box 4.
The front surface of the power supply box 4 is provided with a plurality of probe areas, and the probe areas correspond to the IGBT chips in the type 1 three-level module 3 one by one; each probe area is connected inside the power supply box 4 according to the testing method of the corresponding IGBT chip; the testing method of the IGBT chip is the testing method of the type 1 three-level module. When testing one IGBT chip in the 1 type three-level module 3, the 1 type three-level module 3 is connected with a probe area corresponding to the tested IGBT chip.
As shown in fig. 5, each probe region includes a plurality of female heads, and the female heads correspond to the polarities of the type 1 three-level modules 3 one to one; when the type 1 three-level module 3 is tested, all the female heads of each probe area are connected with the type 1 three-level module 3 through the left-side testing adapter 7.
As shown in fig. 6, a power probe is disposed on the back of the power box 4, the power probe is connected to the dynamic test equipment through the right test adapter 8, and the power probe is used for passing or cutting off the test current to the inside of the power box 4 under the control of the dynamic test equipment.
As shown in fig. 3, the type 1 three-level module test apparatus further includes: the fixture 1 is tested. The test fixture 1 is used for leading out all polarities of the type 1 three-level module 3 through the copper probe 2; the copper probe 2 is connected to the probe area on the front side of the power supply box 4 when testing the type 1 three-level module 3.
The test jig 1 includes: the press down device and the copper probe 2. The copper probe 2 is arranged at the bottom of the pressing device; the type 1 three-level module 3 is positioned below the copper probe 2. The pressing device is used for moving the copper probe 2 downwards to enable the copper probe 2 to be connected with the polarity of the type 1 three-level module 3.
The power supply box 4 is mainly connected with a 15V external power supply and the front and back power supply boxes shown in the figures 5 and 6 through a female connector. The front and back power boxes are communicated, so that the T1\ T2\ T3\ T4 can be conveniently replaced, and the mass production test can be conveniently carried out. Draw out each polarity of module through copper probe 2, install female with power pack 4, insert power cord in power pack 4 through female with 4 left side test adapter 7 (public head) according to following wiring mode, draw out to dynamic test equipment through right side test adapter 8 (public head) from the power pack back 6. For example: and after the test T1 is finished, the test is respectively carried out by converting the test adapter into T2, T3 and T4. And ensuring that the product can be dynamically tested.
The wiring mode inside the power supply box 4 is as follows:
T1: [G1]-[G] [E1]-[E] [G2]-[+15V] [E2]-[0V] [+]-[+] [U]-[-] [G3]-[E3] [G4]-[E4]
T2: [G2]-[G] [E2]-[E] [G3]-[+15V] [E3]-[0V] [N]-[+] [U]-[-] [G1]-[E1] [G4]-[E4]
T3: [G3]-[G] [E3]-[E] [G2]-[+15V] [E2]-[0V] [U]-[+] [N]-[-] [G1]-[E1] [G4]-[E4]
T4: [G4]-[G] [E4]-[E] [G3]-[+15V] [E3]-[0V] [U]-[+] [-]-[-] [G1]-[E1] [G2]-[E2]
the test result for one IGBT chip in the type 1 three-level module 3 is shown in fig. 7. In fig. 7, (1), (2), (3) and (4) show the voltage between the collector and the emitter, (5), (6), (7), (8) and (9) show the voltage between the gate and the emitter, and (10), (11), (12) and (13) show the current between the collector and the emitter.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (10)
1. A type 1 three-level module test method is characterized by comprising the following steps:
sequentially testing each IGBT chip in the type 1 three-level module; the type 1 three-level module comprises a plurality of IGBT chips which are connected in sequence;
when an ith IGBT chip is tested, one IGBT chip connected with the ith IGBT chip in the type 1 three-level module is switched on; wherein i is a positive integer, i is more than or equal to 1 and less than or equal to N, and N is the number of IGBT chips in the 1-type three-level module;
after the turned-on IGBT chip releases a double-pulse signal to the ith IGBT chip, the testing current is conducted to the positive electrode of the ith IGBT chip and flows out from the negative electrode of the ith IGBT chip;
measuring a voltage waveform diagram and a current waveform diagram of the ith IGBT chip;
and determining the performance of the ith IGBT chip according to the voltage waveform diagram and the current waveform diagram.
2. The type 1 tri-level module test method of claim 1, wherein the type 1 tri-level module comprises: a plurality of IGBT chips and a plurality of FRD chips;
the plurality of IGBT chips comprise a chip T1, a chip T2, a chip T3 and a chip T4;
the plurality of FRD chips include a chip D5 and a chip D6;
a collector C1 of the chip T1 is used as the anode of the 1-type three-level module, and an emitter E1 of the chip T1 is connected with a collector C2 of the chip T2;
a collector C3 of the chip T3 is connected with an emitter E2 of the chip T2, an emitter E3 of the chip T3 is connected with a collector C4 of the chip T4, and an emitter E4 of the chip T4 is used as a negative electrode of the 1-type three-level module;
a connecting point of an emitter E1 of the chip T1 and a collector C2 of the chip T2 is connected with a cathode of the chip D5, a connecting point of an emitter E3 of the chip T3 and a collector C4 of the chip T4 is connected with an anode of the chip D6, and an anode of the chip D5 is connected with a cathode of the chip D6;
the linking point of the anode of the die D5 and the cathode of the die D6 serves as the N-pole of the type 1 tri-level module, and the linking point of the emitter E2 of the die T2 and the collector C3 of the die T3 serves as the U-phase of the type 1 tri-level module.
3. The type 1 three-level module test method according to claim 2, wherein when i is 1, the ith IGBT chip is a chip T1;
the process of testing the chip T1 is as follows:
the grid G3 and the emitter E3 of the chip T3 are in short circuit, and the grid G4 and the emitter E4 of the chip T4 are in short circuit;
connecting the positive electrode of a 15V power supply with the grid G2 of the chip T2, and connecting the negative electrode of the 15V power supply with the U of the 1-type three-level module to enable the chip T2 to be switched on;
after the chip T2 releases a double-pulse signal to the chip T1, a current of 150A is conducted to the anode of the 1-type three-level module, and the current of 150A flows out of the U phase after passing through the chip T1 and the chip T2;
measuring a voltage waveform diagram and a current waveform diagram of the chip T1 by an oscilloscope;
the performance of the chip T1 is determined from the voltage waveform diagram and the current waveform diagram.
4. The type 1 three-level module test method according to claim 2, wherein when i is 2, the ith IGBT chip is a chip T2;
the process of testing the chip T2 is as follows:
the grid G1 and the emitter E1 of the chip T1 are in short circuit, and the grid G4 and the emitter E4 of the chip T4 are in short circuit;
connecting the positive electrode of a 15V power supply with the grid G3 of the chip T3, and connecting the negative electrode of the 15V power supply with the emitter E3 of the chip T3 to enable the chip T3 to be switched on;
after the chip T3 releases a double-pulse signal to the chip T2, 150A current is conducted to the N pole of the 1-type three-level module, and the 150A current flows out of the U phase after passing through the chip D5 and the chip T2;
measuring a voltage waveform diagram and a current waveform diagram of the chip T2 by an oscilloscope;
the performance of the chip T2 is determined from the voltage waveform diagram and the current waveform diagram.
5. The type 1 three-level module test method according to claim 2, wherein when i is 3, the ith IGBT chip is a chip T3;
the process of testing the chip T3 is as follows:
the grid G1 and the emitter E1 of the chip T1 are in short circuit, and the grid G4 and the emitter E4 of the chip T4 are in short circuit;
connecting the positive electrode of a 15V power supply with the grid G2 of the chip T2, and connecting the negative electrode of the 15V power supply with the emitter E2 of the chip T2 to switch on the chip T2;
after the chip T2 releases a double-pulse signal to the chip T3, 150A current is communicated to the U of the 1-type three-level module, and the 150A current flows out of the N pole of the 1-type three-level module after passing through the chip T3 and the chip D6;
measuring a voltage waveform diagram and a current waveform diagram of the chip T3 by an oscilloscope;
the performance of the chip T3 is determined from the voltage waveform diagram and the current waveform diagram.
6. The type 1 tri-level module test method according to claim 2, wherein when i is 4, the ith IGBT chip is a chip T4;
the process of testing the chip T4 is as follows:
the grid G1 and the emitter E1 of the chip T1 are in short circuit, and the grid G2 and the emitter E2 of the chip T2 are in short circuit;
connecting the positive electrode of a 15V power supply with the grid G3 of the chip T3, and connecting the negative electrode of the 15V power supply with the emitter E3 of the chip T3 to enable the chip T3 to be switched on;
after the chip T3 releases a double-pulse signal to the chip T4, the current 150A is communicated with the U of the 1-type three-level module, and the current 150A flows out of the negative electrode of the 1-type three-level module after passing through the chip T3 and the chip T4;
measuring a voltage waveform diagram and a current waveform diagram of the chip T4 by an oscilloscope;
the performance of the chip T4 is determined from the voltage waveform diagram and the current waveform diagram.
7. A type 1 tri-level module test apparatus, comprising: a power supply box;
the front surface of the power supply box is provided with a plurality of probe areas, and the probe areas correspond to the IGBT chips in the type 1 three-level module one by one; each probe area is connected inside the power box according to the testing method of the corresponding IGBT chip; the testing method of the IGBT chip is the testing method of the type 1 three-level module as claimed in any one of claims 1 to 6;
when one IGBT chip in the 1 type three-level module is tested, the 1 type three-level module is connected with a probe area corresponding to the tested IGBT chip.
8. The type 1 tri-level module test device according to claim 7, wherein each probe area comprises a plurality of female heads, the female heads corresponding to the polarity of the type 1 tri-level module one to one; when the type 1 three-level module is tested, all the female heads of each probe area are connected with the type 1 three-level module through a test adapter;
the back of the power supply box is provided with a power supply probe, the power supply probe is connected with dynamic test equipment through another test adapter, and the power supply probe is used for introducing or disconnecting test current into the power supply box under the control of the dynamic test equipment.
9. The type 1 tri-level module test device of claim 7, further comprising: testing the clamp;
the test fixture is used for leading out all polarities of the 1-type three-level module through the copper probe; and when the type 1 three-level module is tested, the copper probe is connected with a probe area on the front surface of the power box.
10. The type 1 tri-level module test apparatus of claim 9, wherein the test fixture comprises: a hold down device and a copper probe;
the copper probe is arranged at the bottom of the pressing device; the type 1 three-level module is positioned below the copper probe;
the pressing device is used for moving the copper probe downwards to enable the copper probe to be communicated with each polarity of the type-1 three-level module.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745499A (en) * | 1995-10-11 | 1998-04-28 | Micron Technology, Inc. | Supervoltage detection circuit having a multi-level reference voltage |
| US20110140727A1 (en) * | 2010-05-28 | 2011-06-16 | General Electric Company | Switching device failure detection system and method for multilevel converters |
| CN103248255A (en) * | 2013-05-24 | 2013-08-14 | 哈尔滨工业大学 | Tri-phase modular multi-level converter and fault-tolerate detecting method for IGBT (insulated gate bipolar translator) open circuit fault in sub-modules thereof |
| CN105490511A (en) * | 2015-12-31 | 2016-04-13 | 深圳青铜剑科技股份有限公司 | T-type three-level IGBT drive circuit |
| CN206834981U (en) * | 2017-06-02 | 2018-01-02 | 西安思坦科技有限公司 | A kind of three level IGBT inverter overcurrent protection drive circuits |
| CN108627744A (en) * | 2018-05-29 | 2018-10-09 | 四川蓝芯微电子科技有限公司 | A kind of PN junction breakdown voltage test system and method for igbt chip |
| EP3435100A1 (en) * | 2017-07-24 | 2019-01-30 | TDK-Micronas GmbH | Method for testing an electronic device and an interface circuit therefore |
| CN109374996A (en) * | 2018-08-17 | 2019-02-22 | 国电南瑞科技股份有限公司 | A kind of the dipulse test circuit and method of three level DCDC (PCC) power of striding capacitance |
| US20190064249A1 (en) * | 2016-11-16 | 2019-02-28 | Fuji Electric Co. Ltd. | Semiconductor test circuit, semiconductor test apparatus, and semiconductor test method |
| CN110988538A (en) * | 2019-12-10 | 2020-04-10 | 天津瑞能电气有限公司 | Three-level module testing method |
| CN110988735A (en) * | 2019-12-10 | 2020-04-10 | 天津瑞能电气有限公司 | Three-level module short circuit test method |
| CN111371293A (en) * | 2020-03-10 | 2020-07-03 | 北京交通大学 | IGBT drive circuit with state monitoring and fault recording functions |
| CN113765336A (en) * | 2021-11-10 | 2021-12-07 | 青岛鼎信通讯股份有限公司 | Self-checking method for I-type three-level inverter switching tube applied to SVG |
| WO2021259145A1 (en) * | 2020-06-23 | 2021-12-30 | 山特电子（深圳）有限公司 | I-type three-level converter and uninterruptible power module |
-
2023
- 2023-02-10 CN CN202310091389.4A patent/CN115825703B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745499A (en) * | 1995-10-11 | 1998-04-28 | Micron Technology, Inc. | Supervoltage detection circuit having a multi-level reference voltage |
| US20110140727A1 (en) * | 2010-05-28 | 2011-06-16 | General Electric Company | Switching device failure detection system and method for multilevel converters |
| CN103248255A (en) * | 2013-05-24 | 2013-08-14 | 哈尔滨工业大学 | Tri-phase modular multi-level converter and fault-tolerate detecting method for IGBT (insulated gate bipolar translator) open circuit fault in sub-modules thereof |
| CN105490511A (en) * | 2015-12-31 | 2016-04-13 | 深圳青铜剑科技股份有限公司 | T-type three-level IGBT drive circuit |
| US20190064249A1 (en) * | 2016-11-16 | 2019-02-28 | Fuji Electric Co. Ltd. | Semiconductor test circuit, semiconductor test apparatus, and semiconductor test method |
| CN206834981U (en) * | 2017-06-02 | 2018-01-02 | 西安思坦科技有限公司 | A kind of three level IGBT inverter overcurrent protection drive circuits |
| EP3435100A1 (en) * | 2017-07-24 | 2019-01-30 | TDK-Micronas GmbH | Method for testing an electronic device and an interface circuit therefore |
| CN108627744A (en) * | 2018-05-29 | 2018-10-09 | 四川蓝芯微电子科技有限公司 | A kind of PN junction breakdown voltage test system and method for igbt chip |
| CN109374996A (en) * | 2018-08-17 | 2019-02-22 | 国电南瑞科技股份有限公司 | A kind of the dipulse test circuit and method of three level DCDC (PCC) power of striding capacitance |
| CN110988538A (en) * | 2019-12-10 | 2020-04-10 | 天津瑞能电气有限公司 | Three-level module testing method |
| CN110988735A (en) * | 2019-12-10 | 2020-04-10 | 天津瑞能电气有限公司 | Three-level module short circuit test method |
| CN111371293A (en) * | 2020-03-10 | 2020-07-03 | 北京交通大学 | IGBT drive circuit with state monitoring and fault recording functions |
| WO2021259145A1 (en) * | 2020-06-23 | 2021-12-30 | 山特电子（深圳）有限公司 | I-type three-level converter and uninterruptible power module |
| CN113765336A (en) * | 2021-11-10 | 2021-12-07 | 青岛鼎信通讯股份有限公司 | Self-checking method for I-type three-level inverter switching tube applied to SVG |
Non-Patent Citations (3)
| Title |
|---|
| MARINA SITAL-DAHONE等: "Multiple device open circuit fault diagnosis for neutral-point-clamped inverters", 《 2017 IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC)》 * |
| 姜齐荣等: "功率器件的高压大电流对冲连续测试方法", 清华大学学报(自然科学版) * |
| 梁帅奇等: "T型三电平IGBT驱动的优化设计与测试", 电力电子技术 * |
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