CN115793332B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN115793332B CN115793332B CN202211514305.5A CN202211514305A CN115793332B CN 115793332 B CN115793332 B CN 115793332B CN 202211514305 A CN202211514305 A CN 202211514305A CN 115793332 B CN115793332 B CN 115793332B
- Authority
- CN
- China
- Prior art keywords
- line
- pixel
- row
- common
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 claims description 29
- 239000004973 liquid crystal related substance Substances 0.000 claims description 23
- 230000009977 dual effect Effects 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000001680 brushing effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Abstract
The application belongs to the field of display, and in particular relates to a display panel and a display device, wherein the display panel comprises a plurality of rows of scanning lines, a plurality of columns of data lines and pixel units which are arranged at the intersection points of the scanning lines and the data lines in a one-to-one correspondence manner, the control end of a driving transistor of each pixel unit is connected with the scanning line of the row where the driving transistor is located, the first end of the driving transistor is connected with the data line of the column where the driving transistor is located, the second end of the driving transistor is connected with a pixel electrode, the display panel further comprises a first connecting line and a second connecting line, the common line of the pixel units of the 2m-1 row is connected with the first connecting line, the common line of the pixel units of the 2m-1 row is connected with the second connecting line, m is an integer larger than or equal to 1, and the driving mode of the display panel comprises a double-gate line mode. Compared with the scheme that the common line voltage of all pixel units is the same, the application improves the resolution of a display picture and improves the display picture quality in a double-grid line mode.
Description
Technical Field
The application belongs to the field of display, and particularly relates to a display panel and a display device.
Background
The liquid crystal display panel includes a plurality of display modes such as a Twisted Nematic (TN) mode, an Electronically Controlled Birefringence (ECB) mode, an in-plane switching mode (IPS), and a Vertical Alignment (VA), wherein the VA mode is a common display mode having advantages of high contrast ratio, wide viewing angle, no rubbing alignment, and the like. Currently, a VA pixel design of 8 domains is generally adopted, in one sub-pixel, a data line signal enters a main region sub-pixel and a sub-region sub-pixel, and a voltage part of the sub-region sub-pixel is released to a common line (AVcom) on the side of an array substrate, so that the voltages of the main region sub-pixel and the sub-region sub-pixel are different, and an eight-domain display effect is achieved.
For the display panel with 8-domain pixel design, a Dual gate (DLG) driving technology can be adopted, and the refresh rate can be doubled by reducing the resolution, so that the display panel can display dynamic pictures more smoothly, and the display effect is improved. However, while the refresh rate in the dual-gate mode is increased, the resolution of the display screen may be reduced, especially when the arc pattern is displayed, the arc edge screen is coarser than the normal driving screen, affecting the viewing experience of the user.
Disclosure of Invention
The application aims to provide a display panel and a display device, which are used for improving the display image quality in a double-grid line mode.
In order to achieve the above object, the present application provides a display panel including a plurality of rows of scan lines, a plurality of columns of data lines, and pixel units disposed at intersections of the scan lines and the data lines in one-to-one correspondence, the pixel units including a driving transistor, a pixel electrode, and a common line, a control end of the driving transistor being connected to the scan line of a row in which the driving transistor is located, a first end of the driving transistor being connected to the data line of a column in which the driving transistor is located, a second end of the driving transistor being connected to the pixel electrode, the common line being disposed opposite to the pixel electrode in a thickness direction of the display panel to form a storage capacitor;
the display panel further comprises a first connecting line and a second connecting line, wherein the common line of the pixel units in the 2m-1 th row is connected with the first connecting line, the common line of the pixel units in the 2 m-th row is connected with the second connecting line, and m is an integer greater than or equal to 1;
the driving mode of the display panel comprises a double-grid line mode, and the first connecting line voltage and the second connecting line voltage are different in the double-grid line mode.
Optionally, the display panel further includes an array substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer disposed between the array substrate and the counter substrate, and the scan lines, the data lines, the driving transistors, the common lines, and the pixel electrodes are all disposed on the array substrate;
the pixel unit further comprises a common electrode, wherein the common electrode is positioned on the opposite substrate, and the common electrode and the pixel electrode are positioned on two opposite sides of the liquid crystal layer to form a liquid crystal capacitor;
the pixel unit comprises a main area sub-pixel and a secondary area sub-pixel, wherein the common line of the main area sub-pixel in the 2m-1 row and the common line of the secondary area sub-pixel in the 2m-1 row are connected with the first connecting line, and the common line of the main area sub-pixel in the 2m row and the common line of the secondary area sub-pixel in the 2m row are connected with the second connecting line.
Optionally, the driving transistor includes a first driving transistor and a second driving transistor;
the main region sub-pixel comprises a first driving transistor, a control end of the first driving transistor is connected with the scanning line, a first end of the first driving transistor is connected with the data line, and a second end of the first driving transistor is connected with a pixel electrode corresponding to the main region sub-pixel;
the secondary region sub-pixel comprises a second driving transistor and a leakage transistor, wherein the control end of the second driving transistor is connected with the scanning line, the first end of the second driving transistor is connected with the data line, the second end of the second driving transistor is connected with a pixel electrode corresponding to the secondary region sub-pixel, the control end of the leakage transistor is connected with the scanning line, the first end of the leakage transistor is connected with a pixel electrode corresponding to the secondary region sub-pixel, and the second end of the leakage transistor is connected with a shared discharge line.
Optionally, the shared discharge line connected with the leakage transistors in the 2m-1 row is a first connection line, and the shared discharge line connected with the leakage transistors in the 2m row is a second connection line.
Optionally, the pixel unit further includes a common electrode, where the common electrode and the pixel electrode are disposed on opposite sides of the liquid crystal layer to form a liquid crystal capacitor;
the common electrode of the pixel units in the 2m-1 row is connected with a third connecting wire, and the common electrode of the pixel units in the 2m row is connected with a fourth connecting wire;
in the dual gate line mode, the third connection line voltage and the fourth connection line voltage are different.
Optionally, the first connection line, the second connection line, and the common line are disposed on the same layer, and in a row direction, the first connection line and the second connection line are respectively disposed on two sides of all the pixel units.
Optionally, one of the first connection line and the second connection line is disposed on the same layer as the common line, the other is disposed on a different conductive layer from the common line, the first connection line and the second connection line are insulated from each other, and in a row direction, the first connection line and the second connection line are disposed on the same side as all the pixel units.
Optionally, the display panel further includes a black matrix trace, and projections of the first connection line and the second connection line in a thickness direction of the display panel are located in or overlapped with the black matrix trace.
Optionally, the driving mode of the display panel further includes a normal mode in which the first connection line and the second connection line have the same voltage.
The present application also provides a display device including:
a display panel, wherein a driving mode of the display panel includes a dual gate line mode;
the system-in-chip is used for sending a driving mode control instruction;
a timing controller for reading a voltage setting from the flash memory chip;
and the power management chip is used for generating a common voltage according to the voltage setting, wherein the common voltage comprises a first common voltage output to the first connecting wire and a second common voltage output to the second connecting wire.
The display panel and the display device disclosed by the application have the following beneficial effects:
in the application, the common line of the pixel units of the 2m-1 row is connected with the first connecting line, the common line of the pixel units of the 2m row is connected with the second connecting line, and in the double-grid line mode, the voltage of the first connecting line is different from the voltage of the second connecting line, even if the input signals of the data lines received by the pixel units of the 2m-1 row and the pixel units of the 2m row are the same, the deflection angles of liquid crystal molecules of the pixel units of the 2m-1 row and the pixel units of the 2m row are also different, namely, the pictures displayed by the pixel units of the 2m-1 row and the pixel units of the 2m row are different, compared with the scheme that the common line voltage of all the pixel units is the same, the application improves the resolution of the display picture and improves the display picture quality in the double-grid line mode.
Other features and advantages of the application will be apparent from the following detailed description, or may be learned by the practice of the application.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic plan view of a display panel according to a first embodiment of the application.
Fig. 2 is a schematic structural diagram of a pixel unit according to a first embodiment of the application.
Fig. 3 is a schematic cross-sectional view of a display panel according to a first embodiment of the application.
Fig. 4 is a schematic plan view of a common electrode in a second embodiment of the present application.
Fig. 5 is a schematic cross-sectional view of a display panel according to a third embodiment of the present application.
Fig. 6 is a schematic plan view of a common electrode in a third embodiment of the present application.
Fig. 7 is a schematic structural diagram of a display device according to a fourth embodiment of the present application.
Fig. 8 is a schematic structural diagram of a pixel unit in the third embodiment of the application.
Reference numerals illustrate:
110. a first substrate base plate; 121. a gate; 122. a scanning line; 123. a common line; 124. a first connecting line; 125. a second connecting line; 130. a gate insulating layer; 140. an active layer; 151. a source electrode; 152. a drain electrode; 153. a data line; 154. sharing the discharge wire; 160. a flat layer; 170. a pixel electrode;
200. a liquid crystal layer;
310. a second substrate base plate; 321. a common electrode; 3211. a main region common electrode; 3212. a sub-region common electrode; 322. a third connecting line; 323. a fourth connecting line; 324. a fifth connecting line; 325. a sixth connecting line;
cst, storage capacitor; clc, liquid crystal capacitor; t1, a first driving transistor; t2, a second driving transistor; t3, leakage transistor;
p1, a main region sub-pixel; p2, sub-region sub-pixels;
10. a system-on-chip; 20. a timing controller; 30. a power management chip; 40. and a flash memory chip.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The application will be described in further detail with reference to the drawings and the specific examples. It should be noted that the technical features of the embodiments of the present application described below may be combined with each other as long as they do not collide with each other. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.
Example 1
Referring to fig. 1 to 3, the display panel includes an array substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer 200 between the array substrate and the counter substrate. The array substrate includes a first substrate 110, and a first metal layer including a gate electrode 121, a scan line 122, and a common line 123, a gate insulating layer 130, an active layer 140, a second metal layer including a source electrode 151, a drain electrode 152, and a data line 153, a planarization layer 160, and a pixel electrode 170 sequentially formed on the first substrate 110. The array substrate includes transistors, each including a gate electrode 121, an active layer 140, a source electrode 151, and a drain electrode 152. The opposite substrate includes a second substrate 310 and a common electrode 321 formed on the second substrate 310.
The display panel includes a plurality of rows of scan lines 122, a plurality of columns of data lines 153, and pixel units disposed at intersections of the scan lines 122 and the data lines 153 in one-to-one correspondence, the pixel units including transistors including driving transistors for display driving, common lines 123, pixel electrodes 170, and common electrodes 321.
The control terminal of the driving transistor is connected to the scanning line 122 of the row where the driving transistor is located, the first terminal of the driving transistor is connected to the data line 153 of the column where the driving transistor is located, and the second terminal of the driving transistor is connected to the pixel electrode 170. The control terminal of the driving transistor may be the gate 121, the first terminal of the driving transistor may be the source 151, and the second terminal of the driving transistor may be the drain 152. The common line 123 and the pixel electrode 170 are disposed opposite to each other in a thickness direction of the display panel to form a storage capacitance cst, and the common electrode 321 and the pixel electrode 170 are disposed at opposite sides of the liquid crystal layer 200 to form a liquid crystal capacitance clc.
The display panel further includes a first connection line 124 and a second connection line 125, the common line 123 of the pixel cells of the 2m-1 th row is connected to the first connection line 124, the common line 123 of the pixel cells of the 2 m-th row is connected to the second connection line 125, and m is an integer of 1 or more. The driving mode of the display panel includes a dual gate line mode in which the first connection line 124 voltage and the second connection line 125 voltage are different. The common electrode 321 corresponding to the pixel unit in the 2m-1 row and the common electrode 321 corresponding to the pixel unit in the 2m row may be integral and have the same voltage.
Some display panels with a dual-gate line mode and a normal mode have common lines 123 of all pixel units connected as a whole, when the display panel is switched from the normal mode to the dual-gate line mode, input signals of data lines 153 received by the pixel units in the 2m-1 row and the pixel units in the 2m row are identical, deflection angles of liquid crystal molecules of the pixel units in the 2m-1 row and the pixel units in the 2m row are identical, namely pictures displayed by the pixel units in the 2m-1 row and the pixel units in the 2m row are identical, resolution of a display picture can be reduced, especially when an arc pattern is displayed, an arc edge picture is coarser than a normal driving picture, and viewing experience of a user is affected.
In the present application, the common line 123 of the pixel units in the 2m-1 row is connected to the first connection line 124, the common line 123 of the pixel units in the 2m row is connected to the second connection line 125, and in the dual-gate line mode, the voltage of the first connection line 124 is different from the voltage of the second connection line 125, even if the input signals of the data lines 153 received by the pixel units in the 2m-1 row and the pixel units in the 2m row are the same, the deflection angles of the liquid crystal molecules of the pixel units in the 2m-1 row and the pixel units in the 2m row are different, that is, the pictures displayed by the pixel units in the 2m-1 row and the pixel units in the 2m row are different, and compared with the scheme that the common line 123 voltage of all the pixel units is the same, the present application improves the resolution of the display picture, and improves the display quality in the dual-gate line mode.
In some embodiments, the driving mode of the display panel further includes a normal mode in which the first connection line 124 voltage and the second connection line 125 voltage are the same.
When the voltage of the first connection line 124 is the same as the voltage of the second connection line 125, the deflection angles of the liquid crystal molecules of the pixel units in the 2m-1 row and the pixel units in the 2m row are determined by the input signals of the data line 153, the input signals of the pixel units in the 2m-1 row and the pixel units in the 2m row are different, the deflection angles of the liquid crystal molecules of the pixel units in the 2m-1 row and the pixel units in the 2m row are different, the gray scale brightness of the displayed images are different, namely, the images displayed by the pixel units in the 2m-1 row and the pixel units in the 2m row are different, and the resolution of the displayed images is higher. The display panel has a normal mode and a double-grid line mode, and can adopt the normal mode when displaying a static picture, thereby ensuring the display image quality; when displaying dynamic pictures, the double-grid line mode can be adopted, so that the refresh rate of the display panel is improved, the display panel can display the dynamic pictures more smoothly, and the problem of screen smear when displaying the dynamic pictures is solved.
In some embodiments, the driving mode of the display panel only adopts the dual-gate line mode, so that the high refresh rate function of the product can be met, the cost can be reduced, and the image quality under the high refresh rate can be improved. For example, when the product hardware actually has 120 Hz refresh rate, the dual-grid line mode is started at the same time, so that the product realizes 240 Hz high refresh rate, which is equivalent to reducing the cost for the product, and simultaneously realizes the function of high refresh rate; the product aims at the optimal design of the double grid line mode, so that the image quality under 240 Hz (namely high refresh rate) is improved and improved; that is, when the dual gate line mode is adopted, the product cost is reduced, the function of high refresh rate is satisfied, and the display image quality under high brushing is improved.
As an example, referring to fig. 1 and 2, the pixel unit includes a main region sub-pixel P1 and a sub-region sub-pixel P2, and a common line 123 of the main region sub-pixel P1 of a 2m-1 row and a common line 123 of the sub-region sub-pixel P2 of a 2m-1 row are both connected to the first connection line 124, and a common line 123 of the main region sub-pixel P1 of a 2m row and a common line 123 of the sub-region sub-pixel P2 of a 2m row are both connected to the second connection line 125.
It should be noted that the common line 123 of the main area sub-pixel P1 of row 2m-1 may be connected to the first connection line 124, the common line 123 of the main area sub-pixel P1 of row 2m may be connected to the second connection line 125, but not limited thereto, the common line 123 of all the main area sub-pixels P1 may be connected to an additionally provided conductive line to provide a common voltage.
The pixel unit comprises a main region sub-pixel P1 and a secondary region sub-pixel P2, and the gray scale brightness displayed by the main region sub-pixel P1 and the secondary region sub-pixel P2 can be different, so that the 8-domain display effect is achieved, and the color cast problem of the display panel is improved.
Referring to fig. 1 and 2, the driving transistor includes a first driving transistor T1 and a second driving transistor T2. The main region sub-pixel P1 includes the first driving transistor T1, the control terminal of the first driving transistor T1 is connected to the scan line 122, the first terminal of the first driving transistor T1 is connected to the data line 153, and the second terminal of the first driving transistor T1 is connected to the pixel electrode 170 corresponding to the main region sub-pixel P1.
The sub-region sub-pixel P2 includes the second driving transistor T2 and the leakage transistor T3, that is, the sub-region sub-pixel P2 has one leakage transistor T3 added thereto as compared with the main region sub-pixel P1. The control end of the second driving transistor T2 is connected to the scan line 122, the first end of the second driving transistor T2 is connected to the data line 153, and the second end of the second driving transistor T2 is connected to the pixel electrode 170 corresponding to the sub-pixel P2. The control end of the leakage transistor T3 is connected to the scan line 122, the first end of the leakage transistor T3 is connected to the pixel electrode 170 corresponding to the sub-pixel P2, the second end of the leakage transistor T3 is connected to the shared drain line 154, and the shared drain line 154 may be a wire that is independently set to control the size of the leakage.
When the pixel unit displays, the scan line 122 turns on the first driving transistor T1 and the second driving transistor T2, the data line 153 signals into the main region sub-pixel P1 and the sub-region sub-pixel P2, and the scan line 122 also turns on the drain transistor T3 because the sub-region sub-pixel P2 further includes the drain transistor T3, and the voltage of the sub-region sub-pixel P2 can be partially released to the shared discharge line 154 through the drain transistor T3, so that the voltages of the main region sub-pixel P1 and the sub-region sub-pixel P2 are different, thereby achieving the eight-domain display effect.
In some embodiments, the shared discharge line 154 connected to the leakage transistor T3 of row 2m-1 is the first connection line 124, and the shared discharge line 154 connected to the leakage transistor T3 of row 2m is the second connection line 125.
The leakage transistors T3 in the 2m-1 row use the first connection line 124 as the shared discharge line 154, the leakage transistors T3 in the 2m row use the second connection line 125 as the shared discharge line 154, and compared with the independently arranged shared discharge line 154 for controlling the leakage size, the shared discharge line 154 can be prevented from occupying the design space of other structures of the display panel, and the aperture ratio of the display panel is improved.
Referring to fig. 1 to 3, the first connection line 124, the second connection line 125, and the common line 123 are disposed in the same layer, i.e., the first connection line 124, the second connection line 125, and the common line 123 are all located in the first metal layer. Wherein the common line 123 is a ring frame and is disposed opposite to an edge of the pixel electrode 170. In the row direction, the first connection line 124 and the second connection line 125 are located on both sides of all the pixel units, respectively.
It should be understood that the term "co-layer arrangement" in the present application refers to a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then forming the film layer by using the same mask plate through a one-time patterning process, that is, the one-time patterning process corresponds to one mask plate (also referred to as a photomask). Depending on the particular pattern, a patterning process may include multiple exposure, development, or etching processes, and the particular patterns in the formed layer structure may be continuous or discontinuous, and may be at different heights or have different thicknesses. Therefore, the manufacturing process is simplified, the manufacturing cost is saved, and the production efficiency is improved.
The first connection line 124 and the second connection line 125 are disposed on the first metal layer, so that the design can simplify the structure of the display panel and reduce the manufacturing cost of the display panel. The first connection lines 124 and the second connection lines 125 are respectively located at two sides of all the pixel units, and the first connection lines 124 and the second connection lines 125 do not occupy the display area, so that the aperture ratio of the display panel can be improved.
In some embodiments, one of the first connection line 124 and the second connection line 125 is disposed at the same layer as the common line 123, the other is at a different conductive layer from the common line 123, the first connection line 124 and the second connection line 125 are insulated from each other, and the first connection line 124 and the second connection line 125 are at the same side of all the pixel cells in a row direction. For example, the gate driving chips of the display panel are disposed on the left side of the display panel, and the first connection lines 124 and the second connection lines 125 are disposed on the right side of the display panel, so that the first connection lines 124 and the second connection lines 125 can be designed to avoid affecting the layout of the gate driving chips.
Referring to fig. 1 to 3, the display panel further includes black matrix wirings disposed on the opposite substrate. The projections of the first connection lines 124 and the second connection lines 125 in the thickness direction of the display panel are located in or coincide with the black matrix wirings.
The projections of the first connection lines 124 and the second connection lines 125 in the thickness direction of the display panel are located in or overlapped with the black matrix wiring, that is, the first connection lines 124 and the second connection lines 125 are shielded by the black matrix wiring, so that the aperture ratio of the display panel can be improved.
Example two
As shown in fig. 4, the main difference between the second embodiment and the first embodiment is that the structure of the common electrode 321 is different.
In the first embodiment, the common electrode 321 corresponding to the pixel unit in the 2m-1 th row and the common electrode 321 corresponding to the pixel unit in the 2m-1 th row are integrated and have the same voltage. In this embodiment, the common electrode 321 of the pixel unit in the 2m-1 row is connected to the third connection line 322, and the common electrode 321 of the pixel unit in the 2m row is connected to the fourth connection line 323, where in the dual gate line mode, the voltage of the third connection line 322 is different from the voltage of the fourth connection line 323, and in the normal mode, the voltage of the third connection line 322 is the same as the voltage of the fourth connection line 323.
In the dual gate line mode, the third connection line 322 voltage and the fourth connection line 323 voltage are different, the third connection line 322 voltage compensates for the first connection line 124 voltage floating, the fourth connection line 323 voltage compensates for the first connection line 124 voltage floating, so that the design can prevent the first connection line 124 and the fourth connection line 323 voltage floating from affecting the common electrode 321 voltage, and alleviate the common line 123 voltage instability caused by the common line 123 discharge.
Example III
As shown in fig. 5, the main difference between the third embodiment and the first embodiment is the structure of the common electrode 321.
In the first embodiment, each row of the pixel units includes a main region sub-pixel P1 and a sub-region sub-pixel P2, and the common electrode 321 corresponding to the main region sub-pixel P1 and the common electrode 321 corresponding to the sub-region sub-pixel P2 are integrated and have the same voltage.
In this embodiment, the common electrode 321 corresponding to the main region sub-pixel P1 is a main region common electrode 3211, the common electrode 321 corresponding to the sub-region sub-pixel P2 is a sub-region common electrode 3212, and the sub-region common electrode 3212 and the main region common electrode 3211 are disconnected from each other. Wherein, all the main region common electrodes 3211 are connected to the fifth connection lines 324, and all the sub region common electrodes 3212 are connected to the sixth connection lines 325. When the display panel displays, the voltages of the fifth connection line 324 and the sixth connection line 325 are different, i.e. the voltages of the main region sub-pixel P1 and the sub-region sub-pixel P2 are different.
Note that, all the main region common electrodes 3211 may be connected to the fifth connection lines 324, all the sub region common electrodes 3212 may be connected to the sixth connection lines 325, but not limited thereto, for the main region common electrodes 3211, the main region common electrodes 3211 of the 2m-1 th row and the main region common electrodes 3211 of the 2m-1 th row may be provided to be connected to different connection lines, and the main region common electrodes 3211 of the 2m-1 th row and the main region common electrodes 3211 of the 2 m-th row may be connected to different connection lines, as the case may be.
When the pixel unit displays, the scanning line 122 turns on the first driving transistor T1 and the second driving transistor T2, the data line 153 signals enter the main area sub-pixel P1 and the sub-area sub-pixel P2, the voltages of the main area sub-pixel P1 and the sub-area sub-pixel P2 are different, and the main area sub-pixel P1 and the sub-area sub-pixel P2 can display different gray scale brightness, so that an eight-domain display effect is achieved. Referring to fig. 5, 6 and 8, that is, when the voltage of the fifth connection line 324 is different from the voltage of the sixth connection line 325, the leakage transistor T3 is not required, and the main region sub-pixel P1 and the sub-region sub-pixel P2 can also display different gray scale brightness. The leakage transistor T3 is omitted, the design space of other display structures on the array substrate is larger, and the aperture opening ratio of the display panel can be improved.
For the array substrate, the common line 123 of the main region sub-pixel P1 of the 2m-1 th row and the common line 123 of the sub-region sub-pixel P2 of the 2m-1 th row are connected to the first connection line 124, and the common line 123 of the main region sub-pixel P1 of the 2 m-th row and the common line 123 of the sub-region sub-pixel P2 of the 2 m-th row are connected to the second connection line 125.
In the dual-gate line mode, the voltage of the first connection line 124 is different from the voltage of the second connection line 125, even if the input signals of the data lines 153 received by the pixel units in the 2m-1 row and the pixel units in the 2m row are the same, the deflection angles of the liquid crystal molecules in the pixel units in the 2m-1 row and the pixel units in the 2m row are different, that is, the pictures displayed by the pixel units in the 2m-1 row and the pixel units in the 2m row are different, so that the display image quality in the dual-gate line mode is improved. On the basis, for each pixel unit, the main area sub-pixel P1 and the secondary area sub-pixel P2 display different gray scale brightness, and further improve the image quality of the display panel.
Example IV
Referring to fig. 7, the display device includes a display panel, a system on a chip 10, a timing controller 20, and a power management chip 30. The display panel includes the display panels disclosed in the first to third embodiments, and the driving mode of the display panel includes a dual gate line mode and a normal mode. The system-in-chip 10 is configured to send a driving mode control instruction to switch the driving mode of the display panel to one of a dual-gate line mode and a normal mode. The timing controller 20 is used to read the voltage setting from the flash memory chip 40, and the power management chip 30 is used to generate a common voltage according to the voltage setting, the common voltage including a first common voltage output to the first connection line 124 and a second common voltage output to the second connection line 125. The voltage settings may be stored in the flash memory chip 40 when the display panel is being debugged.
In the present application, the display device includes a display panel, in which the common line 123 of the pixel units in the 2m-1 th row is connected to the first connection line 124, and the common line 123 of the pixel units in the 2m-1 th row is connected to the second connection line 125, and in the dual-gate line mode, the voltages of the first connection line 124 and the second connection line 125 are different, even if the input signals of the data lines 153 received by the pixel units in the 2m-1 th row and the pixel units in the 2m-1 th row are the same, the deflection angles of the liquid crystal molecules of the pixel units in the 2m-1 th row and the pixel units in the 2m-1 th row are different, that is, the images displayed by the pixel units in the 2m-1 th row and the pixel units in the 2 m-th row are different, and compared with the scheme that the common line 123 voltage of all the pixel units is the same, the present application improves the resolution of the display image and the display image quality in the dual-gate line mode.
When the display device is driven:
the system-in-chip 10 determines the driving mode of the display panel according to the frame to be displayed, for example, when displaying dynamic frames such as game frames, a high refresh rate is required, and a dual-gate line mode can be used to make the display frame smoother. When a still picture is displayed or a slower picture is switched, a high refresh rate display is not required, and a normal mode can be adopted to further improve the image quality.
When the high refresh rate display is required, the system-in-chip 10 switches the driving mode of the display panel to the dual-gate mode, and the timing controller 20 receives the instruction of the system-in-chip 10, reads the voltage settings from the flash memory chip 40, and the voltage settings include a first voltage setting V1 and a second voltage setting V2. The power management chip 30 generates a first common voltage according to the first voltage setting V1, generates a second common voltage according to the first voltage setting V2, and the first common voltage and the second common voltage are different;
when the high refresh rate display is not required, the system-in-chip 10 switches the driving mode of the display panel to the normal mode, the timing controller 20 receives an instruction of the system-in-chip 10, reads the voltage setting from the flash memory chip 40, and the voltage setting includes the third voltage setting V3. The power management chip 30 generates a first common voltage and a second common voltage according to the third voltage setting V3, the first common voltage and the second common voltage being the same.
In addition, the dual-gate line mode may be used when displaying a still picture or a moving picture. The system-in-chip 10 switches the driving mode of the display panel to the dual gate line mode, and the timing controller 20 receives an instruction of the system-in-chip 10, reads a voltage setting from the flash memory chip 40, the voltage setting including a first voltage setting V1 and a second voltage setting V2. The power management chip 30 generates a first common voltage according to the first voltage setting V1, generates a second common voltage according to the first voltage setting V2, and the first common voltage and the second common voltage are different, so that the pixel units in the 2m-1 row and the pixel units in the 2m row can display different gray scale brightness, and the display image quality in the dual-gate line mode is improved. For example, when the product hardware actually has 120 Hz refresh rate, the dual-grid line mode is started at the same time, so that the product realizes 240 Hz high refresh rate, which is equivalent to reducing the cost for the product, and simultaneously realizes the function of high refresh rate; the product aims at the optimal design of the double grid line mode, so that the image quality under 240 Hz (namely high refresh rate) is improved and improved; that is, when the dual gate line mode is adopted, the product cost is reduced, the function of high refresh rate is satisfied, and the display image quality under high brushing is improved. The application relates to a project sponsored by a scientific innovation plan (The science and technology innovation Program of Hunan Province) in Hunan province, and the project number is 2022WZ 1003.
The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly, and may be fixedly attached, detachably attached, or integrally formed, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, reference to the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present application have been shown and described, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made in the above embodiments by those skilled in the art within the scope of the application, which is therefore intended to be covered by the appended claims and their equivalents.
Claims (9)
1. The display panel comprises a plurality of rows of scanning lines, a plurality of columns of data lines and pixel units which are arranged at the intersection points of the scanning lines and the data lines in a one-to-one correspondence mode, and is characterized in that the pixel units comprise driving transistors, pixel electrodes and common lines, the control ends of the driving transistors are connected with the scanning lines of the rows where the driving transistors are located, the first ends of the driving transistors are connected with the data lines of the columns where the driving transistors are located, the second ends of the driving transistors are connected with the pixel electrodes, and the common lines and the pixel electrodes are oppositely arranged in the thickness direction of the display panel to form storage capacitors;
the display panel further comprises a first connecting line and a second connecting line, wherein the common line of the pixel units in the 2m-1 th row is connected with the first connecting line, the common line of the pixel units in the 2 m-th row is connected with the second connecting line, and m is an integer greater than or equal to 1;
the driving mode of the display panel comprises a double-grid line mode, in the double-grid line mode, input signals of the data lines received by the pixel units in the 2m-1 row are identical to input signals of the data lines received by the pixel units in the 2m row, and the first connecting line voltage and the second connecting line voltage are different, so that display pictures of the pixel units in the 2m-1 row and the pixel units in the 2m row are different.
2. The display panel according to claim 1, further comprising an array substrate and a counter substrate provided to a cell, and a liquid crystal layer between the array substrate and the counter substrate, the scan line, the data line, the driving transistor, the common line, and the pixel electrode being all located on the array substrate;
the pixel unit further comprises a common electrode, wherein the common electrode is positioned on the opposite substrate, and the common electrode and the pixel electrode are positioned on two opposite sides of the liquid crystal layer to form a liquid crystal capacitor;
the pixel unit comprises a main area sub-pixel and a secondary area sub-pixel, wherein the common line of the main area sub-pixel in the 2m-1 row and the common line of the secondary area sub-pixel in the 2m-1 row are connected with the first connecting line, and the common line of the main area sub-pixel in the 2m row and the common line of the secondary area sub-pixel in the 2m row are connected with the second connecting line.
3. The display panel according to claim 2, wherein the driving transistor includes a first driving transistor and a second driving transistor;
the main region sub-pixel comprises a first driving transistor, a control end of the first driving transistor is connected with the scanning line, a first end of the first driving transistor is connected with the data line, and a second end of the first driving transistor is connected with a pixel electrode corresponding to the main region sub-pixel;
the secondary region sub-pixel comprises a second driving transistor and a leakage transistor, wherein the control end of the second driving transistor is connected with the scanning line, the first end of the second driving transistor is connected with the data line, the second end of the second driving transistor is connected with a pixel electrode corresponding to the secondary region sub-pixel, the control end of the leakage transistor is connected with the scanning line, the first end of the leakage transistor is connected with a pixel electrode corresponding to the secondary region sub-pixel, and the second end of the leakage transistor is connected with a shared discharge line.
4. A display panel according to claim 3, wherein the shared discharge line to which the leakage transistors of row 2m-1 are connected is a first connection line, and the shared discharge line to which the leakage transistors of row 2m are connected is a second connection line.
5. The display panel according to claim 1, wherein the pixel unit further comprises a common electrode disposed on opposite sides of the liquid crystal layer with the pixel electrode to form a liquid crystal capacitance;
the common electrode of the pixel units in the 2m-1 row is connected with a third connecting wire, and the common electrode of the pixel units in the 2m row is connected with a fourth connecting wire;
in the dual gate line mode, the third connection line voltage and the fourth connection line voltage are different.
6. The display panel according to claim 1, wherein the first connection line, the second connection line, and the common line are disposed in the same layer, and the first connection line and the second connection line are respectively located at both sides of all the pixel units in a row direction.
7. The display panel according to claim 1, wherein one of the first connection line and the second connection line is provided in the same layer as the common line, the other is provided in a different conductive layer from the common line, the first connection line and the second connection line are insulated from each other, and the first connection line and the second connection line are provided on the same side of all the pixel units in a row direction.
8. The display panel according to claim 6 or 7, further comprising a black matrix wiring, wherein projections of the first connection lines and the second connection lines in a thickness direction of the display panel are located within or coincide with the black matrix wiring.
9. A display device, comprising:
the display panel according to any one of claims 1 to 8, wherein a driving mode of the display panel includes a dual gate line mode;
the system-in-chip is used for sending a driving mode control instruction;
a timing controller for reading a voltage setting from the flash memory chip;
and the power management chip is used for generating a common voltage according to the voltage setting, wherein the common voltage comprises a first common voltage output to the first connecting wire and a second common voltage output to the second connecting wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211514305.5A CN115793332B (en) | 2022-11-29 | 2022-11-29 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211514305.5A CN115793332B (en) | 2022-11-29 | 2022-11-29 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115793332A CN115793332A (en) | 2023-03-14 |
| CN115793332B true CN115793332B (en) | 2023-11-24 |
Family
ID=85443293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211514305.5A Active CN115793332B (en) | 2022-11-29 | 2022-11-29 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115793332B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290444A (en) * | 2008-06-06 | 2008-10-22 | 友达光电股份有限公司 | Method for driving LCD device |
| CN101783128A (en) * | 2010-04-02 | 2010-07-21 | 福州华映视讯有限公司 | Method for driving liquid crystal display |
| CN102081246A (en) * | 2009-12-01 | 2011-06-01 | 群康科技(深圳)有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN102478736A (en) * | 2010-11-20 | 2012-05-30 | 乐金显示有限公司 | Array substrate for liquid crystal display device and liquid crystal display device including the same |
| CN103926764A (en) * | 2013-03-14 | 2014-07-16 | 上海中航光电子有限公司 | TFT (thin film transistor) array substrate and display panel as well as display device |
| CN105789220A (en) * | 2016-03-24 | 2016-07-20 | 京东方科技集团股份有限公司 | Dual gate line array substrate, testing method, display panel and display device |
| CN106990619A (en) * | 2016-01-11 | 2017-07-28 | 三星显示有限公司 | Display device |
| CN107167977A (en) * | 2017-05-09 | 2017-09-15 | 友达光电股份有限公司 | Pixel array |
| CN107643634A (en) * | 2017-10-26 | 2018-01-30 | 深圳市华星光电半导体显示技术有限公司 | A kind of pixel cell and display base plate |
| CN107783345A (en) * | 2017-10-30 | 2018-03-09 | 深圳市华星光电半导体显示技术有限公司 | Dot structure circuit and liquid crystal display circuit |
| CN110837195A (en) * | 2019-10-22 | 2020-02-25 | 深圳市华星光电技术有限公司 | Eight-domain pixel structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101067618B1 (en) * | 2004-06-29 | 2011-09-27 | 엘지디스플레이 주식회사 | Liquid Crystal Display Panel And Fabricating Method Thereof |
| KR102326555B1 (en) * | 2015-04-29 | 2021-11-17 | 삼성디스플레이 주식회사 | Display device |
-
2022
- 2022-11-29 CN CN202211514305.5A patent/CN115793332B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290444A (en) * | 2008-06-06 | 2008-10-22 | 友达光电股份有限公司 | Method for driving LCD device |
| CN102081246A (en) * | 2009-12-01 | 2011-06-01 | 群康科技(深圳)有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN101783128A (en) * | 2010-04-02 | 2010-07-21 | 福州华映视讯有限公司 | Method for driving liquid crystal display |
| CN102478736A (en) * | 2010-11-20 | 2012-05-30 | 乐金显示有限公司 | Array substrate for liquid crystal display device and liquid crystal display device including the same |
| CN103926764A (en) * | 2013-03-14 | 2014-07-16 | 上海中航光电子有限公司 | TFT (thin film transistor) array substrate and display panel as well as display device |
| CN106990619A (en) * | 2016-01-11 | 2017-07-28 | 三星显示有限公司 | Display device |
| CN105789220A (en) * | 2016-03-24 | 2016-07-20 | 京东方科技集团股份有限公司 | Dual gate line array substrate, testing method, display panel and display device |
| CN107167977A (en) * | 2017-05-09 | 2017-09-15 | 友达光电股份有限公司 | Pixel array |
| CN107643634A (en) * | 2017-10-26 | 2018-01-30 | 深圳市华星光电半导体显示技术有限公司 | A kind of pixel cell and display base plate |
| WO2019080188A1 (en) * | 2017-10-26 | 2019-05-02 | 深圳市华星光电半导体显示技术有限公司 | Pixel unit and display substrate |
| CN107783345A (en) * | 2017-10-30 | 2018-03-09 | 深圳市华星光电半导体显示技术有限公司 | Dot structure circuit and liquid crystal display circuit |
| CN110837195A (en) * | 2019-10-22 | 2020-02-25 | 深圳市华星光电技术有限公司 | Eight-domain pixel structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115793332A (en) | 2023-03-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7701520B2 (en) | Liquid crystal panel and display device with data bus lines and auxiliary capacitance bus lines both extending in the same direction | |
| KR0177016B1 (en) | Loquid crystal device | |
| US9715133B2 (en) | Liquid crystal display and driving method thereof | |
| US6320566B1 (en) | Driving circuit for liquid crystal display in dot inversion method | |
| US9064472B2 (en) | Liquid crystal display and method thereof | |
| TW200521592A (en) | Liquid crystal display device automatically adjusting aperture ratio in each pixel | |
| JPH08179341A (en) | Liquid crystal display device and its driving method | |
| US8319918B2 (en) | Multi-domain display using fringe fields | |
| TWI405014B (en) | A liquid crystal display and a driving method thereof are provided | |
| US11636818B2 (en) | Display panel, drive method thereof and display apparatus | |
| CN108806629B (en) | Pixel unit, driving method thereof and display panel | |
| CN115793332B (en) | Display panel and display device | |
| TWI406038B (en) | Pixels having polarity extension regions for multi-domain vertical alignment liquid crystal displays | |
| CN113568232B (en) | Pixel unit, array substrate, driving method, liquid crystal panel and liquid crystal display screen | |
| US8339529B2 (en) | Pixels having polarity extension regions for multi-domain vertical alignment liquid crystal displays | |
| CN115457913B (en) | Display panel and display device | |
| CN116741113A (en) | Display panel, display device and display driving method | |
| CN114563892B (en) | Array substrate, display panel and display device | |
| CN114170983B (en) | Display device, display driving method, and electronic apparatus | |
| CN115101024B (en) | Pixel structure, array substrate and display panel | |
| CN114924445B (en) | Array substrate and display panel | |
| US20240212642A1 (en) | Display panel and display device | |
| CN217655405U (en) | Array substrate, display panel and display device | |
| KR102640064B1 (en) | Display panels and display devices | |
| TWI408474B (en) | Subpixel structure and liquid crystal display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |