CN116741113A - Display panel, display device and display driving method - Google Patents

Abstract

The application belongs to the field of display, and particularly relates to a display panel, a display device and a display driving method. The application controls the display panel to switch between 4-domain display and 8-domain display through the scanning lines, when a simple picture is displayed, the 4-domain display can be adopted, the transmissivity of the display panel is higher, and when a complex picture is displayed, the 8-domain display can be adopted, and the visual angle and color cast can be improved.

Description

Display panel, display device and display driving method

Technical Field

The application belongs to the field of display, and particularly relates to a display panel, a display device and a display driving method.

Background

The liquid crystal display panel includes a plurality of display modes such as a Twisted Nematic (TN) mode, an Electronically Controlled Birefringence (ECB) mode, an in-plane switching mode (IPS), and a Vertical Alignment (VA), wherein the VA mode is a common display mode having advantages of high contrast ratio, wide viewing angle, no rubbing alignment, and the like. At present, a VA pixel design of 8 domains is generally adopted, in one sub-pixel, a data line signal enters a main region sub-pixel and a sub-region sub-pixel, and the voltage of the sub-region sub-pixel is released through a transistor, so that the difference of the voltages of the main region sub-pixel and the sub-region sub-pixel is realized, and an eight-domain display effect is achieved.

The 8-domain display has improved viewing angle and color shift compared to the 4-domain display, but the voltage of the sub-region sub-pixel is partially released through the transistor, and the transmittance of the sub-region sub-pixel is lower, resulting in that the 8-domain display has lower transmittance than the 4-domain display.

Disclosure of Invention

The application aims to provide a display panel, a display device and a display driving method, which solve the problem of low transmittance of the display panel designed by 8-domain pixels by switching 4-domain display and 8-domain display.

In order to achieve the above object, the present application provides a display panel, including a plurality of scan lines disposed in a row direction, a plurality of data lines disposed in a column direction, and a pixel unit disposed corresponding to an intersection of the scan lines and the data lines, wherein the pixel unit includes a main region sub-pixel and a sub-region sub-pixel, the main region sub-pixel and the sub-region sub-pixel are respectively disposed at two sides of the scan lines, the scan lines include a first scan line and a second scan line, the main region sub-pixel and the sub-region sub-pixel are both connected with the first scan line, the sub-region sub-pixel includes a sub-region pixel electrode and a leakage transistor, the leakage transistor includes a control terminal, a first connection terminal and a second connection terminal, the second scan line is connected with at least the control terminal of the leakage transistor, the first connection terminal of the leakage transistor is connected with the sub-region pixel electrode, and the second connection terminal of the leakage transistor is connected with the leakage transistor.

Optionally, the main region sub-pixel includes a first transistor and a main region pixel electrode, where the first transistor includes a first control end, a first connection end, and a second connection end, the first control end of the first transistor is connected to the first scan line, the first connection end of the first transistor is connected to the data line, and the second connection end of the first transistor is connected to the main region pixel electrode;

the sub-region sub-pixel further comprises a second transistor, the second transistor comprises a first control end, a first connection end and a second connection end, the first control end of the second transistor is connected with the first scanning line, the first connection end of the second transistor is connected with the data line, and the second connection end of the second transistor is connected with the sub-region pixel electrode.

Optionally, the first transistor further includes a second control terminal, and the second control terminal of the first transistor is connected to the second scan line;

the second transistor further comprises a second control end, and the second control end of the second transistor is connected with the second scanning line.

Optionally, the display panel further includes a plurality of shared discharge lines disposed in a column direction, the drain terminal includes the shared discharge line, the second connection terminal of the drain transistor is connected to the shared discharge line of the corresponding column, and all the shared discharge lines are connected.

Optionally, the shared discharge line includes a plurality of first sections and a plurality of second sections, adjacent in the same column the first sections are connected with the second sections, the main area pixel electrode includes a main area longitudinal keel, the secondary area pixel electrode includes a secondary area longitudinal keel, the orthographic projection of the first section on the main area pixel electrode is located in or coincides with the main area longitudinal keel, and the orthographic projection of the second section on the secondary area pixel electrode is located in or coincides with the secondary area longitudinal keel.

Optionally, the shared discharge line and the data line are arranged in the same layer.

Optionally, the sub-region sub-pixel further includes a sub-region common line, the sub-region common line and the sub-region pixel electrode form a sub-region storage capacitor, and the drain terminal is the sub-region common line.

The present application also provides a display device including:

a display panel;

and the main board is connected with the display panel.

The present application also provides a display driving method for the display device, the display device further including a gate driving circuit connected to the scan line, the display driving method including:

detecting display picture information through a time sequence controller, wherein the display picture comprises a simple picture and a complex picture which are opposite;

when the display picture is confirmed to be a simple picture, controlling the grid driving circuit to output a scanning signal to the first scanning line;

and when the display picture is confirmed to be a complex picture, controlling the grid driving circuit to at least output a scanning signal to the second scanning line.

Optionally, the gate driving circuit outputs the same timing to the first scan line signal and the second scan line signal.

The display panel, the display device and the display driving method disclosed by the application have the following beneficial effects:

in the application, the display panel comprises a plurality of scanning lines arranged in a row direction, a plurality of data lines arranged in a column direction and pixel units arranged corresponding to the intersections of the scanning lines and the data lines, wherein each pixel unit comprises a main area sub-pixel and a secondary area sub-pixel, each scanning line comprises a first scanning line and a second scanning line, each main area sub-pixel and each secondary area sub-pixel are connected with the first scanning line, each secondary area sub-pixel comprises a secondary area pixel electrode and a leakage transistor, each second scanning line is at least connected with a control end of each leakage transistor, a first connection end of each leakage transistor is connected with each secondary area pixel electrode, and a second connection end of each leakage transistor is connected with each leakage end. According to the application, the drain transistor is controlled to be turned on or off through the second scanning line, the display panel is controlled to switch between 4-domain display and 8-domain display, when a simple picture is displayed, the 4-domain display can be adopted, the transmissivity of the display panel is higher, when a complex picture is displayed, the 8-domain display can be adopted, and the visual angle and color cast can be improved.

Other features and advantages of the application will be apparent from the following detailed description, or may be learned by the practice of the application.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a display panel according to a first embodiment of the application.

Fig. 2 is a schematic structural diagram of a pixel unit according to a first embodiment of the application.

Fig. 3 is a schematic structural diagram of a pixel unit in the second embodiment of the application.

Fig. 4 is a schematic structural diagram of a display device according to a third embodiment of the present application.

Fig. 5 is a flowchart of a display driving method in a fourth embodiment of the present application.

Reference numerals illustrate:

110. a scanning line; 111. a first scan line; 112. a second scanning line;

120. a data line;

210. a main region sub-pixel; 211. a first transistor; 212. a main region pixel electrode; 2121. longitudinal keels in the main area; 213. a main region common electrode; 214. a main region common line;

220. sub-region sub-pixels; 221. a sub-region pixel electrode; 2211. a secondary region longitudinal keel; 222. a leakage transistor; 223. a second transistor; 224. a sub-region common electrode; 225. a secondary region common line; 226. sharing the discharge wire; 2261. a first segment; 2262. a second segment; 2263. a connection section;

10. a display panel; 20. a main board; 30. a gate driving circuit; 40. and a data driving circuit.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.

The application will be described in further detail with reference to the drawings and the specific examples. It should be noted that the technical features of the embodiments of the present application described below may be combined with each other as long as they do not collide with each other. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.

Example 1

Referring to fig. 1 and 2, the display panel in this embodiment includes a plurality of scan lines 110 arranged in a row direction, a plurality of data lines 120 arranged in a column direction, and pixel units arranged corresponding to intersections of the scan lines 110 and the data lines 120. The pixel unit includes a main region sub-pixel 210 and a sub-region sub-pixel 220, and the main region sub-pixel 210 and the sub-region sub-pixel 220 are respectively located at two sides of the scan line 110.

The scan line 110 includes a first scan line 111 and a second scan line 112, the main region sub-pixel 210 and the sub-region sub-pixel 220 are connected to the first scan line 111, the sub-region sub-pixel 220 includes a sub-region pixel electrode 221 and a drain transistor 222, the drain transistor 222 includes a control terminal, a first connection terminal and a second connection terminal, the second scan line 112 is connected to at least the control terminal of the drain transistor 222, the first connection terminal of the drain transistor 222 is connected to the sub-region pixel electrode 221, and the second connection terminal of the drain transistor 222 is connected to the drain terminal. The control terminal, the first connection terminal and the second connection terminal of the drain transistor 222 may be a gate, a source and a drain thereof, respectively.

The display panel includes a 4-domain display mode and an 8-domain display mode. The first scan line 111 inputs a scan signal to control the main area sub-pixel 210 and the sub-area sub-pixel 220 to be turned on, and the main area sub-pixel 210 and the sub-area sub-pixel 220 realize the display with the same brightness, namely, the 4-domain display. The first scan line 111 inputs a scan signal to control the main region sub-pixel 210 and the sub-region sub-pixel 220 to be turned on, the first scan line 111 inputs a scan signal to control the drain transistor 222 to be turned on, and although the data signals written into the main region sub-pixel 210 and the sub-region sub-pixel 220 are the same, a part of the voltage of the sub-region pixel electrode 221 is released through the drain terminal, and finally the main region sub-pixel 210 and the sub-region sub-pixel 220 realize different brightness display, namely 8domain display.

The 8-domain display has improved viewing angle and color shift compared to the 4-domain display, but the voltage of the sub-region sub-pixel 220 is partially discharged through the drain transistor 222, and the transmittance of the sub-region sub-pixel 220 is lower, resulting in the 8-domain display having lower transmittance than the 4-domain display.

In this embodiment, the display panel includes a plurality of scan lines 110 disposed in a row direction, a plurality of data lines 120 disposed in a column direction, and pixel units disposed corresponding to intersections of the scan lines 110 and the data lines 120, the pixel units include a main region sub-pixel 210 and a sub-region sub-pixel 220, the scan lines 110 include a first scan line 111 and a second scan line 112, the main region sub-pixel 210 and the sub-region sub-pixel 220 are connected to the first scan line 111, the sub-region sub-pixel 220 includes a sub-region pixel electrode 221 and a drain transistor 222, the second scan line 112 is connected to at least a control terminal of the drain transistor 222, a first connection terminal of the drain transistor 222 is connected to the sub-region pixel electrode 221, and a second connection terminal of the drain transistor 222 is connected to a drain terminal. The second scan line 112 controls the leakage transistor 222 to be turned on or off, and controls the display panel to switch between 4-domain display and 8-domain display, so that the 4-domain display can be adopted when a simple picture is displayed, the transmittance of the display panel is higher, and the 8-domain display can be adopted when a complex picture is displayed, thereby improving the visual angle and color cast.

As illustrated with reference to fig. 1 and 2, the main region sub-pixel 210 includes a first transistor 211 and a main region pixel electrode 212. The first transistor 211 includes a first control terminal, a first connection terminal, and a second connection terminal, the first control terminal of the first transistor 211 is connected to the first scan line 111, the first connection terminal of the first transistor 211 is connected to the data line 120, and the second connection terminal of the first transistor 211 is connected to the main region pixel electrode 212. The control terminal, the first connection terminal and the second connection terminal of the first transistor 211 may be a gate, a source and a drain thereof, respectively.

The main region sub-pixel 210 further includes a main region common electrode 213 and a main region common line 214, the main region common electrode 213 and the main region pixel electrode 212 being disposed opposite to each other in a thickness direction of the display panel to form a main region liquid crystal capacitance for driving liquid crystal molecules to deflect according to a data voltage to display a picture; the main region pixel electrode 212 and the main region common line 214 are disposed opposite to each other in a thickness direction of the display panel to form a main region storage capacitor for maintaining a data voltage.

The sub-region sub-pixel 220 further includes a second transistor 223, the second transistor 223 including a first control terminal, a first connection terminal, and a second connection terminal, the first control terminal of the second transistor 223 being connected to the first scan line 111, the first connection terminal of the second transistor 223 being connected to the data line 120, the second connection terminal of the second transistor 223 being connected to the sub-region pixel electrode 221. The control terminal, the first connection terminal and the second connection terminal of the second transistor 223 may be a gate, a source and a drain thereof, respectively.

The sub-region sub-pixel 220 further includes a sub-region common electrode 224 and a sub-region common line 225, the sub-region common electrode 224 and the sub-region pixel electrode 221 being disposed opposite to each other in a thickness direction of the display panel to form a sub-region liquid crystal capacitance; the sub-region pixel electrode 221 and the sub-region common line 225 are disposed opposite to each other in the thickness direction of the display panel to form a sub-region storage capacitance.

The display panel includes an array substrate, a counter substrate, and a liquid crystal layer disposed between the array substrate and the counter substrate, and the counter substrate may include a color film substrate. The array substrate comprises a substrate, a first metal layer, an insulating layer, an active layer, a second metal layer, a flat layer and a pixel electrode layer, wherein the first metal layer, the insulating layer, the active layer, the second metal layer, the flat layer and the pixel electrode layer are sequentially formed on one side of the substrate. The scan line 110, the gate of the first transistor 211, the gate of the second transistor 223, the gate of the drain transistor 222, the main region common line 214, and the sub region common line 225 are all located in the first metal layer, the data line 120, the source-drain electrode of the first transistor 211, the source-drain electrode of the second transistor 223, and the source-drain electrode of the drain transistor 222 are all located in the second metal layer, and the main region pixel electrode 212 and the sub region pixel electrode 221 are all located in the pixel electrode layer. The color film substrate comprises a substrate, a color film layer and a common electrode layer, wherein the color film layer and the common electrode layer are sequentially formed on one side of the substrate, and the main area common electrode 213 and the secondary area common electrode 224 are both positioned on the common electrode layer.

The first scanning line 111 controls the main area sub-pixel 210 through the first transistor 211, the first scanning line 111 controls the sub-area sub-pixel 220 through the second transistor 223, the second scanning line 112 controls the sub-area pixel electrode 221 to be connected with the drain terminal through the drain transistor 222, the display panel is controlled to realize that 4-domain display and 8-domain display are switched simply, and meanwhile, the pixel driving circuit is simple in structure and can reduce the manufacturing cost of the display panel.

It should be noted that, the sub-region sub-pixel 220 is connected to the drain terminal through the drain transistor 222, and a portion of the charges of the sub-region sub-pixel 220 may be released to the drain terminal through the drain transistor 222, but not limited thereto, the main region common electrode 213 and the sub-region common electrode 224 may also be controlled separately, so that the driving voltage of the sub-region sub-pixel 220 is greater than the voltage of the main region sub-pixel 210, as the case may be.

Referring to fig. 1 and 2, the display panel further includes a plurality of common discharge lines 226 (share bar) arranged in a column direction, the common discharge lines 226 being arranged in one-to-one correspondence with the data lines 120. The drain terminal includes a common discharge line 226, and the second connection terminal of the drain transistor 222 is connected to the common discharge line 226 of the corresponding column, and all the common discharge lines 226 are connected.

The shared drain line 226 is additionally disposed on one side of the data line 120 as a drain terminal of the drain transistor 222, so as to avoid unstable voltage of the drain terminal caused by releasing charges on the sub-pixel electrode 221.

It should be noted that the shared discharge lines 226 may be disposed along the column direction, but not limited thereto, and the shared discharge lines 226 may be disposed along the row direction, where the shared discharge lines 226 are in one-to-one correspondence with the scan lines 110, as the case may be. While the common discharge lines 226 may also be arranged in the row direction, the common discharge lines 226 may be arranged in the same layer as the scan lines 110 when the common discharge lines 226 are in one-to-one correspondence with the scan lines 110.

Referring to fig. 1 and 2, the shared discharge line 226 includes a plurality of first segments 2261 and a plurality of second segments 2262, with adjacent first segments 2261 and second segments 2262 being connected in the same column. The main region pixel electrode 212 includes a main region longitudinal keel 2121 and the sub region pixel electrode 221 includes a sub region longitudinal keel 2211, with the orthographic projection of the first segment 2261 onto the main region pixel electrode 212 being located within or coincident with the main region longitudinal keel 2121 and the orthographic projection of the second segment 2262 onto the sub region pixel electrode 221 being located within or coincident with the sub region longitudinal keel 2211.

The shared discharge line 226 further includes a connection section 2263, and the connection section 2263 surrounds the second transistor 223 and the leakage transistor 222 on three sides and connects the first section 2261 and the second section 2262. That is, in the same column of adjacent two pixel units, the first segment 2261 and the second segment 2262 are directly connected, and in the same pixel unit, the first segment 2261 and the second segment 2262 are connected by the connection segment 2263.

The orthographic projection of the first segment 2261 on the main region pixel electrode 212 is located in or coincides with the main region longitudinal keel 2121, and the orthographic projection of the second segment 2262 on the secondary region pixel electrode 221 is located in or coincides with the secondary region longitudinal keel 2211, so that the design can reduce the design space occupied by the shared discharge line 226 on the display panel, and is beneficial to improving the aperture ratio of the display panel.

Referring to fig. 1 and 2, the shared discharge line 226 is disposed at the same layer as the data line 120.

It should be understood that the term "co-layer arrangement" in the present application refers to a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then forming the film layer by using the same mask plate through a one-time patterning process, that is, the one-time patterning process corresponds to one mask plate (also referred to as a photomask). Depending on the particular pattern, a patterning process may include multiple exposure, development, or etching processes, and the particular patterns in the formed layer structure may be continuous or discontinuous, and may be at different heights or have different thicknesses.

The shared discharge line 226 and the data line 120 are arranged in the same layer, so that the manufacturing cost of the display panel can be reduced.

It should be noted that the shared discharge line 226 may be disposed at the same layer as the data line 120, but not limited thereto, and the shared discharge line 226 may be disposed at a different structural layer from the data line 120, as the case may be.

Referring to fig. 1 and 2, the sub-region sub-pixel 220 includes a sub-region common electrode 224 and a sub-region common line 225, the sub-region common electrode 224 and the sub-region pixel electrode 221 being disposed opposite to each other in a thickness direction of the display panel to form a sub-region liquid crystal capacitance; the sub-region pixel electrode 221 and the sub-region common line 225 are disposed opposite to each other in the thickness direction of the display panel to form a sub-region storage capacitance.

In some embodiments, the drain terminal is a secondary common line 225.

The leakage transistor 222 discharges part of charges on the sub-pixel electrode 221 to the sub-common line 225, so that the structure of the pixel driving circuit is simpler, and meanwhile, the leakage end occupies smaller design space of the display panel, so that the aperture ratio of the display panel can be improved.

Example two

The main difference between the second embodiment and the first embodiment is that the first transistor 211 and the second transistor 223 are different in structure.

Referring to fig. 3, in the second embodiment, the first transistor 211 further includes a second control terminal, and the second control terminal of the first transistor 211 is connected to the second scan line 112. The second transistor 223 further includes a second control terminal, and the second control terminal of the second transistor 223 is connected to the second scan line 112.

In the first embodiment, the first scan line 111 controls the main region sub-pixel 210 to be turned on or off through the first transistor 211, controls the sub-region sub-pixel 220 to be turned on or off through the second transistor 223, and the second scan line 112 controls the connection between the sub-region pixel electrode 221 and the drain terminal through the drain transistor 222. In the second embodiment, the first scan line 111 controls the main area sub-pixel 210 to be turned on or off through the first transistor 211, controls the sub-area sub-pixel 220 to be turned on or off through the second transistor 223, and controls the connection between the sub-area pixel electrode 221 and the drain terminal through the drain transistor 222.

In the display panel of the first embodiment, the first scan line 111 inputs the scan signal to control the display surface to enter the 4-domain display mode, and the first scan line 111 and the second scan line 112 simultaneously inputs the scan signal to control the display surface to enter the 8-domain display mode. In the display panel of the second embodiment, the first scan line 111 inputs a scan signal to control the display surface to enter the 4-domain display mode, and the second scan line 112 inputs a scan signal to control the display surface to enter the 8-domain display mode.

In the display panel of this embodiment, the first scan line 111 inputs a scan signal to control the display surface to enter the 4-domain display mode, and the second scan line 112 inputs a scan signal to control the display surface to enter the 8-domain display mode, and only one path of scan signal is needed, compared with the first embodiment, the gate driving circuit can be designed to be simpler.

Example III

Referring to fig. 4, the display device in this embodiment includes a display panel 10 and a main board 20, the main board 20 is connected to the display panel 10, and the display panel 10 includes the display panel 10 disclosed in the first embodiment and the second embodiment. The display device further includes a gate driving circuit 30 and a data driving circuit 40, the gate driving circuit 30 and the data driving circuit may be disposed on the display panel 10, the scan lines 110 are connected to the gate driving circuit 30, and the data lines 120 are connected to the data driving circuit 40. The main board 20 includes a timing controller for detecting display screen information and outputting a data signal to the data driving circuit 40, and generating a data voltage according to the data signal, the data voltage being output to the main area pixel electrode 212 and the sub area pixel electrode 221, driving the liquid crystal molecules to deflect to display a screen.

The display device includes a display panel 10, the display panel 10 includes a plurality of scan lines 110 arranged in a row direction, a plurality of data lines 120 arranged in a column direction, and a pixel unit corresponding to an intersection of the scan lines 110 and the data lines 120, the pixel unit includes a main region sub-pixel 210 and a sub-region sub-pixel 220, the scan line 110 includes a first scan line 111 and a second scan line 112, the main region sub-pixel 210 and the sub-region sub-pixel 220 are both connected to the first scan line 111, the sub-region sub-pixel 220 includes a sub-region pixel electrode 221 and a leakage transistor 222, the second scan line 112 is connected to at least a control terminal of the leakage transistor 222, a first connection terminal of the leakage transistor 222 is connected to the sub-region pixel electrode 221, and a second connection terminal of the leakage transistor 222 is connected to a leakage terminal. The second scan line 112 controls the leakage transistor 222 to be turned on or off, so that the display panel 10 is controlled to switch between 4-domain display and 8-domain display, when a simple picture is displayed, the 4-domain display can be adopted, the transmittance of the display panel 10 is higher, and when a complex picture is displayed, the 8-domain display can be adopted, and the viewing angle and color cast can be improved.

Example IV

In this embodiment, a display driving method is used to drive a display device including the display device disclosed in the third embodiment. Referring to fig. 5, the display driving method includes:

s100: detecting display picture information through a time sequence controller, wherein the display picture comprises a simple picture and a complex picture which are opposite;

s200: when the display screen is confirmed to be a simple screen, the control gate driving circuit 30 outputs a scanning signal to the first scanning line 111;

s300: when the display screen is a complex screen, the control gate driving circuit 30 outputs at least a scan signal to the second scan line 112.

When the display panel 10 is the display panel 10 in the first embodiment, the display screen is a complex screen, the gate driving circuit 30 outputs the scan signal to the second scan line 112, and the gate driving circuit 30 outputs the scan signal to the first scan line 111, so as to control the main area sub-pixel 210 and the sub-area sub-pixel 220 to be turned on simultaneously.

When the display panel 10 is the display panel 10 in the second embodiment, the display screen is a complex screen, and the gate driving circuit 30 outputs the scan signal to the second scan line 112 to control the main area sub-pixel 210 and the sub-area sub-pixel 220 to be turned on simultaneously.

The 8-domain display has improved viewing angle and color shift compared to the 4-domain display, but the voltage of the sub-region sub-pixel 220 is partially discharged through the drain transistor 222, and the transmittance of the sub-region sub-pixel 220 is lower, resulting in the 8-domain display having lower transmittance than the 4-domain display.

In this embodiment, the timing controller detects the display frame information, when the display frame is a simple frame, the scan line 110 controls the display panel 10 to switch to 4-domain display, the transmittance of the display panel 10 is higher, when the display frame is a complex frame, the scan line 110 controls the display panel 10 to switch to 8-domain display, the viewing angle of the display panel 10 is better and the color shift can be improved, that is, the display panel 10 is controlled to switch between 4-domain display and 8-domain display by detecting the display frame, and both the transmittance and the viewing angle of the display panel 10 are considered.

In some embodiments, the display screen is confirmed to be a complex screen, the gate driving circuit 30 outputs a scan signal to the second scan line 112, and the gate driving circuit 30 outputs a scan signal to the first scan line 111, so as to control the main area sub-pixel 210 and the sub-area sub-pixel 220 to be turned on simultaneously. The gate driving circuit 30 outputs the same timing of signals to the first scan line 111 and the second scan line 112.

The timing of the signals output from the gate driving circuit 30 to the first scan line 111 and the second scan line 112 is the same, and the gate driving circuit 30 can be designed to be simpler.

The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly, and may be fixedly attached, detachably attached, or integrally formed, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

In the description of the present specification, reference to the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

While embodiments of the present application have been shown and described, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made in the above embodiments by those skilled in the art within the scope of the application, which is therefore intended to be covered by the appended claims and their equivalents.

Claims (10)

1. The display panel comprises a plurality of scanning lines arranged in the row direction, a plurality of data lines arranged in the column direction and pixel units corresponding to the scanning lines and the data line crossing points, wherein each pixel unit comprises a main area sub-pixel and a secondary area sub-pixel, the main area sub-pixel and the secondary area sub-pixel are respectively positioned on two sides of the scanning line.

2. The display panel according to claim 1, wherein the main region sub-pixel includes a first transistor and a main region pixel electrode, the first transistor includes a first control terminal, a first connection terminal, and a second connection terminal, the first control terminal of the first transistor is connected to the first scan line, the first connection terminal of the first transistor is connected to the data line, and the second connection terminal of the first transistor is connected to the main region pixel electrode;

the sub-region sub-pixel further comprises a second transistor, the second transistor comprises a first control end, a first connection end and a second connection end, the first control end of the second transistor is connected with the first scanning line, the first connection end of the second transistor is connected with the data line, and the second connection end of the second transistor is connected with the sub-region pixel electrode.

3. The display panel of claim 2, wherein the first transistor further comprises a second control terminal, the second control terminal of the first transistor being connected to the second scan line;

the second transistor further comprises a second control end, and the second control end of the second transistor is connected with the second scanning line.

4. The display panel according to claim 2, further comprising a plurality of shared discharge lines arranged in a column direction, wherein the drain terminal comprises the shared discharge line, wherein the second connection terminal of the drain transistor is connected to the shared discharge line of a corresponding column thereof, and wherein all the shared discharge lines are connected.

5. The display panel of claim 4, wherein the shared discharge line comprises a plurality of first segments and a plurality of second segments, adjacent the first segments and the second segments in a same column are connected, the primary region pixel electrode comprises a primary region longitudinal keel, the secondary region pixel electrode comprises a secondary region longitudinal keel, an orthographic projection of the first segments on the primary region pixel electrode is located within or coincident with the primary region longitudinal keel, and an orthographic projection of the second segments on the secondary region pixel electrode is located within or coincident with the secondary region longitudinal keel.

6. The display panel of claim 4, wherein the shared discharge line is disposed at the same layer as the data line.

7. The display panel of claim 2, wherein the sub-region sub-pixel further includes a sub-region common line forming a sub-region storage capacitance with the sub-region pixel electrode, the drain terminal being the sub-region common line.

8. A display device, comprising:

the display panel according to any one of claims 1 to 7;

and the main board is connected with the display panel.

9. A display driving method for the display device according to claim 8, further comprising a gate driving circuit connected to the scanning line, the display driving method comprising:

detecting display picture information through a time sequence controller, wherein the display picture comprises a simple picture and a complex picture which are opposite;

when the display picture is confirmed to be a simple picture, controlling the grid driving circuit to output a scanning signal to the first scanning line;

and when the display picture is confirmed to be a complex picture, controlling the grid driving circuit to at least output a scanning signal to the second scanning line.

10. The display driving method according to claim 9, wherein the gate driving circuit outputs the first scan line signal and the second scan line signal at the same timing.