CN115101024B - Pixel structure, array substrate and display panel - Google Patents
Pixel structure, array substrate and display panel Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0439—Pixel structures
- G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0242—Compensation of deficiencies in the appearance of colours
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
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Abstract
The application discloses pixel structure, array substrate and display panel, this pixel structure includes: a plurality of data lines; a plurality of scan lines; the scanning lines are arranged vertically to the data lines and define a plurality of pixel areas, each pixel area is provided with two sub-pixels along the extending square of the scanning line, the grid electrodes of the two sub-pixels are connected with two different scanning lines, and the source electrodes of the two sub-pixels are connected with the same data line; or, two sub-pixels in each pixel area are respectively connected with the same data line with the sub-pixels in the adjacent pixel areas; each sub-pixel comprises a main pixel and a sub-pixel which are arranged along the column direction. The color cast problem of the liquid crystal display of the conventional VA mode can be solved.
Description
Technical Field
The present disclosure relates to the field of liquid crystal display technologies, and in particular, to a pixel structure, an array substrate, and a display panel.
Background
The liquid crystal display panel is generally composed of a color filter substrate, a thin film transistor array substrate and a liquid crystal layer arranged between the two substrates, wherein a pixel electrode and a common electrode are respectively arranged on the opposite inner sides of the two substrates, and the liquid crystal molecules are controlled to change directions by applying voltage, so that light rays of the backlight module are refracted to generate a picture. The liquid crystal display includes a Twisted Nematic (TN) mode, an Electronically Controlled Birefringence (ECB) mode, a Vertical Alignment (VA) mode, and the like, wherein the VA mode is a common display mode having advantages of high contrast ratio, wide viewing angle, no rubbing alignment, and the like. However, since VA mode adopts vertically rotated liquid crystal, the difference of birefringence of liquid crystal molecules is relatively large, resulting in serious color shift (color shift) problem at a large viewing angle. With the development of liquid crystal display technology, the size of a display screen is larger and larger, and the poor performance of visual character bias is highlighted by using a PSVA (polymer stable vertical alignment) pixel with 4 domains.
Disclosure of Invention
The main purpose of the present application is to provide a pixel structure, which aims to solve the problem of poor color deviation of the conventional VA-mode liquid crystal display.
The scanning lines are arranged vertically to the data lines and define a plurality of pixel areas, each pixel area is provided with two sub-pixels along the extending square of the scanning line, the grid electrodes of the two sub-pixels are connected with two different scanning lines, and the source electrodes of the two sub-pixels are connected with the same data line;
or, two sub-pixels in each pixel area are respectively connected with the same data line with the sub-pixels in the adjacent pixel areas; wherein,,
each sub-pixel comprises a main pixel and a sub-pixel which are arranged along the column direction;
in each pixel region, the main pixels and the sub-pixels of the two sub-pixels arranged along the extending direction of the scanning line are arranged in a rotationally symmetrical manner along the extending direction of the data line.
Optionally, the pixel structure further includes:
a plurality of first common electrode lines;
the pixel areas in the same row are correspondingly provided with a first common electrode line, the first common electrode line is provided with a common section and surrounding sections corresponding to the sub-pixels, the common section extends along the direction of the scanning line, each surrounding section surrounds the sub-pixels, and two leading-out ends surrounded by each surrounding section are respectively connected with the common section;
A plurality of second common electrode lines;
the second common electrode wires are arranged in parallel with the data wires, and one second common electrode wire is arranged between every two adjacent data wires;
two sub-pixels in the same pixel region are connected with the same second common electrode line.
Optionally, each of the sub-pixels includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a main pixel electrode, and a sub-pixel electrode;
the first thin film transistor, the second thin film transistor and the third thin film transistor are respectively arranged on one side, close to the scanning line, of the main pixel electrode, the grid electrodes of the first thin film transistor, the second thin film transistor and the third thin film transistor are connected with the same scanning line, the source electrodes of the first thin film transistor and the second thin film transistor are connected with the same data line, the source electrode of the third thin film transistor is connected with the drain electrode of the second thin film transistor, and the drain electrode of the third thin film transistor is connected with the second common electrode line;
a first connecting wiring is arranged between the drain electrode of the first thin film transistor and the main pixel electrode, and a second connecting wiring is also arranged between the drain electrode of the second thin film transistor and the sub pixel electrode.
Optionally, the second connection trace is disposed across the main pixel electrode and is connected to the sub-pixel electrode; or,
the second connection wiring is extended from the drain electrode of the second thin film transistor along the peripheral side of the main pixel electrode and is connected with the sub pixel electrode.
Optionally, sources of the two first thin film transistors and the two second thin film transistors in the same pixel region are connected to the same data line, and the two first thin film transistors and the two second thin film transistors are arranged in the same column with a main pixel electrode and a sub pixel electrode of one of the sub pixels in the same pixel region; wherein,,
the first thin film transistor and the second thin film transistor are arranged in the same column with the main pixel electrode and the secondary pixel electrode respectively, and the second thin film transistor is arranged at one side of the first thin film transistor, which is away from the main pixel electrode;
the first thin film transistor is arranged on one side of the second thin film transistor away from the main pixel electrode, and the second thin film transistor is arranged in the first thin film transistor and the second thin film transistor which are arranged in the adjacent columns respectively.
The application also provides an array substrate, which comprises a substrate and the pixel structure;
the substrate base plate is formed with:
a first metal layer forming a plurality of scan lines, a plurality of first common electrode lines, a plurality of gates of first thin film transistors, a plurality of gates of second thin film transistors, and a plurality of gates of third thin film transistors;
the first insulating layer is arranged on the first metal layer;
the second metal layer is arranged on the first insulating layer, and forms a plurality of data lines, a plurality of second common electrode lines, a plurality of sources and drains of the first thin film transistors, a plurality of sources and drains of the second thin film transistors and a plurality of sources and drains of the third thin film transistors;
the second insulating layer is arranged on the second metal layer;
a transparent conductive layer forming a plurality of main pixel electrodes and a plurality of sub pixel electrodes, respectively; wherein,,
each of the first thin film transistor, the second thin film transistor, the third thin film transistor, the main pixel electrode and the sub pixel electrode form a sub pixel, and each of the two sub pixels forms a pixel region.
Optionally, the first connection trace includes a first metal trace segment formed by the second metal layer, and a first via connection segment disposed between the transparent conductive layer and the first metal trace segment and penetrating the second insulating layer; or,
The first connecting wire comprises a first metal wire section formed by a second metal layer, a first transparent wire section formed by the transparent conductive layer, and a first via connecting section arranged between the first transparent wire section and the first metal wire section and penetrating through the second insulating layer.
Optionally, the second connection trace includes a second metal trace segment formed by the second metal layer, and a second via connection segment disposed between the transparent conductive layer and the second metal trace segment and penetrating the second insulating layer; wherein,,
the second via connection section is arranged on a central line in the row direction of the secondary pixel electrode, and the second metal wire section is arranged across the primary pixel electrode.
Optionally, the second connection trace includes a second metal trace segment formed by a second metal layer, a second transparent trace segment formed by the transparent conductive layer, and a second via connection segment disposed between the second transparent trace segment and the second metal trace segment and penetrating the second insulating layer; wherein,,
the second via hole connecting section is arranged in a device area where the second thin film transistor is located, and the second transparent wire section extends along the peripheral side of the main pixel electrode.
The application also provides a display panel which comprises the pixel structure; or,
the color film substrate comprises the array substrate and the color film substrate which is arranged opposite to the array substrate.
In the technical scheme, the pixel structure comprises a plurality of Data lines Data and a plurality of scanning lines Gn, the plurality of scanning lines Gn are vertically arranged with the plurality of Data lines Data and define a plurality of pixel areas, each pixel area is provided with two sub-pixels along the extending square of the scanning line Gn, the grid of each sub-pixel is connected with two different scanning lines Gn, the source of each sub-pixel is connected with the same Data line Data, or the two sub-pixels in each pixel area are respectively connected with the same Data line Data with the sub-pixels in the adjacent pixel areas, so that double-grid driving is realized. According to the method, the double-grid driving mode is adopted, so that the consumption of Source COF is reduced, and the cost of the liquid crystal panel can be effectively reduced. Meanwhile, each sub-pixel is divided into two, namely a main pixel and a sub-pixel which are arranged along the column direction, and the sub-pixel is divided into eight areas by adopting a multi-domain vertical alignment technology, so that liquid crystals in each area fall to different directions after voltage is applied, and the display effect of 8 domains is realized. According to the pixel array structure, the main pixels and the sub-pixels are arranged in a staggered mode, so that the pixels in the staggered mode can achieve 8domain display effects under the condition that scanning lines Gn are not increased when being applied to double-grid driving, the display effects of 8domain are achieved, visual angle performance of a display panel can be effectively improved, the color cast problem is solved, the display effects of the display panel are improved, the problems that the wiring of a pixel structure is complex, crosstalk is easy to generate, the display effects are affected and the like can be solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from the structures shown in these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a pixel structure according to a first embodiment of the normal architecture of the present application;
FIG. 2 is a schematic diagram of a pixel structure according to a second embodiment of the normal architecture of the present application;
FIG. 3 is a schematic diagram of a pixel structure according to a third embodiment of the normal architecture of the present application;
FIG. 4 is a schematic structural diagram of a first embodiment of a pixel structure of the long-short-hand architecture of the present application;
FIG. 5 is a schematic diagram of a second embodiment of a pixel structure of the long-short-hand architecture of the present application;
FIG. 6 is a schematic structural diagram of an embodiment of an array substrate of the present application;
fig. 7 is a schematic structural diagram of an embodiment of a display panel of the present application.
Reference numerals illustrate:
| reference numerals | Name of the name | Reference numerals | Name of the name |
| Data | Data line | T3 | Third thin film transistor |
| Gn～Gn+7 | Scanning line | Q1 | First via connection section |
| main pixel | Main pixel electrode | Q2 | Second via connection section |
| Sub pixel | Sub-pixel electrode | S1 | Surrounding section |
| M1 | First common electrode line | S2 | Public segment |
| M2 | Second common electrode line | 100 | Array substrate |
| L1 | First connecting wire | 101 | Effective display area |
| L2 | Second connecting wiring | 102 | Driving circuit of display panel |
| T1 | First thin film transistor | 200 | Color film substrate |
| T2 | Second thin film transistor | 300 | Liquid crystal layer |
The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that, in the embodiment of the present application, directional indications (such as up, down, left, right, front, and rear … …) are referred to, and the directional indications are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present application, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application.
At present, with the development of active thin film transistor liquid crystal display technology, the size of a display screen is increasingly larger, and the demand of people for a large viewing angle range is also increasingly larger, because a Vertical Alignment (VA) liquid crystal display panel adopts vertically rotated liquid crystals, the difference of the birefringence of liquid crystal molecules is relatively large, so that the color shift (color shift) problem under a large viewing angle is relatively serious, in order to improve the viewing angle performance of the panel and improve the color shift problem, a Multi-domain vertical alignment technology (MVA) is generally adopted, namely one sub-pixel is divided into a plurality of areas, and the liquid crystals in each area fall into different directions after voltage is applied, so that the effect seen in all directions tends to be uniform, namely, the viewing angle performance and the color shift problem of the PSVA pixel adopting 4 domains are still not ideal.
Therefore, the present application proposes a pixel structure applied to an array substrate, the array substrate further includes a substrate, a first metal layer and a second metal layer are formed on the substrate, the first metal layer forms a plurality of scan lines Gn, the second metal layer forms a plurality of Data lines Data, referring to fig. 1 to 5, in an embodiment, the pixel structure includes:
the scanning lines Gn and the Data lines Data are vertically arranged and define a plurality of pixel areas, each pixel area is provided with two sub-pixels along the extending square of the scanning line Gn, the grid electrodes of the two sub-pixels are connected with two different scanning lines Gn, and the source electrodes of the two sub-pixels are connected with the same Data line Data;
or, two sub-pixels in each pixel area are respectively connected with the same Data line Data with the sub-pixels in the adjacent pixel areas; wherein,,
each sub-pixel comprises a main pixel and a sub-pixel which are arranged along the column direction;
in each pixel region, the main pixels and the sub-pixels of the two sub-pixels arranged along the extending direction of the scanning line Gn are arranged in 180-degree rotation symmetry along the extending direction of the Data line Data.
The pixel structure comprises a plurality of pixels, a plurality of Data lines Data and a plurality of scanning lines Gn, wherein the pixels comprise at least three sub-pixels, different sub-pixels can display different primary color lights, and according to the principle of spatial color mixing, different primary color lights can be mixed according to a certain proportion to display various colors. Generally, a pixel includes at least an R sub-pixel, a G sub-pixel and a B sub-pixel, and these three sub-pixels are hereinafter all classified as sub-pixels, so as to describe the technical solution of the present application in detail. Of course, those skilled in the art may select other primary colors for combination without performing any inventive effort, and adjust the scheme of the present application accordingly to improve the color display effect of the display device, which is not described herein. The plurality of sub-pixels are arranged in a rectangular array shape, each sub-pixel is respectively and electrically connected with the Data line Data and the scanning line Gn, the corresponding sub-pixel is respectively opened under the action of a scanning signal on the scanning line Gn, and when the sub-pixel is in an opened state, the sub-pixel is charged under the driving action of a driving signal on the Data line Data, so that certain brightness is displayed, and different colors are displayed under the filtering action of corresponding photoresistors. The driving signal may be obtained according to gray scales of pixels or sub-pixels in the frame to be displayed.
The driving modes of the display panel are usually normal arrangement, DRD arrangement, and tri-gate arrangement, that is, single gate driving, double gate driving, and triple gate driving, and in this embodiment, the driving mode of the display panel is DRD arrangement. Specifically, two scan lines Gn extending in the row direction are disposed between two adjacent rows of sub-pixels, and two adjacent sub-pixels are used as a pixel area, and one Data line Data extending in the column direction is disposed between each two adjacent columns of pixel areas, that is, the number of the scan lines Gn is twice that of the Data lines Data. Thus, the number of Data lines Data will be reduced, and correspondingly, the number of Source COFs (Source driving) for signal transmission will be reduced. Along with the gradual maturation of the GOA technology, the application range is wider and wider, gate COF (Gate driving) is not used any more, and the cost of COF is mainly concentrated on the Source COF side, so that the cost of the liquid crystal panel can be effectively reduced by reducing the number of Source COFs, and therefore, the use amount of Source COF can be reduced by adopting a double-Gate driving mode, so that the cost of the liquid crystal panel is effectively reduced. Further, the dual gate driving has two architectures, one is a normal architecture, as shown in fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a pixel structure of the normal architecture, that is, two sub-pixels in each pixel area are respectively connected with the same Data line Data with sub-pixels in adjacent pixel areas. In the other case, the long-short hand architecture is shown in fig. 4, and fig. 4 is a schematic structural diagram of an embodiment of a pixel structure of the long-short hand architecture, that is, sources of two sub-pixels in the same pixel area are connected to the same Data line Data, and because distances between the two sub-pixels and the same Data line Data are different, lengths of connection wires are naturally different, so that the pixel structure is called a long-short hand architecture.
Based on the above-mentioned dual gate driving, in this embodiment, each sub-pixel is divided into two, and is divided into a main pixel and a sub-pixel that are arranged along the column direction, and a multi-domain vertical alignment technology is adopted, so that each main pixel and sub-pixel are divided into four regions, that is, one sub-pixel is divided into eight regions, and the liquid crystal in each region falls down to different directions after voltage is applied, so that the effects seen in the respective directions tend to be uniform, for example, a 3T-8 domain pixel structure, or other 8domain pixel structures can be adopted, so as to achieve the display effect of 8 domains.
In this embodiment, the main pixels and the sub-pixels are further arranged in a staggered manner, specifically, for the sub-pixels in the same row, if the main pixels and the sub-pixels in one sub-pixel are sequentially the main pixels and the sub-pixels along the column direction, then the main pixels and the sub-pixels in the sub-pixels adjacent to the main pixels are sequentially the sub-pixels and the main pixels along the column direction, that is, the sub-pixels adjacent to the main pixels along the row direction, as shown in fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a pixel structure with a normal architecture. According to the pixel array structure, the main pixels and the sub-pixels are arranged in a staggered arrangement mode, so that the pixels in the arrangement mode can realize an 8domain display effect under the condition that scanning lines Gn are not increased when being applied to double-grid driving, the problems that the wiring of a pixel structure is complex, crosstalk is easy to generate and the display effect is influenced can be solved.
In the technical scheme, the pixel structure comprises a plurality of Data lines Data and a plurality of scanning lines Gn, the plurality of scanning lines Gn are vertically arranged with the plurality of Data lines Data and define a plurality of pixel areas, each pixel area is provided with two sub-pixels along the extending square of the scanning line Gn, the grid of each sub-pixel is connected with two different scanning lines Gn, the source of each sub-pixel is connected with the same Data line Data, or the two sub-pixels in each pixel area are respectively connected with the same Data line Data with the sub-pixels in the adjacent pixel areas, so that double-grid driving is realized. According to the method, the double-grid driving mode is adopted, so that the consumption of Source COF is reduced, and the cost of the liquid crystal panel can be effectively reduced. Meanwhile, each sub-pixel is divided into two, namely a main pixel and a sub-pixel which are arranged along the column direction, and the sub-pixel is divided into eight areas by adopting a multi-domain vertical alignment technology, so that liquid crystals in each area fall to different directions after voltage is applied, and the display effect of 8 domains is realized. According to the pixel array structure, the main pixels and the sub-pixels are arranged in a staggered mode, so that the pixels in the staggered mode can achieve 8domain display effects under the condition that scanning lines Gn are not increased when being applied to double-grid driving, the display effects of 8domain are achieved, visual angle performance of a display panel can be effectively improved, the color cast problem is solved, the display effects of the display panel are improved, the problems that the wiring of a pixel structure is complex, crosstalk is easy to generate, the display effects are affected and the like can be solved.
Referring to fig. 1 to 5, in an embodiment, the pixel structure further includes:
a plurality of first common electrode lines M1;
the pixel areas in the same row are correspondingly provided with a first common electrode line M1, the first common electrode line M1 is provided with a common section S2 and a surrounding section S1 corresponding to each sub-pixel, the common section S2 extends along the direction of a scanning line Gn, each surrounding section S1 surrounds the sub-pixel, and two leading-out ends surrounded by each surrounding section S1 are respectively connected with the common section S2.
It will be appreciated that in a display panel, in order to reduce the variation of the pixel level on the pixel electrode as much as possible, to alleviate flicker of a picture in the display panel, and to improve the display effect, the storage capacitance should be increased as much as possible under other conditions, and the storage capacitance is related to the overlapping area of the pixel electrode and the common electrode, the larger the overlapping area is, the larger the storage capacitance is.
For this reason, in the present embodiment, the pixel structure further includes a plurality of first common electrode lines M1, and one first common electrode line M1 is disposed in correspondence with the pixel regions of the same row, specifically, each first common electrode line M1 may be divided into a common segment S2 and a surrounding segment S1 disposed in correspondence with each sub-pixel, where the common segment S2 extends along the row direction, the surrounding segment S1 is disposed around the sub-pixel, and the surrounding segment S1 is disposed in a shape of a mouth after being connected to the common segment S2, and is disposed in an overlapping manner with the main pixel electrode main pixel and the sub-pixel electrode sub-pixel, so that the main pixel electrode main pixel and the sub-pixel electrode sub-pixel form storage capacitors with the common electrode line, as shown in fig. 2, and fig. 2 is a schematic structural diagram of an embodiment of a pixel structure with a normal architecture. By the arrangement, the overlapping area between the first common electrode line M1 and the main pixel electrode main pixel and the overlapping area between the first common electrode line M1 and the sub pixel electrode sub pixel can be increased, so that the capacitance of the storage capacitor is increased, flicker of pictures in the display panel is relieved, and the display effect is improved. On the other hand, although the pixel electrode is generally made of transparent Indium Tin Oxide (ITO), it is considered that the common electrode is generally made of non-transparent metal, and thus, the non-transparent common electrode will cause a decrease in light transmission area in the pixel, that is, a decrease in aperture ratio of the pixel, a decrease in display brightness of the display panel as a whole, or an increase in power consumption of a required backlight light source. In the present embodiment, the common electrode is disposed around the pixel electrode on the peripheral side of the pixel electrode and overlaps the pixel electrode to form a storage capacitor, thereby avoiding a decrease in the pixel aperture ratio to some extent.
Referring to fig. 1 to 5, in an embodiment, the pixel structure further includes:
a plurality of second common electrode lines M2;
the second common electrode line M2 is arranged in parallel with the Data lines Data, and one second common electrode line M2 is arranged between every two adjacent Data lines Data;
two sub-pixels in the same pixel region are connected to the same second common electrode line M2.
It can be understood that the sub-pixel has a discharging process in completing the multi-domain display, so a common wiring for releasing charges of the pixel is generally required to be provided in the display panel, and therefore, in this embodiment, as shown in fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a pixel structure with a normal architecture, the pixel structure further includes a plurality of second common electrode lines M2 disposed parallel to the Data lines Data, and one second common electrode line M2 is provided between every two adjacent Data lines Data, and two sub-pixels in the same pixel area are connected to the same second common electrode line M2. Specifically, when the scanning line Gn drives the thin film transistor to be turned on, the main pixel and the sub-pixel start to charge, and at the same time, the main pixel discharges a part of the charges through the second common electrode line M2, so as to complete the multi-domain display effect.
Referring to fig. 1 to 5, in an embodiment, each of the sub-pixels includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a main pixel electrode main pixel and a sub-pixel electrode sub pixel;
the first thin film transistor T1 and the second thin film transistor T2 are respectively disposed on a side of the main pixel electrode main pixel, which is close to the scanning line Gn, the gates of the first thin film transistor T1 and the second thin film transistor T2 are connected to the same scanning line Gn, the sources of the first thin film transistor T1 and the second thin film transistor T2 are connected to the same Data line Data, the source of the third thin film transistor T3 is connected to the drain of the second thin film transistor T2, and the drain of the third thin film transistor T3 is connected to the second common electrode line;
a first connection line L1 is disposed between the drain electrode of the first thin film transistor T1 and the main pixel electrode main pixel, and a second connection line L2 is disposed between the drain electrode of the second thin film transistor T2 and the sub pixel electrode sub pixel.
In this embodiment, each sub-pixel includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a main pixel electrode main pixel and a sub-pixel electrode sub-pixel, wherein a drain electrode of the first thin film transistor T1 is connected to the main pixel electrode main pixel through a first connection trace L1, and a drain electrode of the second thin film transistor T2 is connected to the sub-pixel electrode sub-pixel through a second connection trace L2. The drain electrode of the second thin film transistor is further connected to the source electrode of the third thin film transistor T3, that is, the source electrode of the third thin film transistor T3 is connected to the second connection line L2. The first thin film transistor T1 and the second thin film transistor T2 control the Data line Data to charge the corresponding main pixel and sub-pixel under the action of the scanning signal on the scanning line Gn, and correspondingly, the main pixel and the sub-pixel generate certain display brightness under the combined action of the scanning signal on the scanning line Gn and the Data signal on the Data line Data. Meanwhile, since the source electrode of the third thin film transistor T3 is connected to the second connection trace L2, the third thin film transistor T3 is turned on at this time, and the charging current of the sub-pixel electrode is split to the second common electrode line, so that the voltage of the main pixel electrode and the voltage of the sub-pixel electrode are different, thereby realizing the display effect of a large viewing angle.
Optionally, the second connection trace L2 is disposed across the main pixel electrode main pixel and is connected to the sub pixel electrode sub pixel.
In an embodiment, the second thin film transistor T2 and the third thin film transistor T3 are disposed on a side of the first thin film transistor T1 facing away from the main pixel electrode, i.e. the second thin film transistor T2 and the third thin film transistor T3 are farther from the main pixel electrode than the first thin film transistor T1. The second connection trace L2 is connected to the sub-pixel electrode sub across the main pixel electrode main pixel, and it is understood that on the array substrate, the second connection trace L2 may be located at a different layer from the pixel electrode, for example, the second connection trace L2 may form a metal trace on the second metal layer and be connected to the sub-pixel electrode sub located at the transparent conductive layer through the conductive hole. So set up, because the second is connected and is walked line L2 and pixel electrode department different structural layers, need not to consider integrated into one piece's technology degree of difficulty during production, make things convenient for product batch production. Meanwhile, when the device is used in the later period, if the connection wiring is broken accidentally, the connection wiring and the pixel electrode are arranged on different structural layers, so that maintenance personnel can repair or replace the broken wiring conveniently, and the operation and maintenance cost is reduced. On the other hand, when setting up the second connection line L2, can also make the second connection line L2 and Data line Data parallel arrangement, and be connected with the central point of sub-pixel electrode sub pixel, so for the second connection line L2 all keeps the furthest distance with Data line Data and second public electrode line M2, can effectively reduce the signal crosstalk between the circuit, and makes the left and right sides regional symmetry of pixel electrode, can reduce the influence of line to aperture ratio and penetration rate. Meanwhile, the center point of the sub-pixel electrode sub-pixel of the second connection wiring L2 is connected, so that the charging speed of the sub-pixel electrode sub-pixel can be increased, the response speed of the sub-pixel electrode sub-pixel is increased, and the display effect of the display panel is further improved.
Optionally, the second connection trace L2 extends from the drain of the second thin film transistor T2 along the peripheral side of the main pixel electrode main pixel, and is connected to the sub pixel electrode sub pixel.
In another embodiment, the second thin film transistor T2 and the third thin film transistor T3 are disposed on the side of the first thin film transistor T1 facing away from the main pixel electrode, i.e. the second thin film transistor T2 and the third thin film transistor T3 are farther from the main pixel electrode than the first thin film transistor T1. The second connection trace L2 is wound around the peripheral side of the main pixel electrode main pixel and is connected with the sub pixel electrode sub pixel, and it can be understood that, because the second connection trace L2 is wound around the peripheral side of the main pixel electrode main pixel, that is, the second connection trace L2 has no overlapping portion with the main pixel electrode main pixel, the second connection trace L2 can be disposed on the transparent conductive layer where the pixel electrode is located on the array substrate. So set up, reduced the second on the one hand and connected the wiring L2 arrange the degree of difficulty for second is connected and is walked line L2 and can be formed with sub-pixel electrode sub pixel integration, has reduced production technology's degree of difficulty, can not increase production process, is favorable to guaranteeing production efficiency, and then reduces the manufacturing cost of mass production. On the other hand, the second connecting wire L2 is wound on the peripheral side of the main pixel electrode, so that the overlapping part of the second connecting wire L2 and the pixel electrode is reduced, parasitic capacitance is reduced, the penetration rate and the aperture ratio are increased, the display effect of the display panel is improved, and the energy consumption required by display is reduced.
Referring to fig. 1 to 5, in an embodiment, sources of the two first thin film transistors T1 and the two second thin film transistors T2 in the same pixel region are connected to the same Data line Data, and the two first thin film transistors T1 and the two second thin film transistors T2 are disposed in the same column with a main pixel electrode main pixel and a sub pixel electrode sub pixel of one of the sub pixels in the same pixel region.
In the present embodiment, the sources of the two first thin film transistors T1 and the two second thin film transistors T2 in the same pixel region are connected to the same Data line Data, i.e. a dual-gate driving with long and short hands is adopted. It will be appreciated that, due to the long and short hand architecture, a Column Inversion driving method (Column Inversion) may be selected when driving the pixels, i.e. the polarities of the Data signals received on the adjacent Data lines Data are opposite. When the liquid crystal panel is driven by column inversion, the polarities of the voltages of the adjacent Data lines Data are opposite, and after space averaging, the flicker phenomenon of display can be effectively reduced, the transverse crosstalk is reduced, and meanwhile, the driving power consumption of pixels can be effectively reduced.
Optionally, the first thin film transistor T1 and the second thin film transistor T2 are in the same column with the main pixel electrode main pixel and the sub pixel electrode sub pixel, and the second thin film transistor T2 is disposed at a side of the first thin film transistor T1 away from the main pixel electrode main pixel;
the first thin film transistor T1 and the second thin film transistor T2 are in adjacent columns with the main pixel electrode main pixel and the sub pixel electrode sub pixel, and the first thin film transistor T1 is disposed at a side of the second thin film transistor T2 away from the main pixel electrode main pixel.
In an embodiment, in a pixel region, two first thin film transistors T1 and two second thin film transistors T2 are disposed in the same row with the main pixel electrode main pixel and the sub pixel electrode sub pixel of one sub pixel, at this time, the main pixel electrode main pixel and the sub pixel electrode sub pixel of one sub pixel are disposed in the same row with the corresponding connected thin film transistors, and the main pixel electrode main pixel and the sub pixel electrode sub pixel of the other sub pixel are disposed in adjacent rows with the corresponding connected thin film transistors. At this time, in order to avoid the staggered or overlapped routing, when the first thin film transistor T1 and the second thin film transistor T2 are in the same row with the pixel electrode correspondingly connected, the second thin film transistor T2 is disposed at a side of the first thin film transistor T1 facing away from the main pixel electrode main pixel; when the first thin film transistor T1 and the second thin film transistor T2 are in adjacent columns with the pixel electrodes correspondingly connected, the first thin film transistor T1 is disposed on a side of the second thin film transistor T2 away from the main pixel electrode main pixel, as shown in fig. 4, and fig. 4 is a schematic structural diagram of an embodiment of a pixel structure of a long-short hand architecture. By the arrangement, connection wirings when the first thin film transistor T1 and the second thin film transistor T2 are connected with corresponding pixel electrodes are not staggered or overlapped, wiring arrangement difficulty can be reduced, signal crosstalk is reduced, and display effect of the display panel is further improved.
Referring to fig. 6, the present application further provides an array substrate, including a substrate and a pixel structure as described above;
the substrate base plate is formed with:
a first metal layer forming a plurality of scan lines Gn, a plurality of first common electrode lines M1, a plurality of gates of first thin film transistors T1, a plurality of gates of second thin film transistors T2, and a plurality of gates of third thin film transistors T3;
the first insulating layer is arranged on the first metal layer;
a second metal layer disposed on the first insulating layer, wherein the second metal layer forms a plurality of Data lines Data, a plurality of second common electrode lines M2, a plurality of sources and drains of the first thin film transistors T1, a plurality of sources and drains of the second thin film transistors T2, and a plurality of sources and drains of the third thin film transistors T3;
the second insulating layer is arranged on the second metal layer;
a transparent conductive layer respectively forming a plurality of main pixel electrodes main pixel and a plurality of sub pixel electrodes sub pixel; wherein,,
each of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the main pixel electrode main pixel and the sub pixel electrode sub pixel constitute a sub pixel, and each of the two sub pixels constitutes a pixel region.
Referring to fig. 6, an array substrate is disclosed, the array substrate includes an effective display area 101 and an inactive display area, the substrate is disposed in the effective display area 101, the inactive display area surrounds the periphery of the effective display area 101, and a driving circuit 102 of the display panel is disposed in the inactive display area of the array substrate.
In this embodiment, the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 each include two metal layers, two insulating layers, an active layer and an ohmic contact layer. The two metal layers may be made of the same or different materials, and may be made of aluminum or copper, for example. The scanning line Gn, the first common electrode line M1 and the gate electrode of the thin film transistor may be implemented by using the same metal layer, and specifically, the scanning line Gn, the first common electrode line M1 and the gate electrode of the thin film transistor may be formed by patterning the first metal layer M1. Similarly, the Data line Data, the second common electrode line M2, and the drain and source of the thin film transistor may be implemented by using the same metal layer, and specifically, the Data line Data, the second common electrode line M2, and the drain and source of the thin film transistor may be formed by patterning the second metal layer M2. In this embodiment, the first insulating layer is a gate insulating layer, and the second insulating layer is a passivation layer. The transparent conductive layer may form a main pixel electrode and a sub pixel electrode, and the transparent conductive layer ITO may be an ITO thin film layer.
In this embodiment, each of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the main pixel electrode main pixel and the sub pixel electrode sub pixel constitute a sub pixel, each of the two sub pixels constitutes a pixel region, two scan lines Gn extending in the row direction are disposed between each two adjacent rows of pixel regions, and one Data line Data extending in the column direction is disposed between each two adjacent columns of pixel regions, so as to form a dual-gate driving architecture. Correspondingly, the grid electrodes of the thin film transistors of the two sub-pixels in the same pixel area are connected with two different scanning lines Gn, the source electrodes of the thin film transistors of the two sub-pixels in the same pixel area are connected with the same Data line Data, or the source electrodes of the thin film transistors of the two sub-pixels in each pixel area are respectively connected with the same Data line Data with the source electrodes of the thin film transistors of the sub-pixels in the adjacent pixel area, and the connection modes of the two Data lines Data respectively correspond to a normal structure and a long-short-hand structure of the double-grid type driving.
In addition, the array substrate includes the pixel structure, and the specific structure of the pixel structure refers to the above embodiment, and since the array substrate adopts all the technical solutions of all the above embodiments, at least the array substrate has all the beneficial effects brought by the technical solutions of the above embodiments, which are not described in detail herein.
Referring to fig. 1 to 5, in an embodiment, the first connection trace L1 includes a first metal trace segment formed by the second metal layer, and a first via connection segment Q1 disposed between the transparent conductive layer and the first metal trace segment and penetrating the second insulating layer; or,
the first connection trace L1 includes a first metal trace segment formed by a second metal layer, a first transparent trace segment formed by the transparent conductive layer, and a first via connection segment Q1 disposed between the first transparent trace segment and the first metal trace segment and penetrating through the second insulating layer.
In an embodiment, the first connection trace L1 includes a first metal trace segment formed by a second metal layer, and a first via connection segment Q1 disposed between the transparent conductive layer and the first metal trace segment and penetrating the second insulating layer, i.e. a conductive connection between the drain electrode of the first thin film transistor T1 and the main pixel electrode main pixel may be achieved through a via. For example, as shown in fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a pixel structure with a normal architecture, and a via hole formed in the first connection trace L1 is disposed close to the first thin film transistor T1, that is, the length of a metal trace segment formed by the second metal layer in the first connection trace L1 is reduced, so as to reduce the parasitic capacitance.
In another embodiment, the first connection trace L1 includes a first metal trace segment formed by the second metal layer, a first transparent trace segment formed by the transparent conductive layer, and a first via connection segment Q1 disposed between the first transparent trace segment and the first metal trace segment and penetrating the second insulating layer. For example, as shown in fig. 5, fig. 5 is a schematic structural diagram of an embodiment of a pixel structure of a long-short architecture, which reduces the length of a metal line segment formed by a second metal layer in the first connection line L1, thereby reducing the parasitic capacitance. On the other hand, the through holes are designed outside the pixel area, so that the display area of the pixel area can be enlarged, the penetration rate and the aperture opening ratio are increased, the display effect of the display panel is improved, and the energy consumption required by display is reduced.
Referring to fig. 1 to 5, in an embodiment, the second connection trace L2 includes a second metal trace segment formed by the second metal layer, and a second via connection segment Q2 disposed between the transparent conductive layer and the second metal trace segment and penetrating the second insulating layer; wherein,,
the second via connection section Q2 is disposed on a central line in the sub-pixel column direction, and the second metal line section is disposed across the main pixel electrode main pixel.
In an embodiment, the second connection trace L2 includes a second metal trace segment formed by a second metal layer, and a second via connection segment Q2 disposed between the transparent conductive layer and the second metal trace segment and penetrating through the second insulating layer, that is, a conductive connection between the drain electrode of the second thin film transistor T2 and the main pixel electrode main pixel may be implemented through a via. For example, as shown in fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a pixel structure with a normal architecture, and a via hole formed in the first connection trace L1 is disposed at a central position in a column direction of the sub-pixel electrode sub-pixel, so that a charging speed of the sub-pixel electrode sub-pixel can be increased, a response speed of the sub-pixel electrode sub-pixel can be increased, and a display effect of the display panel can be further improved. Meanwhile, the metal wire section is connected with the center point of the sub-pixel electrode sub-pixel, so that the left and right areas of the pixel electrode are symmetrical, the influence of the metal wire section on the aperture ratio and the penetration rate can be reduced, the second connecting wire L2, the Data wire Data and the second common electrode wire M2 can be kept at the farthest distance, and the signal crosstalk between the lines can be effectively reduced. In addition, when producing, need not to consider integrated into one piece's technology degree of difficulty, make things convenient for product batch production to and when later stage use, if connect the unexpected broken string of line, because connect line and pixel electrode set up in different structural layers, can make things convenient for the maintenance personal to repair or change the broken string, reduce the fortune dimension cost.
Optionally, the second connection trace L2 includes a second metal trace segment formed by a second metal layer, a second transparent trace segment formed by the transparent conductive layer, and a second via connection segment Q2 disposed between the second transparent trace segment and the second metal trace segment and penetrating the second insulating layer; wherein,,
the second via connection section Q2 is disposed in a device area where the second thin film transistor T2 is located, and the second transparent line section extends along the peripheral side of the main pixel electrode main pixel.
In another embodiment, the second connection trace L2 includes a second metal trace segment formed by a second metal layer, a second transparent trace segment formed by a transparent conductive layer, and a second via connection segment Q2 disposed between the second transparent trace segment and the second metal trace segment and penetrating through the second insulating layer. For example, as shown in fig. 3, fig. 3 is a schematic structural diagram of an embodiment of a pixel structure with a normal architecture, and the via hole formed in the second connection trace L2 is disposed in the device area where the thin film transistor is located, on one hand, the via hole is designed outside the pixel area, so that the display area of the pixel area can be enlarged, the penetration rate and the aperture ratio are increased, the display effect of the display panel is improved, and the energy consumption required for display is reduced. On the other hand, the second transparent line section extends along the periphery of the main pixel electrode, so that the arrangement difficulty of the transparent line section is reduced, the transparent line section can be integrally formed with the sub pixel electrode, the difficulty of a production process is reduced, the production procedure is not increased, the production efficiency is guaranteed, and the production cost of batch production is reduced.
Referring to fig. 7, the present application further provides a display panel, where the display device includes the above pixel structure, or includes the above array substrate 100 and a color film substrate 200 disposed opposite to the array substrate.
In this embodiment, the liquid crystal layer 300 is disposed between the array substrate 100 and the color film substrate 200, and the pixel structure and the specific structure of the array substrate refer to the above embodiments, and since the display panel adopts all the technical solutions of all the embodiments, it has at least all the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and all equivalent structural changes made by the specification and drawings of the present application or direct/indirect application in other related technical fields are included in the scope of the claims of the present application.
Claims (9)
1. The utility model provides a pixel structure, is applied to in the array substrate, array substrate still includes the substrate, be formed with first metal level and second metal level on the substrate, first metal level forms many scanning lines, second metal level forms many data lines, its characterized in that, pixel structure includes:
A plurality of second common electrode lines;
the second common electrode wires are arranged in parallel with the data wires, and one second common electrode wire is arranged between every two adjacent data wires;
the scanning lines are arranged vertically to the data lines and define a plurality of pixel areas, each pixel area is provided with two sub-pixels along the extending direction of the scanning line, the grid electrodes of the two sub-pixels are connected with two different scanning lines, and the source electrodes of the two sub-pixels are connected with the same data line;
or, two sub-pixels in each pixel area are respectively connected with the same data line with the sub-pixels in the adjacent pixel areas; wherein,,
two sub-pixels in the same pixel area are connected with the same second common electrode line;
each sub-pixel comprises a main pixel and a sub-pixel which are arranged along the column direction;
in each pixel region, main pixels and sub-pixels of two sub-pixels arranged along the extending direction of the scanning line are arranged in a rotationally symmetrical manner along the extending direction of the data line;
each sub-pixel comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a main pixel electrode and a sub-pixel electrode, wherein the first thin film transistor, the second thin film transistor and the third thin film transistor are respectively arranged on one side, close to the scanning line, of the main pixel electrode, the grid electrodes of the first thin film transistor, the second thin film transistor and the third thin film transistor are connected with the same scanning line, the source electrodes of the first thin film transistor and the second thin film transistor are connected with the same data line, the source electrode of the third thin film transistor is connected with the drain electrode of the second thin film transistor, the drain electrode of the third thin film transistor is connected with the second common electrode line, a first connecting wiring is arranged between the drain electrode of the first thin film transistor and the main pixel electrode, and a second connecting wiring is also arranged between the drain electrode of the second thin film transistor and the sub-pixel electrode.
2. The pixel structure of claim 1, wherein the pixel structure further comprises:
a plurality of first common electrode lines;
the pixel areas in the same row are correspondingly provided with a first public electrode line, the first public electrode line is provided with a public section and surrounding sections corresponding to the sub-pixels, the public section extends along the direction of the scanning line, each surrounding section surrounds the sub-pixels, and two leading-out ends surrounded by each surrounding section are respectively connected with the public section.
3. The pixel structure of claim 1, wherein the second connection trace is disposed across the primary pixel electrode and connected to the secondary pixel electrode; or,
the second connection wiring is extended from the drain electrode of the second thin film transistor along the peripheral side of the main pixel electrode and is connected with the sub pixel electrode.
4. The pixel structure according to claim 1, wherein sources of the two first thin film transistors and the two second thin film transistors in the same pixel region are connected to the same data line, and the two first thin film transistors and the two second thin film transistors are arranged in the same column with a main pixel electrode and a sub pixel electrode of one of the sub pixels in the same pixel region; wherein,,
The first thin film transistor and the second thin film transistor are arranged in the same column with the main pixel electrode and the secondary pixel electrode respectively, and the second thin film transistor is arranged at one side of the first thin film transistor, which is away from the main pixel electrode;
the first thin film transistor is arranged on one side of the second thin film transistor away from the main pixel electrode, and the second thin film transistor is arranged in the first thin film transistor and the second thin film transistor which are arranged in the adjacent columns respectively.
5. An array substrate, comprising a substrate and the pixel structure of any one of claims 1-4;
the substrate base plate is formed with:
a first metal layer forming a plurality of scan lines, a plurality of first common electrode lines, a plurality of gates of first thin film transistors, a plurality of gates of second thin film transistors, and a plurality of gates of third thin film transistors;
the first insulating layer is arranged on the first metal layer;
the second metal layer is arranged on the first insulating layer, and forms a plurality of data lines, a plurality of second common electrode lines, a plurality of sources and drains of the first thin film transistors, a plurality of sources and drains of the second thin film transistors and a plurality of sources and drains of the third thin film transistors;
The second insulating layer is arranged on the second metal layer;
a transparent conductive layer forming a plurality of main pixel electrodes and a plurality of sub pixel electrodes, respectively; wherein,,
each of the first thin film transistor, the second thin film transistor, the third thin film transistor, the main pixel electrode and the sub pixel electrode form a sub pixel, and each of the two sub pixels forms a pixel region.
6. The array substrate of claim 5, wherein the first connection trace includes a first metal trace segment formed by the second metal layer, and a first via connection segment disposed between the transparent conductive layer and the first metal trace segment and penetrating the second insulating layer; or,
the first connecting wire comprises a first metal wire section formed by a second metal layer, a first transparent wire section formed by the transparent conductive layer, and a first via connecting section arranged between the first transparent wire section and the first metal wire section and penetrating through the second insulating layer.
7. The array substrate of claim 5, wherein the second connection trace includes a second metal trace segment formed by the second metal layer, and a second via connection segment disposed between the transparent conductive layer and the second metal trace segment and penetrating the second insulating layer; wherein,,
The second via connection section is arranged on a central line in the row direction of the secondary pixel electrode, and the second metal wire section is arranged across the primary pixel electrode.
8. The array substrate of claim 5, wherein the second connection trace includes a second metal trace segment formed from a second metal layer, a second transparent trace segment formed from the transparent conductive layer, and a second via connection segment disposed between the second transparent trace segment and the second metal trace segment and penetrating the second insulating layer; wherein,,
the second via hole connecting section is arranged in a device area where the second thin film transistor is located, and the second transparent wire section extends along the peripheral side of the main pixel electrode.
9. A display panel comprising a pixel structure according to any one of claims 1-4; or,
an array substrate according to any one of claims 5 to 8 and a color film substrate disposed opposite to the array substrate.
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