KR20040021893A - Driving apparatus of liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display and a method of driving the liquid crystal display are provided to improve texture of the liquid crystal display. CONSTITUTION: A gradation voltage generator(800) generates a plurality of gradation voltages. A data driver(500) selects a gradation voltage corresponding to a gradation signal from the plurality of gradation voltages and applies the selected gradation voltage to pixels as a data voltage. A signal controller(600) receives the gradation signal and a control input signal for controlling display of the gradation signal to control the data driver. Each of the gradation voltages has the first gradation voltage having the first voltage value and the second gradation voltage having the second voltage value different from the first voltage value. The gradation voltage generator selects one of the first and second gradation voltages and supplies the selected voltage to the data driver.

Description

Liquid crystal display and its driving method {DRIVING APPARATUS OF LIQUID CRYSTAL DISPLAY}

The present invention relates to a drive device for a liquid crystal display device.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

Among such liquid crystal display devices, liquid crystal display devices using twisted nematic (TN) liquid crystals have various advantages, but have limitations in extending their range to the monitor or TV area due to viewing angle problems. For this reason, a series of achievements have been shown through many studies such as the multi-domain method or the development of a new compensation film to improve the viewing angle of the TN mode. In particular, when the WV (wide viewing) film is applied, the characteristics are almost inferior to other wide viewing angle modes in the left and right directions. However, in the up and down direction, there remains a problem of gray level inversion (a phenomenon in which the brightness to be increased as the gray voltage is increased). In particular, the gray level inversion of the lower side is a very serious problem.

In particular, in a multi-domain liquid crystal display, a side gamma curve distortion phenomenon occurs in which a gamma curve at a front side and a gamma curve at a side do not coincide with each other, resulting in inferior visibility in left and right sides, even when compared to a TN mode liquid crystal display. For example, in the patterned vertically aligned (PVA) mode, which makes an incision by domain dividing means, the screen looks brighter and the color tends to shift toward white as the side faces. Occasionally, the picture appears clumped and disappears.

The technical problem to be achieved by the present invention is to implement a liquid crystal display device having excellent visibility by improving the image quality of the liquid crystal display device.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

FIG. 5A is a cross-sectional view taken along the line Va-Va ′ of FIG. 4.

FIG. 5B is a cross-sectional view of the TFT panel cut along the line Vb-Vb ′ of FIG. 4.

6 is a detailed circuit diagram of a gray voltage generator according to an exemplary embodiment of the present invention.

FIG. 7A illustrates a polar state of each subpixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

7B is a diagram illustrating a polar state of each subpixel of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

FIG. 8 shows the transmittance for each gray level when the data signal is applied in the one-dot inversion method and the two-dot inversion method according to the prior art, and when the data signal is applied in the two-dot inversion method according to an embodiment of the present invention. It is a graph.

An apparatus for driving a liquid crystal display device comprising a plurality of pixels each connected to a gate line and a data line and arranged in a matrix form for achieving the object of the present invention,

A gray voltage generator for generating a plurality of gray voltages;

A data driver which selects a gray voltage corresponding to the gray level signal from among the plurality of gray voltages and applies it to the pixel as a data voltage;

A signal controller configured to receive the control signal and the data driver to control the display of the gray signal;

Including;

Each of the gray voltages includes a second gray voltage having a second voltage value different from the first voltage value with respect to the same gray level as the first gray voltage having a first voltage value,

The gray voltage generator selects at least one of the first gray voltage and the second gray voltage according to a control signal from the signal controller and supplies it to the data driver.

Each of the first gray voltage and the second gray voltage may include a plurality of pairs of gray voltages having opposite polarities and the same magnitude.

The gray voltage generator may select only one of the first gray voltage and the second gray voltage when the polarity of the data voltage is changed every row and every column, or the polarity of the data voltage every two rows and every column. When is changed, it is preferable to alternately select the first gray voltage and the second gray voltage.

In this case, the gray voltage generator may select a relatively high gray voltage among the first gray voltage and the second gray voltage for the row in which the polarity is changed.

The gray voltage generator may include a plurality of resistor strings connected in series between a first voltage and a second voltage, and include a first voltage generator configured to generate the first gray voltage.

A second voltage generator including a plurality of resistor strings connected in series between the first voltage and the second voltage and generating the second gray voltage;

A voltage selector connected to the first and second voltage generators and selecting at least one of the first gray voltage and the second gray voltage according to a state of the control signal from the signal controller;

It may include. In this case, the voltage selector is preferably a multiplexer.

Each pixel includes a first subpixel and a second subpixel, wherein the first and second subpixels include a switching element connected to one of the gate lines and one of the data lines, a liquid crystal capacitor and a storage capacitor connected to the switching element. Each may include, and the first and second subpixels may be connected to another adjacent subpixel by a coupling capacitor.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a liquid crystal display device according to an embodiment of the present invention will be described.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a liquid crystal display according to an embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the present invention includes a liquid crystal panel assembly 300, a gate driver 400 and a data driver 500 connected thereto. The driving voltage generator 700 connected to the gate driver 400, the gray voltage generator 800 connected to the data driver 500, and a signal controller for controlling the driving voltage generator 700 are connected to the gate driver 400. It contains 600.

The liquid crystal panel assembly 300 includes a plurality of signal lines G ₁ -G _n , D ₁ -D _m , 131 and a plurality of pixels connected thereto in an equivalent circuit.

The signal lines G ₁ -G _n , D ₁ -D _m , 131 transmit a scanning signal or a gate signal, and the plurality of scanning signal lines or gate lines G ₁ -G extending in the row direction. _n ) and a data signal line or data line D ₁ -D _m which transmits an image signal or a data signal and extends in the column direction. The signal lines G ₁ -G _n , D ₁ -D _m are also applied with a common voltage (V _com ) or a reference voltage, between the gate lines G ₁ -G _n , and with the pixels. The storage electrode line 131 is disposed between the pixels.

As shown in FIG. 2, each pixel P _i , _j connected to the i-th gate line G _i and the j-th data line D _j (i = 1, 2, ..., n, j = 1, 2, ..., m) are two subpixels ( , ) And each subpixel ( , ) Is a switching element Q ₁ , Q ₂ connected to the signal lines G ₁ -G _n , D ₁ -D _m , respectively, and a liquid crystal capacitor C _LC1 , C _LC2 and a storage capacitor connected thereto. capacitors) (C _ST1 , C _ST2 ). The neighboring pixels up and down are connected to the coupling capacitor C _pp , and the upper sub-pixel (eg, pixel P _{i, j} ) of the pixel is connected. ) Is the lower subpixel of the upper pixel P _{i-1, j} ) And the coupling capacitor (C _pp ) ) Is the upper subpixel of the lower pixel P _{i + 1, j} ) And a coupling capacitor (C _pp ).

The switching elements Q ₁ , Q ₂ are three-terminal elements, the control terminal of which is connected to the gate lines G ₁ -G _n , the input terminal of which is connected to the data lines D ₁ -D _m , and the output terminals Is connected to one terminal of the liquid crystal capacitors C _{LC1 and} C _LC2 and the storage capacitors C _{ST1 and} C _ST2 .

The liquid crystal capacitors C _{LC1 and} C _LC2 have a holding capacitor C _{ST1 and} C _ST2 between the output terminals of the switching elements Q ₁ and Q ₂ and a common voltage V _com or a reference voltage. ) Is connected between the switching elements Q ₁ and Q ₂ and the storage electrode line 131.

Meanwhile, the liquid crystal panel assembly 300 may be schematically illustrated as shown in FIG. 3. For convenience, only one subpixel is shown in FIG. 3.

As shown in FIG. 3, the liquid crystal panel assembly 300 includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 therebetween. The lower panel 100 includes a gate line G _i , a data line D _j , a switching element Q1, and a storage capacitor C _ST1 . The liquid crystal capacitor C _LC1 has two terminals, a pixel electrode 190 of the lower panel 100 and a reference electrode 270 of the upper panel 200, and a liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric.

The pixel electrode 190 is connected to the switching element Q ₁ , and the reference electrode 270 is formed on the entire surface of the upper panel 200 and is connected to the common voltage V _com .

Herein, the liquid crystal molecules change their arrangement according to the change of the electric field generated by the pixel electrode 190 and the reference electrode 270, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

The pixel electrode 190 overlaps the storage electrode line 131 to form a storage capacitor C _ST1 , and is connected to a neighboring pixel electrode by a coupling capacitor C _PP . In addition, the pixel electrode 190 and / or the reference electrode 270 may have a plurality of cutouts or protrusions formed on the electrodes 190 and 270. In this case, the viewing angle may be improved by the fringe field.

FIG. 3 shows a MOS transistor as an example of a switching element Q ₁ , which is implemented as a thin film transistor using amorphous silicon or polysilicon as a channel layer in an actual process. .

Unlike in FIG. 3, the reference electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 are linearly formed.

On the other hand, in order to implement color display, each pixel should be able to display a color, which is provided with a color filter 230 of red, green, or blue in a region corresponding to each pixel electrode 190. It is possible by doing. The color filter 230 is mainly formed in the corresponding region of the upper panel 200 as shown in FIG. 2, but may be formed above or below the pixel electrode 190 of the lower panel 100.

Next, a detailed structure of the liquid crystal panel assembly 300 of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to the drawings.

4 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 5A is a cross-sectional view taken along the line Va-Va 'of FIG. 4, and FIG. 5B is along the line Vb-Vb' of FIG. 4. It is sectional drawing of the thin-film transistor display panel cut out.

First, the thin film transistor array panel will be described.

Gate wirings 121, 124, and 129 and storage electrode lines 131 are formed on a transparent insulating substrate 110 such as glass.

The gate lines 121, 124, and 129 include a gate line 121 extending in the horizontal direction, and a portion of the gate line 121 protrudes up and down to form the gate electrode 124. A gate pad 129 that receives a gate signal from the outside and transfers the gate signal to the gate line 121 is connected to an end of the gate line 121.

The storage electrode line 131 extends in parallel with the gate line 121 and may have branch lines although not illustrated. The potential of the common electrode (FIG. 2) facing the pixel electrodes 190a and 190b is usually applied to the storage electrode line 131.

The gate lines 121, 124, and 129 and the storage electrode line 131 are covered with the gate insulating layer 140, and semiconductor patterns 151, 156, 157, and 159 made of amorphous silicon are formed on the gate insulating layer 140. . Portions 154a and 154b of the semiconductor pattern 156 overlap the gate electrode 124 to form a channel portion of the thin film transistor. On the semiconductor patterns 151, 156, 157, and 159, ohmic contact layer patterns 161, 163, 165a, 165b, 167, and 169 made of amorphous silicon doped with N-type impurities such as phosphorus are formed.

The data lines 171, 173, 175a, 175b, and 179 and the coupling electrode 177 are formed on the contact layer patterns 161, 163, 165a, 165b, 167, and 169.

The data lines 171, 173, 175a, 175b, and 179 may include a data line 171 extending along the semiconductor pattern 161, a source electrode 173 connected thereto, and two drain electrodes 175a and 175b separated from the data line 171. Include. One end of the data line 171 is connected with a data pad 179 for receiving an image signal from the outside. The source electrode 173 protrudes from the data line 171 on the gate electrode 123, and the drain electrodes 175a and 175b are disposed on both sides of the source electrode 173, and one end of each of the source lines 173 is disposed at the gate line ( It extends up and down around 121).

The coupling electrode 177 partially overlaps the storage electrode line 131. Here, the ohmic contact layer patterns 161, 163, 165a, 165b, 167, and 169 may include the semiconductor patterns 151, 156, 157, and 159, the data lines 171, 173, 175a, 175b, and 179, and the coupling electrode 177. It is located only in this overlapping part. Data wirings 171, 173, 175a, 175b, and 179 and coupling electrodes 177, ohmic contact layer patterns 161, 163, 165a, 165b, 167, and 169, and semiconductor patterns 151, 156, 157, and 159. The silver has substantially the same planar shape except for the channel portions 154a and 154b.

The passivation layer 180 is formed on the data lines 171, 173, 175a, 175b, and 179 and the coupling electrode 177. In this case, the passivation layer 180 has contact holes 181 and 182 exposing one end of the two drain electrodes 175a and 175b, and a contact hole 183 exposing one end of the coupling electrode 177. . The passivation layer 180 also has a contact hole 185 exposing the data pad 179, and a contact hole 184 exposing the gate pad 95 together with the gate insulating layer 140.

Two pixel electrodes 190a and 190b connected to the drain electrodes 175a and 175b are formed on the passivation layer 180 through the contact holes 181 and 182, respectively. The lower pixel electrode 190a is connected to the coupling electrode 177 through the contact hole 183, and the upper pixel electrode 190b overlaps the coupling electrode 177. That is, the lower pixel electrode 190a of the upper pixel and the upper pixel electrode 190b of the lower pixel form a capacitive capacitor through the coupling electrode 177. The pixel electrodes 190a and 190b are made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Meanwhile, the lower pixel electrode 190a has one horizontal cutout 191 extending in the horizontal direction. The number of horizontal cutouts 191 may be plural, and a vertical cutout may be formed in the pixel electrode 190b. In order to eliminate the gray level reversal phenomenon, the ratio of the lower pixel electrode 190a to the entire pixel electrode area is preferably 10% to 50%, and particularly preferably 20 to 30%.

In addition, the auxiliary gate pad 95 and the auxiliary data pad 97, which are connected to the gate pad 129 and the data pad 179, respectively, are formed on the passivation layer 180 through the contact holes 184 and 185. Here, the auxiliary gate and data pads 95 and 97 are for protecting the gate and data pads 129 and 179, but are not essential.

An alignment layer 11 is formed on the entire surface of the thin film transistor array panel 100 except for the vicinity of the auxiliary gate pad and the auxiliary data pads 95 and 97.

Next, the color filter display panel will be described with reference to FIGS. 4 and 5A.

The black matrix 220 is formed on a transparent insulating substrate 210 such as glass, and the red, green, and blue color filters 230 are repeatedly formed in each pixel region defined by the black matrix 220. . An overcoat layer 250 is formed on the color filter 230, and a reference electrode 270 made of a transparent conductive material such as ITO is formed on the overcoat layer 250.

Reference electrode 270 has three linear cutouts 271, 272, 273. The cutout 271 extending in the vertical direction divides the upper pixel electrode 190b from side to side and divides it into two left and right small regions, and the two cutouts 272 and 273 extending in the horizontal direction are horizontal. Located at both sides of the cutout 191, the lower pixel electrode 190a is positioned up and down by four. At this time, each of the small regions partitioned by the cutout 191 and the cutouts 271, 272, and 273 has a substantially quadrangular shape, and two long sides thereof are formed on the gate line 121 and the data line 171. Parallel to

Positions of the cutouts 191, 271, 272, and 273 of the pixel electrodes 190a and 190b and the reference electrode 270 may be changed upside down. That is, the horizontal cutouts 191, 272, and 273 may be located in the upper pixel 190a, and the vertical cutout 271 may be located in the lower pixel 190b.

An alignment layer 21 is formed on the reference electrode 270 and the entire exposed cutouts 271, 272, and 273.

Polarizers 12 and 22 are attached to the outer sides of the two substrates 110 and 210, respectively. At this time, the polarization axes of these polarizing plates 12 and 22 are parallel to the gate line 121 or the data line 171, and are arranged to be orthogonal to each other.

A liquid crystal material is injected between the thin film transistor substrate 100 and the color filter substrate 200 having such a structure to form the liquid crystal layer 3.

Meanwhile, in the present embodiment, the coupling electrode 177 is placed on the same layer as the data lines 171, 173, 175a, 175b, and 179. Alternatively, the coupling electrode 177 may be placed on the same layer as the gate lines 121, 124, and 129. . In this case, care should be taken so that the storage electrode line 131 does not come into contact with the coupling electrode 177.

Returning to Figure 1, the driving voltage generator 700 includes a switching element (Q _1, Q _2), the gate-off voltage turn turning off the gate-on voltage (V _on) and switching elements (Q _1, Q ₂₎ to turn on the (V _off) and the like and generates a reference voltage (V _com) is applied to the reference electrode (270).

The gray voltage generator 800 generates a plurality of gray voltages related to the luminance of the liquid crystal display.

The gate driver 400 may also be referred to as a scan driver. The gate driver 400 may be connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to provide a gate-on voltage V _on from the driving voltage generator 700. And a gate signal composed of a combination of the gate off voltage V _off are applied to the gate lines G ₁ -G _n .

The data driver 500 may also be referred to as a source driver. The data driver 500 may be connected to the data lines D ₁ -D _m of the display panel 300 to select a gray voltage from the gray voltage generator 800 to select data as a data signal. Applies to lines D ₁ -D _m .

The signal controller 600 generates control signals for controlling operations of the gate driver 400, the data driver 500, the driving voltage generator 700, the gray voltage generator 800, and the like, respectively. ), The data driver 500, the driving voltage generator 700, and the gray voltage generator 800.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 controls an RGB gray level signal R, G, B and its display from an external graphic controller (not shown), for example, vertical synchronization. A vertical synchronizing signal (V _sync ), a horizontal synchronizing signal (H _sync ), a main clock (CLK), and a data enable signal (DE) are provided. The signal controller 600 generates a gate control signal, a data control signal, and a voltage selection control signal VSC based on the control input signal, and generates the gray level signals R, G, and B from the liquid crystal panel 300. After appropriately processing according to the operating conditions of the control signal, the gate control signal is sent to the gate driver 400 and the driving voltage generator 700, and the data control signal and the processed gray level signals R ', G', B 'are the data driver. In step 500, the voltage selection control signal VSC is sent to the gray voltage generator 800.

The gate control signal includes a vertical synchronization start signal (STV) for indicating the start of output of the gate on pulse (high period of the gate signal), and a gate clock signal for controlling the output timing of the gate on pulse. CPV) and a gate on enable signal (OE) for limiting the width of the gate on pulse. Among them, the gate-on enable signal OE and the gate clock signal CPV are supplied to the driving voltage generator 700. The data control signal is a horizontal synchronization start signal (STH) indicating the start of input of the gray scale signal and a load signal (load signal, LOAD or TP) for applying a corresponding data voltage to the data lines D ₁ -D _m . ), An inversion control signal RVS for inverting the polarity of the data voltage, a data clock signal HCLK, and the like.

First, the gray voltage generator 800 supplies a gray voltage having a voltage value determined according to the voltage selection control signal VSC to the data driver 500.

The gate driver 400 sequentially applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal from the signal controller 600, thereby applying the gate-on voltage V _on to the gate lines G ₁ -G _n . Turn on the two connected switching elements Q ₁ , Q ₂ . At the same time, the data driver 500 controls the gray level signals R ', G', and B 'of the pixels including the turned-on switching elements Q ₁ and Q ₂ according to a data control signal from the signal controller 600. The analog gray voltage from the gray voltage generator 800 corresponding to the data signal is supplied as a data signal to the data lines D ₁ -D _m . The data signals supplied to the data lines D ₁ -D _m are applied to the corresponding pixels through the turned-on switching elements Q ₁ and Q ₂ . In this way, the gate-on voltage V _on is sequentially applied to all the gate lines G ₁ -G _n during one frame to apply the data signal to all the pixels. When one frame is over and the inversion control signal RVS is supplied to the driving voltage generator 700 and the data driver 500, the polarities of all data signals of the next frame are changed. At this time, the polarity of the data signal flowing through one data line is changed even within one frame.

Next, a method of applying a data signal to the liquid crystal panel assembly according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7A and 7B.

FIG. 7A illustrates a polar state of each subpixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 7B illustrates a polar state of each subpixel of a liquid crystal panel assembly according to another exemplary embodiment of the present invention. to be. Here, the indications "+" and "-" indicate the polarity of the data signal with respect to the reference voltage V _com .

As shown in Figs. 7A and 7B, in the embodiment of the present invention, the polarity of the data signal applied to the data line is inverted every data line. On the other hand, in the embodiment of Fig. 7A, the polarity of the data signal is inverted every row, while in the embodiment of Fig. 7B, it is inverted every two rows.

When the gate-on voltage Von is applied to the i-th gate line G _i , the voltage of the data signal d _j applied to the j-th data line D _j is _converted into the data voltage ( Let's say

In FIG. 7A The polarity of is (+), The polarity of (x, y is an integer) is (+) if | x + y | is even and (-) if | x + y | is odd. In the next frame of Fig. 7A, the polarities are all reversed. therefore Polarity of 이면 x + y | Is the same as the polarity of and if | x + y | is odd It can be seen that the polarity of the opposite.

In this way, when the data signal is applied, the polarity of a certain pixel _{Pi + x} and _{Pj + y} is the same polarity as the pixels _Pi and _j when | x + y is even and | x + y | Is an odd polarity. For example, the polarities of the pixels (P _{i, j)} and pixels adjacent up and down (P _{i-1, j)} and the pixel (P _{i + 1, j)} in Figure 7a is, | -1 | = | +1 | Since = 1, the polarity of the pixels _Pi and _j is opposite. Therefore, the polarity of the pair of subpixels connected by the coupling capacitor C _pp is reversed.

However, in the case of FIG. 7B, the polarity of the pair of subpixels connected by the coupling capacitor C _pp may be opposite or the same.

On the other hand, the subpixel ( , Voltages applied to the liquid crystal capacitors C _LC1 and C _LC2 ) ), V ( ), The following relation holds.

) =

In Equations 1 and 2, C _LC2 and C _ST2 represent lower subpixels ( Is the capacitance of the liquid crystal capacitor and the holding capacitor, C _pp is the capacitance of the coupled capacitor, Silver subpixel ( ) Means the voltage of the previous frame that was applied to For convenience, the wiring resistance of the data lines D ₁ -D _m is ignored, and the common voltage V _com is assumed to be zero.

In equation (2) Wow If is the same polarity, and Is the opposite polarity, Becomes In particular, in the case where the pixels P _{i + 1} , _j display the same gray level as the pixels P _i , _j and are still images, Equation 2 can be summarized as follows.

,

＞ 1

to be.

Contrary, Wow If is the opposite polarity,

Becomes In the case where the pixels P _{i + 1, j} display the same gray level as the pixels P _{i, j} and are still images

,

<1

Becomes

According to Equations 3 and 5, if the subpixels adjacent to each other have the same polarity, the lower subpixel ( At the top subpixel ( If a voltage higher than) is applied, and vice versa, the lower subpixel ( At the top subpixel ( A voltage lower than) is applied.

As a result, when the polarities of the data signals applied to two adjacent pixel rows are the same, the pixel voltage applied to the lower subpixel of the upper pixel is increased, and conversely, when the polarities are different, the pixel voltage is decreased. Therefore, in the latter case, it is necessary to apply a data signal having a relatively high voltage value. In particular, in the case of FIG. 7A, it is preferable to give a relatively high voltage value to all pixel rows, and in the case of 7b, one row is relatively high and the next row is relatively low. In addition, in the case of FIG. 7B, since the pixel voltage values may be greatly different between neighboring pixels having the same gray scale, different voltage values may be set in consideration of the voltage rising and falling effects due to the coupling capacitor C _pp even in the same gray scale. It needs to be authorized.

To this end, it is necessary to generate two or more gray voltages having different voltage values for the same gray level, and select and export an appropriate value according to the driving method. This will be described in detail with reference to FIG. 6.

6 is a detailed circuit diagram of a gray voltage generator according to an exemplary embodiment of the present invention.

As shown in Fig. 6, the gradation voltage generator of this embodiment is connected to four voltage generators 11-14 and the four voltage generators 11-14, and voltage selection control from the signal controller 600 is performed. The multiplexer 20 receives a signal VSC and supplies a gray voltage 1G-18G to the data driver 500.

The voltage generator 11-14 is different from the first voltage generators 11 and 13 with respect to the same gray level as the first voltage generators 11 and 13 that generate the plurality of gray voltages V1a to V18a. The second voltage generators 12 and 14 may generate a plurality of gray voltages V1b to V18b having voltage values. In consideration of the difference from the reference voltage V _com , each of the voltages V1a to V18a generated by the first voltage generators 11 and 13 is the voltage V1b generated by the second voltage generators 12 and 14. ~ V18b) All higher or lower than each. In the present embodiment, for convenience, it is assumed that the voltages V1a to V18a are higher than the voltages V1b to V18b. In other words

to be. Here, the gray scale voltages of the positive and negative polarities mean polarities based on the common voltage V _com .

One of the first voltage generators 11 and 13 (11) generates positive gray voltages (V1a, V2a, ..., V8a, V9a), the other 13 is a negative gray voltage (V10a) , V11a, ..., V17a, and V18a, and the second voltage generators 12 and 14 also output positive gray voltages V1b, V2b, ..., V8b, and V9b. ) And a voltage generator 14 for outputting negative gray voltages (V10b, V11b, ..., V17b, V18b).

The two voltage generators 11 and 12 for generating a positive gray scale voltage each include a series of resistors connected in series between the power supply Vdd and the reference voltage V _com , and the The voltages V1a, V1b, V2a, V2b, ..., V9a, V9b become output voltages. These gray voltages (V1a, V1b, V2a, V2b, ..., V9a, V9b) include voltages corresponding to the lowest grayscale (black grayscale) and the highest grayscale (white grayscale). In the case of the normally white system, the voltage value corresponding to the black gradation is the largest and the voltage value corresponding to the white gradation is the smallest.

The remaining two voltage generators 13 and 14, which generate the negative gray scale voltage, each have a series of resistors connected in series between the reference voltage V _com and ground, which are also contacts between the resistors. The voltages V10a, V10b, V11a, V11b, ..., V18a, V18b become the output voltages.

Each resistance value of the first voltage generators 11 and 13 is smaller than each resistance value of the second voltage generators 12 and 14, and is a value of the resistor included in the first voltage generators 11 and 13. Are all the same, and the values of the resistors included in the second voltage generators 12 and 14 may all be the same.

In the present embodiment, a resistor string consisting of one stage is shown, but the resistors may have a hierarchical structure connected in stages, and the hierarchical structure may be repeated until an appropriate number of gradation voltages are obtained. In addition, the resistance number of each stage may vary as needed.

The multiplexer 20 emits the voltages V1a, V2a, ...., V17a, and V18a generated by the first voltage generators 11 and 13 according to the value of the voltage selection control signal VSC, And alternating voltages V1a-V18a and V1b-V18b generated by the second voltage generator 11-14.

An operation of the gray voltage generator 570 according to the exemplary embodiment of the present invention having the above structure will be described.

First, the signal controller 600 varies the value of the voltage selection control signal VSC according to an inversion method of inverting the polarity of the data signal applied to the data lines D ₁ -D _m , and thus the gray voltage generator 800. It is supplied to the multiplexer 20 of the. For example, if the 1-dot inversion method is selected, which inverts every data line and every column, the voltage selection control signal VSC becomes a signal of a high level " high " state, but inverts every data line but inverts every row. In the case of selecting the 2-dot inversion method of inverting the polarity every time, the high level "high" and the low level "low" states are alternately shown. In this case, the voltage selection control signal VSC serves as a selection signal of the multiplexer 20.

First, the case where the polarity inversion method of the data signal is selected as the one-dot inversion method will be described.

As described above, in the case of the 1-dot inversion method, since the subpixels of adjacent pixel rows have opposite polarities and the pixel voltage applied to the upper subpixel of the lower pixel is lowered, a relatively high voltage must be applied. .

Therefore, when the voltage selection control signal VSC is in the "high" state, the multiplexer 20 selects the voltages V1a, V2a, ...., V17a and V18a output from the first voltage generators 11 and 13. The data driver 500 supplies the data driver 500 with the gray voltage 1G-18G through the output terminal.

However, in the 2-dot inversion method, since the polarity of the data signal is inverted every two pixel rows, a relatively high voltage and a relatively low voltage must be alternately applied to the data driver 600.

Therefore, the voltage selection control signal VSC is set to the "high" state for the pixel row whose polarity is changed to select relatively high voltages V1a to V18a. However, for the pixel row whose polarity is the same as the previous row, the voltage selection control signal VSC is set to the "low" state, so that the relatively low voltages V1b, V2b, ..., V17b, and V18b are selected and the gray scale voltage (1G) is selected. -118), the operation of supplying to the data driver 500 is repeated.

As described above, according to the method of applying the data signal, a value of the gray voltage 1G-18G applied to the data driver 500 may be selected and applied to the same gray level.

FIG. 8 shows the transmittance for each grayscale when the data signal is applied in the one-dot inversion method and the two-dot inversion method according to the related art, and when the data signal is applied in the two-dot inversion method according to an embodiment of the present invention. It is a graph.

In FIG. 8, graphs A and B respectively show data in a 2-dot inversion method and a 1-dot inversion method when the gray voltage is applied to the data driver 500 according to the related art, that is, when only one gray voltage is output to one gray level. When a signal is applied, the transmittance of each gray scale is shown. In contrast, graph C shows the transmittance for each gray level when the gray voltage generator 800 according to the present embodiment is applied and the data signal is applied in a 2-dot inversion scheme.

As can be seen from the graph, when the data signal is applied in the 2-dot inversion method by applying the gray scale voltage generator 800, a curve similar to that of the 1-dot inversion method is shown, so that the luminance between the 1-dot inversion method and the 2-dot inversion method is reduced. It can be seen that the difference is compensated.

As such, in a liquid crystal display in which pixels are divided into two subpixels, two switching elements and two liquid crystal capacitors are formed per pixel, and neighboring pixels are combined using a coupling capacitor, neighboring subpixels. When the polarities are the same, a relatively low gray voltage is applied to the data driver, and when the neighboring subpixels are different, a relatively large gray voltage is applied to the data driver. Therefore, the luminance difference is compensated for by making the pixel voltage uniformly as a whole, thereby improving the image quality of the liquid crystal display and improving the visibility.

In addition, the luminance difference generated when the data signal is applied in the one-dot inversion method and the two-dot inversion method can be compensated for.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (8)

A device for driving a liquid crystal display device comprising a plurality of pixels connected to a gate line and a data line, respectively, and arranged in a matrix form. A gray voltage generator for generating a plurality of gray voltages; A data driver which selects a gray voltage corresponding to the gray level signal from among the plurality of gray voltages and applies it to the pixel as a data voltage; A signal controller configured to receive the control signal and the data driver to control the display of the gray signal; Including; Each of the gray voltages includes a second gray voltage having a second voltage value different from the first voltage value with respect to the same gray level as the first gray voltage having a first voltage value, The gray voltage generator selects at least one of the first gray voltage and the second gray voltage according to a control signal from the signal controller to supply the data driver to the data driver. Driving device for liquid crystal display device. In claim 1, And a plurality of pairs of gray voltages of opposite polarity and the same magnitude to each of the first gray voltage and the second gray voltage. In claim 2, And the gray level voltage generator selects only one of the first gray voltage and the second gray voltage when the polarity of the data voltage is changed every row and every column. The method of claim 2 or 3, And the gray voltage generator alternately selects the first gray voltage and the second gray voltage when the data voltage is changed in two rows and every column. In claim 4, And the gray voltage generator selects a relatively high gray voltage among the first gray voltage and the second gray voltage for the row of which the polarity is changed. In claim 1, The gray voltage generator includes a plurality of resistor strings connected in series between a first voltage and a second voltage, and includes a first voltage generator configured to generate the first gray voltage. A second voltage generator including a plurality of resistor strings connected in series between the first voltage and the second voltage and generating the second gray voltage; A voltage selector connected to the first and second voltage generators and selecting at least one of the first gray voltage and the second gray voltage according to a state of the control signal from the signal controller; Driving device for a liquid crystal display comprising a. In claim 6, And the voltage selector is a multiplexer. In claim 1, Each pixel includes a first subpixel and a second subpixel. The first and second subpixels each include a switching element connected to one of the gate lines and one of the data lines, a liquid crystal capacitor and a storage capacitor connected to the switching element, respectively. The first and second subpixels are connected to other adjacent subpixels by a coupling capacitor. Driving device for liquid crystal display device.