KR101046929B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device. The liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal layer including liquid crystal molecules interposed between first and second substrates facing each other, the first and second substrates, and formed on the first substrate. A gate line transferring a gate signal, first and second data lines formed on the first substrate and transferring first and second data voltages having different polarities, respectively, and connected to the gate line and the first data line; A first switching element, a second switching element connected to the gate line and the second data line, and first and second pixel electrodes connected to the first and second switching elements, respectively, and separated from each other. In addition, the liquid crystal layer has a positive dielectric anisotropy.

EOC, Ultra High Speed VA, DP, IPS, DFS, PLS, PVA, SPVA, Data Drive

Description

Liquid crystal display {LIQUID CRSYTAL DISPLAY}

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the flat panel display devices most widely used. The liquid crystal display includes two display panels on which field generating electrodes, such as a pixel electrode and a common electrode, are formed, and a liquid crystal layer interposed therebetween. Applying to generate an electric field in the liquid crystal layer through which to determine the orientation of the liquid crystal molecules of the liquid crystal layer and to control the polarization of the incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode.

The liquid crystal display receives an input image signal from an external graphic controller, and the input image signal contains luminance information of each pixel, and each luminance has a predetermined number. Each pixel receives a data voltage corresponding to desired luminance information. The data voltage applied to the pixel is represented by the pixel voltage according to the difference of the common voltage, and each pixel displays the luminance represented by the gray level of the image signal according to the pixel voltage. In this case, the pixel voltage range that the liquid crystal display device can use is determined by the driving unit.

Meanwhile, the driving unit of the liquid crystal display device is directly mounted on the display panel in the form of a plurality of integrated circuit chips or mounted on a flexible circuit film and attached to the display panel. The integrated circuit chip occupies a high ratio in the manufacturing cost of the liquid crystal display device. .

In addition, as the number of wirings such as gate lines or data lines formed in the liquid crystal panel assembly increases, the aperture ratio of the display device is significantly reduced.

The technical problem to be achieved by the present invention is to increase the transmittance by increasing the pixel voltage range that can be used by the liquid crystal display without replacing the driver, to reduce the manufacturing cost of the driver, and to improve the aperture ratio of the display panel.

Another technical problem to be solved by the present invention is to secure a high contrast ratio and a wide viewing angle of the liquid crystal display at the same time, and to speed up the response speed of the liquid crystal molecules.

Another technical problem to be achieved by the present invention is to improve display characteristics of a liquid crystal display device regardless of the influence of pressure from the outside.

The liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal layer including liquid crystal molecules interposed between first and second substrates facing each other, the first and second substrates, and formed on the first substrate. A gate line transferring a gate signal, first and second data lines formed on the first substrate and transferring first and second data voltages having different polarities, respectively, and connected to the gate line and the first data line; A first switching element, a second switching element connected to the gate line and the second data line, and first and second pixel electrodes connected to the first and second switching elements, respectively, and separated from each other. In addition, the liquid crystal layer has a positive dielectric anisotropy.

The liquid crystal layer may be vertically aligned.

The liquid crystal layer may be horizontally aligned.

A third switching element formed on the first substrate and connected to the third and fourth data lines, the gate line, and the third data line, respectively, to transfer third and fourth data voltages having different polarities, respectively; A fourth switching element connected to a line and the fourth data line, a third pixel electrode connected to the third switching element, and a fourth separated from the third pixel electrode and connected to the fourth switching element It may further include a pixel electrode.

A third data element formed on the first substrate and connected to the gate line and the third data line, the third switching element connected to the third data line, the gate line, and the second data line to transfer a third data voltage; A fourth switching electrode, a third pixel electrode connected to the third switching element, and a fourth pixel electrode separated from the third pixel electrode and connected to the fourth switching element, the second data Polarities of the voltage and the third data voltage may be different from each other.

Polarities of the first and second data voltages may be changed periodically for each frame.

The first and second pixel electrodes may be formed on the same layer.

The first and second pixel electrodes may be formed on different layers.

The display device may further include a common electrode formed on the first substrate and receiving a common voltage.

The display device may further include a common electrode formed on the second substrate and receiving a common voltage.

The first and second pixel electrodes may include a plurality of branch electrodes, and the branch electrodes of the first pixel electrode and the branch electrodes of the second pixel electrode may be alternately disposed.

The distance between the branch electrodes of the neighboring first pixel electrode and the branch electrodes of the second pixel electrode may be the same according to the position.

The distance between the branch electrodes of the neighboring first pixel electrodes and the branch electrodes of the second pixel electrodes may vary depending on the position.

The branch electrodes of the first and second pixel electrodes may be bent at least once.

The branch electrodes of the first and second pixel electrodes may be formed obliquely with respect to the gate line.

The first and second data lines may be bent one or more times.

A storage electrode line formed on the first substrate, wherein the first switching element includes a first drain electrode connected to the first pixel electrode, and the second switching element includes the second pixel electrode. And a second drain electrode connected to each other, wherein at least one of the first pixel electrode, the second pixel electrode, the first drain electrode, and the second drain electrode may overlap the storage electrode line.

An electrode connected to the first pixel electrode or the first pixel electrode may overlap the second pixel electrode.

According to another exemplary embodiment of the present invention, a liquid crystal display device is disposed between first and second substrates facing each other, the first and second substrates, and includes a liquid crystal layer including liquid crystal molecules, and is formed on the first substrate. A gate line transferring a gate signal, first and second data lines formed on the first substrate and connected to the first and second data voltages and connected to the gate line and the first data line; And third and fourth switching elements connected to a second switching element, the gate line, and the second data line, and first and second connections to the first, second, third and fourth switching elements, respectively. And second, third and fourth pixel electrodes, wherein the liquid crystal layer has positive dielectric anisotropy.

Polarities of the first data voltage and the second data voltage may be opposite to each other.

The liquid crystal layer may be vertically or horizontally aligned.

Fifth and sixth switching elements formed on the first substrate and connected to the third and fourth data lines, the gate lines, and the third data lines, respectively, to transfer different third and fourth data voltages; Seventh and eighth switching elements connected to the first gate line and the fourth data line, and fifth, sixth, seventh and seventh and eighth switching elements connected to the fifth, sixth, seventh and eighth switching elements, respectively. It may further include an eighth pixel electrode.

Fifth and sixth switching elements formed on the first substrate and connected to the third and third data lines that transfer a third data voltage, the gate lines and the second data lines, and the gate lines and the third data lines. And fifth, sixth, seventh, and eighth pixel electrodes connected to the seventh and eighth switching elements, and the fifth, sixth, seventh, and eighth switching elements, respectively; The data voltage and the third data voltage may be different from each other.

The first, second, third and fourth switching elements may include first, second, third and fourth gate electrodes and first, second, third and fourth drain electrodes, respectively. The second, third, and fourth drain electrodes are connected to the first, second, third, and fourth pixel electrodes, respectively, and have a first overlapping area where the first gate electrode and the first drain electrode overlap. An area, an area where the second gate electrode and the second drain electrode overlap, a second area, an area where the third gate electrode and the third drain electrode overlap, a third area, and the fourth gate electrode and the When the area where the fourth drain electrode overlaps is referred to as a fourth area, at least one of the first to fourth areas may be different from the rest.

The first area may be larger than the third area, or the fourth area may be larger than the third area.

Each of the first to fourth pixel electrodes includes a plurality of branch electrodes, the branch electrodes of the first pixel electrode and the branch electrodes of the third pixel electrode are alternately disposed, and the branch electrodes of the second pixel electrode. And the branch electrodes of the fourth pixel electrode may be alternately arranged.

The branch electrodes of the first to fourth pixel electrodes may be formed obliquely on the gate line.

The display device may further include a storage electrode line formed on the first substrate.

According to another exemplary embodiment of the present invention, a liquid crystal display device is disposed between first and second substrates facing each other, the first and second substrates, and includes a liquid crystal layer including liquid crystal molecules, and is formed on the first substrate. A gate line transferring a gate signal, and first, second, third and fourth data lines formed on the first substrate and transferring different first, second, third and fourth data voltages, respectively; A first switching element connected to a gate line and the first data line, a second switching element connected to the gate line and the second data line, a third switching element connected to the gate line and the third data line, A fourth switching element connected to the gate line and the fourth data line, and first, second, third and fourth subpixels connected to the first, second, third and fourth switching elements, respectively. Including electrode , The first to fourth sub-pixel electrodes receive different voltage is applied to the image information obtained from one of the liquid crystal layer has a positive dielectric anisotropy.

Polarities of the first data voltage and the second data voltage may be opposite to each other, and polarities of the third data voltage and the fourth data voltage may be opposite to each other.

The liquid crystal layer may be vertically or horizontally aligned.

The display device may further include a storage electrode line formed on the first substrate.

According to another exemplary embodiment of the present invention, a liquid crystal display device includes a first and a second substrate facing each other, a liquid crystal layer including liquid crystal molecules interposed between the first and second substrates, and formed on the first substrate. First and second gate lines, first and second data lines formed on the first substrate and transferring different first and second data voltages, respectively, and connected to the first gate line and the first data line. A first switching element, a second switching element connected to the first gate line and the second data line, a third switching element connected to the second gate line and the first data line, and a second gate line; A fourth switching element connected to the second data line, and first, second, third and fourth subpixel electrodes connected to the first, second, third and fourth switching elements, respectively; , The first to the first The four subpixel electrodes receive different voltages obtained from one image information, and the liquid crystal layer has positive dielectric anisotropy.

Polarities of the first data voltage and the second data voltage may be opposite to each other.

The liquid crystal layer may be vertically or horizontally aligned.

The display device may further include a storage electrode line formed on the first substrate.

A liquid crystal display according to another exemplary embodiment of the present invention includes a pixel including first and second subpixels and a coupling capacitor, a gate line formed on a substrate and a gate line transferring a gate signal, and formed on the substrate and different from each other. A first switching element including the first and second data lines transferring first and second data voltages, wherein the first subpixel is connected to the gate line and the first data line; A second switching element connected to two data lines, and a first liquid crystal capacitor connected to the first and second switching elements, wherein the coupling capacitor is connected to the first switching element, The pixel includes the second switching element, and a second liquid crystal capacitor connected to the coupling capacitor and the second switching element, wherein the first and second liquid crystals The capacitor includes a liquid crystal layer having positive dielectric anisotropy.

Polarities of the first data voltage and the second data voltage may be opposite to each other.

The liquid crystal layer may be vertically or horizontally aligned.

The display device may further include a storage electrode line formed on the first substrate.

According to another exemplary embodiment of the present invention, a liquid crystal display device includes a plurality of pixels including first and second subpixels and a boost unit, first and second gate lines formed on a substrate, and transmitting gate signals, and the substrate. First and second data lines formed thereon and transferring first and second data voltages different from each other, wherein the first subpixel is connected to the first gate line and the first data line; An element, a second switching element connected to the first gate line and the second data line, and a first liquid crystal capacitor connected to the first and second switching elements, wherein the second subpixel includes the first subpixel. A third switching element connected to a first gate line and the first data line, the second switching element, and a second liquid crystal capacitor connected to the second and third switching elements, The boost unit is controlled by a boost capacitor connected to the first switching element, a gate signal of the first gate line, and a fourth switching element connected between the boost capacitor and a common voltage, and a gate signal of the second gate line. A fifth switching element controlled by the boost capacitor and connected between the boost capacitor and the second liquid crystal capacitor, wherein the second gate line receives a gate-on voltage later than the first gate line, The two liquid crystal capacitors include a liquid crystal layer having positive dielectric anisotropy.

Polarities of the first data voltage and the second data voltage may be opposite to each other.

The liquid crystal layer may be vertically or horizontally aligned.

When two neighboring pixels are referred to as a first pixel and a second pixel, the second data voltage transmitted by the second data line of the first pixel and the second data line transmitted by the second data line of the second pixel are transferred. The data voltage may be the same.

The first subpixel further includes a first storage capacitor connected to the first switching element, and a second storage capacitor connected to the second switching element, wherein the second subpixel is connected to the third switching element. It may further include a third holding capacitor and the second holding capacitor is connected.

The first subpixel further includes a first storage capacitor connected to the first and second switching elements, and the second subpixel includes a second storage capacitor connected to the second and third switching elements. It may further include.

According to another exemplary embodiment of the present invention, a liquid crystal display device is disposed between first and second substrates facing each other, the first and second substrates, and includes a liquid crystal layer including liquid crystal molecules, and is formed on the first substrate. A gate line transferring a gate signal, first, second and third data lines formed on the first substrate and transferring first, second and third data voltages, respectively; A first switching element connected to the second switching element connected to the gate line and the second data line, a third switching element connected to the gate line and the second data line, the gate line and the third data And a fourth switching element connected to a line, and first, second, third and fourth pixel electrodes connected to the first, second, third and fourth switching elements, respectively.

The liquid crystal layer may have positive dielectric anisotropy.

The liquid crystal layer may be vertically or horizontally aligned.

The second data voltage may vary between the first level and the second level at regular intervals.

The first level may be the highest voltage that the liquid crystal display may use, and the second level may be the lowest voltage that the liquid crystal display may use.

The period may be one frame.

The first to third data lines may be formed on the same layer.

The second data line may be formed on the same layer as the gate line.

The display device may further include a storage electrode line formed on the first substrate.

The first and second pixel electrodes may include a plurality of branch electrodes, and the branch electrodes of the first pixel electrode and the branch electrodes of the second pixel electrode may be alternately disposed.

The distance between the branch electrodes of the neighboring first pixel electrodes and the branch electrodes of the second pixel electrodes may vary depending on the position.

According to another exemplary embodiment, a liquid crystal display device includes a pixel including a first subpixel and a second subpixel, a gate line formed on a substrate, and first, second, and third data formed on the substrate. And a first switching element connected to the gate line and the first data line, a second switching element connected to the gate line and the second data line, and the first and second subpixels. And a liquid crystal capacitor connected to a second switching element, wherein the second subpixel is connected to the gate line and the second data line, and is connected to the third switching element, the gate line, and the third data line. And a liquid crystal capacitor connected to the third and fourth switching elements, wherein the first subpixel and the second subpixel are obtained from one image information. Jin receive each other is applied to the other data voltage.

The liquid crystal capacitor may have positive dielectric anisotropy.

The liquid crystal layer may be vertically or horizontally aligned.

The voltage applied to the second data line may change the first level and the second level at regular intervals.

The first to third data lines may be formed on the same layer.

The second data line may be formed on the same layer as the gate line.

The display device may further include a storage electrode line formed on the substrate.

A liquid crystal display according to another exemplary embodiment of the present invention includes a plurality of pixels arranged in a matrix form and including a first subpixel and a second subpixel, a plurality of first and second gate lines formed on a substrate, and And a plurality of first and second data lines formed on the substrate, wherein the first subpixel comprises: a first switching element, the first gate line, and the first gate line; And a second switching element connected to the second data line, and a first liquid crystal capacitor connected to the first and second switching elements, wherein the second subpixel includes the second gate line and the first data. A third switching element connected to a line, a fourth switching element connected to the second gate line and the second data line, and a second liquid crystal capacitor connected to the third and fourth switching elements The it included, and the first sub-pixel and the second sub-pixel is supplied with a different data voltages obtained from one image information.

The liquid crystal capacitor may include a liquid crystal layer having positive dielectric anisotropy.

The liquid crystal layer may be vertically or horizontally aligned.

The voltage applied to the second data line may change the first level and the second level at regular intervals.

The second data line may be formed on the same layer as the first and second gate lines.

And a plurality of third data lines formed on the substrate, wherein two neighboring pixels of the plurality of pixels are a first pixel and a second pixel, wherein the first subpixel of the second pixel is the first pixel. A fifth switching element connected to a gate line and the third data line, a sixth switching element connected to the first gate line and the second data line, and a third switching element connected to the fifth and sixth switching elements A second subpixel of the second pixel, wherein the second subpixel of the second pixel is connected to the second gate line and the third data line, and is connected to the second gate line and the second data line. An eighth switching element, and a fourth liquid crystal capacitor connected to the seventh and eighth switching elements, wherein the first and second subpixels of the second pixel are different from each other obtained from one image information. Data voltage may be applied.

The display device may further include a storage electrode line formed on the substrate.

A liquid crystal display according to another exemplary embodiment of the present invention includes a coupling capacitor, a first subpixel, and a second subpixel, and each of the first and second pixels adjacent to each other, a gate line formed on a substrate, and the substrate A first switching element including first, second, and third data lines formed thereon, wherein a first subpixel of the first pixel is connected to the first gate line and the first data line; A second switching element connected to a gate line and the second data line, and a first liquid crystal capacitor connected to the first and second switching elements, wherein the coupling capacitor of the first pixel includes the first switching element. And a second subpixel of the first pixel includes the second switching element and a second liquid crystal capacitor connected between the coupling capacitor and the second switching element. The first subpixel of the two pixels is a third switching element connected to the first gate line and the second data line, a fourth switching element connected to the first gate line and the third data line, and the third And a third liquid crystal capacitor connected to a fourth switching element, wherein the coupling capacitor of the second pixel is connected to the fourth switching element, and the second subpixel of the second pixel is the third switching element. And a fourth liquid crystal capacitor connected between the coupling capacitor and the third switching element.

The first to fourth liquid crystal capacitors may have positive dielectric anisotropy.

The liquid crystal layer may be vertically or horizontally aligned.

The voltage applied to the second data line may change the first level and the second level at regular intervals.

The first to third data lines may be formed on the same layer.

The second data line may be formed on the same layer as the gate line.

According to another exemplary embodiment of the present invention, a liquid crystal display device includes a plurality of pixels arranged in a matrix, a plurality of gate lines formed on a substrate and transmitting gate signals, and formed on the substrate, and including first and second data. A first switching element connected to the gate line and the first data line, a first switching element connected to the gate line, and the second data line; A second switching element, and a liquid crystal capacitor connected to the first and second switching elements, wherein the liquid crystal capacitor is positioned between the first pixel electrode, the second pixel electrode, and the first and second pixel electrodes. And a liquid crystal layer having positive dielectric anisotropy, the liquid crystal layer being vertically oriented, wherein each pixel represents an image for one or more frames. After the time limit, the image of the low gray level is displayed for at least one frame.

The plurality of pixels may display a low gray level image during the same frame.

The low gray level image may be displayed for one frame.

At least one pixel row or at least one pixel column among the plurality of pixels may display a low gray level image during the same frame, and the remaining pixels may display the image during the same frame.

Two neighboring pixel rows or two neighboring pixel columns may sequentially display images of low gray levels during two consecutive frames.

At least one pixel row displaying the low gray level image may simultaneously display the low gray level image during the same frame.

The data voltage of the low gray level may be 2/3 or less of the data voltage of the image.

According to the present invention, the transmittance can be increased by increasing the pixel voltage range that can be used by the liquid crystal display without replacing the data driver. In addition, the manufacturing cost of the driving unit may be reduced, and the aperture ratio of the display panel may be improved.

In addition, according to one embodiment of the present invention, it is possible to secure a high contrast ratio and a wide viewing angle of the liquid crystal display at the same time, and to speed up the response speed of the liquid crystal molecules.

In addition, good display characteristics can be exhibited regardless of the influence of pressure or the like from the outside of the liquid crystal display device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram showing one pixel with the structure of the liquid crystal display according to an embodiment of the present invention, and FIG. An equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention may include a liquid crystal panel assembly 300, a gate driver 400, and a data driver 500. And a gray voltage generator 800 and a signal controller 600.

1 and 3, the liquid crystal panel assembly 300 is connected to a plurality of signal lines (Gi, Dj, Dj + 1) and arranged in an approximately matrix form in an equivalent circuit. Pixel PX. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines Gi, Dj, Dj + 1 are connected to a plurality of gate lines Gi, which transmit a gate signal (also called a “scan signal”), and a plurality of pairs of data lines, Dj, Dj + 1, which transmit a data voltage. Include. The gate lines Gi extend substantially in the row direction and are substantially parallel to each other, and the data lines Dj and Dj + 1 extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the i-th (i = 1, 2,, n) gate line Gi and the j-th and j + 1th (j = 1, 2,, m) data lines Dj, Dj The pixel PX connected to +1 is connected to the first and second switching elements Qa and Qb connected to the signal lines Gi, Dj and Dj + 1, the liquid crystal capacitor Clc and the first connected thereto. And second storage capacitors Csta and Qstb. The first and second holding capacitors Csta and Cstb may be omitted as necessary.

The first / second switching elements Qa / Qb are three-terminal elements, such as thin film transistors, provided in the lower panel 100, and control terminals thereof are connected to gate lines Gi, and input terminals are data lines. (Dj / Dj + 1) and an output terminal are connected to the liquid crystal capacitor Clc and the first and second sustain capacitors Csta / Cstb.

2 and 3, the liquid crystal capacitor Clc has the first pixel electrode PEa and the second pixel electrode PEb of the lower panel 100 as two terminals, and the first and second pixel electrodes PEa. , The liquid crystal layer 3 between the PEb functions as a dielectric. The first pixel electrode PEa is connected to the first switching element Qa, and the second pixel electrode PEb is connected to the second switching element Qb. Unlike in FIG. 2, the second pixel electrode PEb may be provided in the upper panel 200. In this case, the second pixel electrode PEb is not connected to the switching element and receives a separate common voltage Vcom. . The liquid crystal layer 3 has dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

The pixel electrode PE and the common electrode CE including the first and second pixel electrodes PEa and PEb may be formed in different layers or in the same layer. In the first and second storage capacitors Csta and Cstb, which serve as an auxiliary role of the liquid crystal capacitor Clc, a separate electrode (not shown) provided in the lower display panel 100 includes the first and second pixel electrodes PEa. , PEb) may be formed to overlap each other with an insulator interposed therebetween.

In order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary color over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of basic colors include red, green, and blue. 2 illustrates a color filter CF in which each pixel PX represents one of the primary colors in an area of the upper panel 200 corresponding to the first and second pixel electrodes PEa and PEb. It shows the equilibrium. Unlike FIG. 2, the color filter CF may be disposed above or below the first and second pixel electrodes PEa and PEb of the lower panel 100.

The liquid crystal panel assembly 300 is provided with at least one polarizer (not shown).

Referring back to FIG. 1, the gray voltage generator 800 generates an entire gray voltage related to the transmittance of the pixel PX or a limited number of gray voltages (hereinafter referred to as a reference gray voltage). The reference gray level voltage may include a positive value and a negative value with respect to the common voltage Vcom.

The gate driver 400 is connected to the gate line of the liquid crystal panel assembly 300 to apply a gate signal formed of a combination of the gate on voltage Von and the gate off voltage Voff to the gate line.

The data driver 500 is connected to the data line of the liquid crystal panel assembly 300, selects a gray voltage from the gray voltage generator 800, and applies the gray voltage to the data line as a data voltage. However, when the gray voltage generator 800 does not provide all the gray voltages but provides only a limited number of reference gray voltages, the data driver 500 divides the reference gray voltages to generate a desired data voltage.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with signal lines and thin film transistor switching elements. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, an example of a driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5 and FIGS. 1 to 3.

4 is a schematic cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating a voltage and a pixel applied to a data line of the liquid crystal display according to the exemplary embodiment of the present invention.

First, referring to FIG. 1, the signal controller 600 receives an input image signal R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 210), 256 (= 28) or 64 (= 26). It has two grays. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock signal MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixel PX in one row and corresponds to each digital image signal DAT. The digital image signal DAT is converted into an analog data voltage by selecting a gray voltage to be applied to the corresponding data line.

The gate driver 400 applies the gate-on voltage Von to the gate line Gi according to the gate control signal CONT1 from the signal controller 600, and thus, the first and second switches connected to the gate line Gi are connected to the gate driver 400. The elements Qa and Qb are turned on. Then, the data voltage applied to the data lines Dj and Dj + 1 is applied to the pixel PX through the turned on first and second switching elements Qa and Qb. That is, a data voltage flowing through the first data line Dj is applied to the first pixel electrode PEa, and the second switching element Qb is applied to the second pixel electrode PEb. The data voltage flowing through the second data line Dj + 1 is applied through the data line. In this case, the data voltages applied to the first and second pixel electrodes PEa and PEb are data voltages corresponding to the luminance of the pixel PX, and polarities of the common voltage Vcom are opposite to each other.

The difference between two data voltages having different polarities applied to the first and second pixel electrodes PEa and PEb is represented as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. When a potential difference occurs between both ends of the liquid crystal capacitor Clc, as shown in FIG. 4, an electric field parallel to the surfaces of the display panels 100 and 200 is formed between the liquid crystal layer 3 between the first and second pixel electrodes PEa and PEb. Is generated. When the liquid crystal molecules 31 have positive dielectric anisotropy, the liquid crystal molecules 31 are inclined such that their major axis is parallel to the direction of the electric field, and the degree of inclination depends on the magnitude of the pixel voltage. This liquid crystal layer 3 is referred to as an electrically-induced optical compensation (EOC) mode. In addition, the degree of change in polarization of light passing through the liquid crystal layer 3 varies according to the degree of inclination of the liquid crystal molecules 31. This change in polarization is represented by a change in the transmittance of light by the polarizer, whereby the pixel PX displays the luminance represented by the gray level of the image signal DAT.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and data enable signal DE), thereby sequentially turning on the gate-on voltage for all gate lines. (Von) and a data voltage are applied to all the pixels PX to display an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data voltage applied to each pixel PX is opposite to that of the previous frame. "Invert frame"). At this time, even in one frame, the polarity of the data voltage flowing through one data line is periodically changed according to the characteristics of the inversion signal RVS (eg, row inversion and point inversion) or polarity of the data voltage applied to one pixel row. They can be different (eg invert columns, invert points).

5 is a charge voltage of the liquid crystal capacitor of the neighboring four pixels in the liquid crystal display according to an embodiment of the present invention is 14V, 10V, 5V and 1V, the lowest voltage that can be used by the liquid crystal display is 0V and the highest voltage Is a diagram showing a voltage applied to each data line at 14V.

Referring to FIG. 5, each pixel is connected to two data lines Dj, Dj + 1 / Dj + 2, Dj + 3 / Dj + 4, Dj + 5 / Dj + 6, and Dj + 7. Two data lines (Dj, Dj + 1 / Dj + 2, Dj + 3 / Dj + 4, Dj + 5 / Dj + 6, Dj + 7) connected to one pixel have different polarities with respect to the common voltage Vcom. Different data voltages are applied, and the difference between the two data voltages is the pixel voltage at each pixel PX, for example, when the common voltage Vcom is 7V, the target pixel voltage of the first pixel is 14V. 14V and 0V may be applied to the first and second data lines Dj and Dj + 1, respectively, and since the target pixel voltage of the second pixel is 10V, the third and fourth data lines Dj + 2 and Dj + 3 may be applied. 12V and 2V can be applied to each other. Since the target pixel voltage of the third pixel is 5V, 9.5V and 4.5V can be applied to the fifth and sixth data lines Dj + 4 and Dj + 5, respectively. Since the target pixel voltage of the fourth pixel is 1V, 7.5V and 6.5V may be applied to the seventh and eighth data lines Dj + 6 and Dj + 7, respectively.

By applying two data voltages having different polarities with respect to the common voltage Vcom to one pixel PX, the driving voltage can be increased, the response speed of the liquid crystal molecules can be increased, and the transmittance of the liquid crystal display can be increased. In addition, since the polarities of the two data voltages applied to one pixel PX are opposite to each other, the image quality deterioration due to flicker may be prevented similarly to the point inversion driving even when the inversion of the data driver 500 is column inversion or row inversion. You can stop it.

In addition, when the first and second switching elements Qa and Qb are turned off in one pixel PX, all of the voltages applied to the first and second pixel electrodes PEa and PEb are kickback voltages. Since the voltage drops by, the charging voltage of the pixel PX hardly changes. Therefore, the display characteristic of a liquid crystal display device can be improved.

Furthermore, when the liquid crystal molecules 31 vertically aligned with respect to the display panels 100 and 200 are used, the contrast ratio of the liquid crystal display device can be increased and a wide viewing angle can be realized. In addition, the liquid crystal molecules 31 having a positive dielectric anisotropy have a higher dielectric anisotropy and a lower rotational viscosity than the liquid crystal molecules having a negative dielectric anisotropy, thereby obtaining a faster response speed. Since it is surely defined in the direction of, even if a disturbance occurs in the arrangement of the liquid crystal molecules 31 due to an external influence, it can be quickly rearranged to exhibit good display characteristics.

Next, another example of the driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 6 to 10 and FIGS. 1 to 5.

6 is a diagram illustrating a pixel electrode and a texture portion of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 7 is a simplified cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. FIG. 9 is a flowchart illustrating a driving method of a liquid crystal display according to an exemplary embodiment. FIG. 9 is a diagram illustrating a driving method according to an embodiment of the present invention. A diagram illustrating the method.

First, referring to FIGS. 6 and 7, the liquid crystal panel assembly according to the present exemplary embodiment, like the liquid crystal panel assembly illustrated in FIG. 2, also includes the lower and upper panel 100 and 200 facing each other and the liquid crystal layer interposed therebetween. 3), and the lower panel 100 includes first and second pixel electrodes 191a and 191b.

The liquid crystal molecules 31 of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels 100 and 200 in the absence of an electric field.

When two data voltages having different polarities are applied to the first and second pixel electrodes 191a and 191b with respect to the common voltage Vcom, the liquid crystal molecules 31 of the liquid crystal layer 3 are as shown in FIG. 7. The display panels 100 and 200 are inclined to be horizontal. However, the liquid crystal molecules 31 positioned at the same distance from the first and second pixel electrodes 191a and 191b may not be inclined to either side, and maintain the initial vertical alignment state as shown in FIGS. 6 and 7. Similarly, a texture A having lower luminance than the surroundings may be formed between the two pixel electrodes 191a and 191b.

Referring to FIG. 9, the driving method of the liquid crystal display according to the present exemplary embodiment also displays N frames of images to be displayed for a predetermined time as in the driving method of the liquid crystal display of FIGS. For example, 60 Hz drive displays 60 frames of video per second). After displaying the image of N frames, as shown in FIG. 9, the low gradation image Ig of one frame is further displayed, and thereafter, the image of N frames to be displayed is displayed.

When the liquid crystal display displays a high gray level luminance such as white, when pressure is applied from the outside as shown in FIG. 8, the liquid crystal molecules 31 of the texture A region between the two pixel electrodes 191a and 191b are applied. May lie horizontally on the display panels 100 and 200. This contributes to the transmittance of the liquid crystal display and may be viewed as a bruising in which the texture A portion is yellowish. Such spots may not disappear even if time passes by the liquid crystal molecules 31 being laid down by a strong electric field of the liquid crystal layer 3 even if the pressure from the outside is removed.

As shown in the present embodiment, after displaying a certain number of images of a frame and displaying an image Ig of one frame of low gradation, the image A is horizontally laid down on the display panels 100 and 200 by a strong electric field. When the influence of the liquid crystal molecules 31 in the state disappears, the liquid crystal molecules 31 are returned to be perpendicular to the display panels 100 and 200 again, and as shown in FIG. 8, the stain may disappear and the original white color may be displayed. In this case, the gray scale of the low gray scale image Ig is a gray scale of less than or equal to the gray scale at which the unevenness of the high gray scale image may disappear after the influence of pressure from the outside disappears, and data of 2/3 or less of the data voltage for the high gray scale The gray level may correspond to a voltage.

Unlike the present embodiment, the number of images Ig of the low gradation frame added may be one or more.

Next, a driving method of a liquid crystal display according to another exemplary embodiment of the present invention will be described with reference to FIG. 10.

Referring to FIG. 10, one row or a plurality of rows of pixels display low gray levels in an image of every frame, and one row or a plurality of rows of low gray levels is displayed while the liquid crystal display displays an image of n frames. Scroll from one end of the display screen to the other. At this time, the low gray level or the gray level of the plurality of rows is also a gray level or less gray level in which the unevenness in the high gray level image may disappear after the influence of external pressure or the like disappears, and is less than 2/3 of the data voltage for the high gray level. The gray level may correspond to a data voltage of.

Unlike in FIG. 10, a row of low gray levels may be scrolled from the bottom of the display screen to the top, left to right, or right to left.

As in the present embodiment, by adding a low gradation row or a plurality of rows that are difficult to be visually recognized from the outside every frame, the liquid crystal molecules 31 lying down by the influence of external pressure or the like are scrolled on the display screen to release from the strong electric field. After the external pressure disappears, it can be restored. As a result, display defects such as yellowing stains can be removed.

In the liquid crystal display device including the vertically aligned liquid crystal molecules 31, when displaying a high gray level image, a low gray level image or row is added to the display panels 100 and 200 by the influence of pressure from the outside. Even if lying down and the external influence disappears, the liquid crystal molecules 31 lying down by the strong electric field can be returned to their original state.

An example of the liquid crystal panel assembly described above will now be described in detail with reference to FIGS. 11 and 12.

FIG. 11 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view of the liquid crystal panel assembly of FIG. 11 taken along the line XII-XII.

11 and 12, a liquid crystal panel assembly according to an exemplary embodiment of the present invention includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer interposed between the two display panels 100 and 200. It includes (3).

First, the lower panel 100 will be described.

A plurality of gate conductors including a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction, and each gate line 121 includes a plurality of pairs of first and second gate electrodes 124a and 124b protruding upward. do.

The storage electrode line 131 receives a predetermined voltage such as the common voltage Vcom and mainly extends in the horizontal direction. Each storage electrode line 131 is located between two adjacent gate lines 121 and is closer to the gate line 121 positioned below. Each storage electrode line 131 includes a plurality of pairs of first and second storage electrodes 133a and 133b extending upward and downward and a storage extension 137 having a large area. The first and second sustain electrodes 133a and 133b are formed in a rod shape from the vicinity of the first and second gate electrodes 124a and 124b of the lower gate line 121 to the vicinity of the upper gate line 121. The sustain extension 137 is a substantially rectangular shape in which the lower two corners are cut off, and connects lower ends of the first and second sustain electrodes 133a and 133b to each other. However, the shape and arrangement of the storage electrode lines 131 including the storage electrodes 133a and 133b and the storage extension 137 may be modified in various forms.

The gate conductors 121 and 131 may have a single layer or a multi layer structure.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 121 and 131.

A plurality of pairs of first and second island-like semiconductors 154a and 154b made of hydrogenated amorphous or polycrystalline silicon are formed on the gate insulating layer 140. The first and second semiconductors 154a and 154b are positioned on the first and second gate electrodes 124a and 124b, respectively.

A pair of island-like ohmic contacts 163a and 165a are formed on each of the first semiconductors 154a, and a pair of island-like ohmic contacts (not shown) are formed on each of the second semiconductors 154b. ) Is formed. The ohmic contacts 163a and 165a may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide.

A plurality of pairs of first and second data lines 171a and 171b and a plurality of pairs of first and second drain electrodes are disposed on the ohmic contacts 163a and 165a and the gate insulating layer 140. Data conductors including 175a and 175b are formed.

The first and second data lines 171a and 171b transmit data signals and mainly extend in the vertical direction to intersect the gate line 121 and the storage electrode line 131. The first and second data lines 171a and 171b have a plurality of pairs of first and second source electrodes 173a and 173b which are bent in a U-shape toward the first and second gate electrodes 124a and 124b. It includes.

The first and second drain electrodes 175a and 175b include a rod-shaped one end portion and a wide first and second extension portions 177a and 177b. The rod-shaped one end portion of the first / second drain electrode 175a / 175b is curved while facing the first / second source electrode 173a / 173b around the first / second gate electrode 124a / 124b. It is partially surrounded by the first / second source electrodes 1763a / 173b. The outer contours of the first and second extensions 177a and 177b are approximately similar to the outer contours of the retaining extension 137 of the lower layer. The first extension 177a overlaps the left half of the retention extension 137 and the second extension 177b overlaps the right half of the retention extension 137.

The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are formed of the first and second semiconductors 154a and 154b. Together with the first and second thin film transistors (Qa / Qb), the channels of the first and second thin film transistors (Qa / Qb) are formed of the first and second source electrodes ( The first and second semiconductors 154a and 154b are formed between 173a and 173b and the first and second drain electrodes 175a and 175b.

The data conductors 171a, 171b, 175a, and 175b may have a single layer or multiple layer structure.

The ohmic contacts 163a and 165a exist only between the semiconductors 154a and 154b below and the data conductors 171a, 171b, 175a and 175b thereon, and lower the contact resistance therebetween. The semiconductors 154a and 154b have portions exposed between the source electrodes 173a and 173b and the drain electrodes 175a and 175b and not covered by the data conductors 171a, 171b, 175a and 175b.

A passivation layer 180 made of an inorganic insulator or an organic insulator is formed on the data conductors 171a, 171b, 175a, and 175b and the exposed semiconductors 154a and 154b.

In the passivation layer 180, a plurality of contact holes 185a and 185b exposing the first and second extensions 177a and 177b are formed.

On the passivation layer 180, a plurality of pairs of first and second pixel electrodes made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a reflective metal such as aluminum, silver, chromium, or an alloy thereof A plurality of pixel electrodes 191 including electrodes 191a and 191b are formed.

As illustrated in FIG. 11, the overall outline of one pixel electrode 191 is a quadrangle, and the first and second pixel electrodes 191a and 191b are engaged with the gap 91 interposed therebetween. The first and second pixel electrodes 191a and 191b are vertically symmetrical with respect to the virtual horizontal center line CL as a whole, and are divided into two upper and lower sub-regions.

The first pixel electrode 191a includes a lower protrusion, a left vertical stem, a horizontal stem extending from the center of the vertical stem to the right, and a plurality of branch parts. The branch located at the upper part with respect to the horizontal center line CL extends obliquely in the upper right direction from the vertical stem part or the horizontal stem part, and the branch part located at the lower part extends obliquely in the lower right direction from the vertical stem part or the horizontal stem part. . An angle formed of the branch part with the gate line 121 or the horizontal center line CL may be approximately 45 degrees.

The second pixel electrode 191b includes a bottom protrusion, a right vertical stem, a top and bottom horizontal stem, and a plurality of branch parts. The upper and lower horizontal stem portions extend horizontally from the top and the bottom of the vertical stem portion to the left, respectively. The branch located at the upper part with respect to the horizontal center line CL extends obliquely in the lower left direction from the vertical stem part or the horizontal stem part at the top, and the branch part located at the lower part is located at the upper left side from the vertical stem part or the horizontal stem part at the bottom. Stretches obliquely in the direction. The branch of the second pixel electrode 191b may also have an angle of about 45 degrees with the gate line 121 or the horizontal center line CL. Branch portions of the upper and lower portions about the horizontal center line CL may be perpendicular to each other.

Branch portions of the first and second pixel electrodes 191a and 191b are alternately arranged to be interlocked with each other at regular intervals to form a comb-tooth pattern.

The first and second pixel electrodes 191a and 191b are physically and electrically connected to the first and second drain electrodes 175a and 175b through the contact holes 185a and 185b and are connected to the first and second drain electrodes. The data voltage is applied from 175a / 175b. The first and second subpixel electrodes 191a and 191b form a liquid crystal capacitor Clc together with a portion of the liquid crystal layer 3 therebetween to be applied even after the first and second thin film transistors Qa and Qb are turned off. Maintain the rated voltage.

The first and second extensions 177a and 177b of the first and second drain electrodes 175a and 175b connected to the first and second subpixel electrodes 191a and 191b may have the gate insulating layer 140 therebetween. The first and second storage capacitors Csta / Cstb overlap with the storage extension 137 to form a first / second storage capacitor Csta / Cstb, and the first / second storage capacitor Csta / Cstb enhances the voltage holding capability of the liquid crystal capacitor Clc.

Next, the upper panel 200 will be described.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass, plastic, or the like. The light blocking member 220 prevents light leakage between the pixel electrodes 191 and defines an opening area facing the pixel electrode 191.

A plurality of color filters 230 is also formed on the substrate 210 and the light blocking member 220. The color filter 230 is mostly present in an area surrounded by the light blocking member 220, and may extend long along the column of pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be made of an (organic) insulator, which prevents the color filter 230 from being exposed and provides a flat surface. The overcoat 250 may be omitted.

Alignment layers 11 and 21 are coated on inner surfaces of the display panels 100 and 200, and they may be vertical alignment layers.

Polarizers (not shown) may be provided on the outer surfaces of the display panels 100 and 200.

The liquid crystal layer 3 between the lower panel 100 and the upper panel 200 includes liquid crystal molecules 31 having positive dielectric anisotropy, and the liquid crystal molecules 31 have two long axes in the absence of an electric field. The display panels 100 and 200 may be oriented perpendicular to the surfaces of the display panels 100 and 200.

Applying data voltages having different polarities to the first and second pixel electrodes 191a and 191b generates an electric field that is substantially horizontal to the surfaces of the display panels 100 and 200. Then, the liquid crystal molecules of the liquid crystal layer 3 which are initially oriented perpendicular to the surfaces of the display panels 100 and 200 are inclined in a direction horizontal to the direction of the electric field in response to the electric field, and the liquid crystal molecules are tilted. The degree of change in polarization of incident light in the liquid crystal layer 3 varies depending on the degree. This change in polarization is represented by a change in transmittance by the polarizer, through which the liquid crystal display displays an image.

Using the vertically aligned liquid crystal molecules 31 may increase the contrast ratio of the liquid crystal display and implement a wide viewing angle. In addition, by applying two data voltages having different polarities with respect to the common voltage Vcom to one pixel PX, the driving voltage may be increased and the response speed may be increased. In addition, as described above, the influence of the kickback voltage is eliminated, thereby preventing flicker.

Next, a liquid crystal panel assembly according to another exemplary embodiment of the present invention will be described with reference to FIG. 13.

13 is an equivalent circuit diagram illustrating one pixel together with the structure of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 13, the liquid crystal panel assembly according to the present exemplary embodiment also includes a signal line including a plurality of gate lines Gi and a plurality of pairs of data lines Dj and Dj + 1 and a plurality of pixels PX connected thereto. do. Structurally, the LCD includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

Each pixel PX includes first and second switching elements Qa and Qb, a liquid crystal capacitor Clc, and a storage capacitor Cst connected to the signal lines Gi, Dj, and Dj + 1. do.

In the present exemplary embodiment, unlike the exemplary embodiment illustrated in FIGS. 2 and 3, the first and second pixel electrodes PEa and PEb overlap each other with an insulator interposed therebetween to form one storage capacitor Cst. As described above, when one storage capacitor Cst is formed in each pixel PX, the wiring ratio for the transfer of the common voltage Vcom does not need to be separately formed, thereby increasing the aperture ratio.

The first and second switching elements Qa and Qb, the liquid crystal capacitor Clc, the color filter CF, the polarizer (not shown), and the operation and effects of the liquid crystal display device including the liquid crystal panel assembly. Since the description is the same as the description of FIGS. 1 to 5, a detailed description thereof will be omitted.

Next, a liquid crystal panel assembly according to another exemplary embodiment of the present invention will be described with reference to FIG. 14.

14 is an equivalent circuit diagram illustrating one pixel together with the structure of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 14, the liquid crystal panel assembly according to the present exemplary embodiment also includes a signal line including a plurality of gate lines Gi and a plurality of pairs of data lines Dj and Dj + 1 and a plurality of pixels PX connected thereto. do. Structurally, the LCD includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

Each pixel PX includes first and second switching elements Qa and Qb, a liquid crystal capacitor Clc, and first and second storage capacitors Csta and Cstb connected to signal lines Gi, Dj, and Dj + 1. It includes.

The first / second switching elements Qa / Qb are three-terminal elements, such as thin film transistors, provided in the lower panel 100, and control terminals thereof are connected to gate lines Gi, and input terminals are data lines. (Dj / Dj + 1) and an output terminal are connected to the liquid crystal capacitor Clc and the first and second sustain capacitors Csta / Cstb.

The liquid crystal capacitor Clc has the first and second pixel electrodes PEa and PEb of the lower panel 100 as two terminals, and at the same time, the first pixel electrode PEa or the second pixel electrode PEb and the common electrode ( CE) can be used as two terminals. The first / second pixel electrodes PEa / PEb are connected to the first / second switching elements Qa / Qb, and the common electrode CE is in an area of one pixel PX of the lower panel 100. It is formed on the front surface and is formed on a layer different from the pixel electrode PE including the first and second pixel electrodes PEa and PEb. A predetermined voltage such as a common voltage Vcom is applied to the common electrode CE, and data voltages having different polarities are applied to the first and second pixel electrodes PEa and PEb based on the common voltage Vcom, respectively. . Meanwhile, the liquid crystal layer 3 has positive dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

In the first and second storage capacitors Csta and Cstb, the first and second pixel electrodes PEa and PEb overlap each other with a common electrode CE and an insulator interposed therebetween. However, the first or second storage capacitors Csta and Cstb have a front gate line (not shown) or a separate signal line (not shown) in which the first or second pixel electrodes PEa and PEb are directly over the insulator. ) And may overlap each other.

In the area of the upper panel 200 corresponding to the pixel electrode PE, a color filter 230 indicating one of the primary colors is provided. Unlike FIG. 14, the color filter CF may be positioned above or below the pixel electrode PE of the lower panel 100.

The liquid crystal panel assembly includes at least one polarizer (not shown).

Since the operation and effects of the liquid crystal display including the liquid crystal panel assembly are the same as those of FIGS. 1 to 5, the detailed description thereof will be omitted.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 14 will be described with reference to FIGS. 15 and 16.

FIG. 15 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 16 is a cross-sectional view of the liquid crystal panel assembly of FIG. 15 taken along the line XVI-XVI.

The layered structure of the liquid crystal panel assembly according to the present embodiment is generally the same as the layered structure of the liquid crystal panel assembly shown in FIGS. 11 and 12 except for the light blocking member and the color filter.

First, the lower panel 100 will be described.

A plurality of gate lines 121 including a plurality of pairs of first and second gate electrodes 124a and 124b and a plurality of common voltage lines 131 are formed on the insulating substrate 110.

The common voltage line 131 transmits a common voltage Vcom and extends in a horizontal direction substantially in parallel with the gate line 121. The common voltage line 131 is positioned between two neighboring gate lines 121 and is disposed at approximately the same distance from the two gate lines 121.

A plurality of common electrodes 137 are formed on the substrate 110 and the common voltage line 131. The common electrode 137 is rectangular and arranged in a matrix to almost fill the space between the gate lines 121. The common electrode 137 is connected to the common voltage line 131 to receive the common voltage Vcom. The common electrode 137 may be made of a transparent conductive material such as ITO or IZO.

A gate insulating layer 140 is formed on the gate line 121, the common voltage line 131, and the common electrode 137. The gate insulating layer 140 prevents the gate line 121 and the common electrode 137 from being shorted to each other, and insulates the other conductive thin film formed on them.

A plurality of pairs of first and second island type semiconductors 154a and 154b, a plurality of pairs of first and second island type ohmic contact members 163a and 165a, and a plurality of pairs of first and second data lines on the gate insulating layer 140. 171 and a plurality of pairs of first and second drain electrodes 175a and 175b are formed in this order.

Lower portions made of silicon nitride or silicon oxide on the first and second data lines 171a and 171b, the first and second drain electrodes 175a and 175b, and the exposed portions of the first and second semiconductors 154a and 154b. The passivation layer 180p is formed.

A light blocking member 220 is formed on the lower passivation layer 180p at predetermined intervals and has a plurality of openings 227. The light blocking member 220 may include a straight portion formed up and down and a rectangular portion corresponding to the thin film transistor, and prevent light leakage. The light blocking member 220 has a plurality of through holes 225a and 225b positioned on the first and second drain electrodes 175a and 175b.

A plurality of color filters 230 are formed on the lower passivation layer 180p and the light blocking member 220. The color filter 230 is mostly present in an area surrounded by the light blocking member 230. The openings 233a and 233b are for increasing the holding capacity by making the thickness of the dielectric forming the holding capacitors Csta and Cstb thin.

The lower passivation layer 180p may prevent the pigment of the color filter 230 from entering the exposed portions of the semiconductors 154a and 154b.

An upper passivation layer 180q is formed on the light blocking member 220 and the color filter 230. The upper passivation layer 180q may be made of an inorganic insulating material such as silicon nitride or silicon oxide, and the liquid crystal layer may be formed of an organic material, such as a solvent, which prevents the color filter 230 from lifting and flows from the color filter 230. By suppressing the contamination of (3), it is possible to prevent defects such as afterimages which may be caused when the screen is driven.

However, at least one of the light blocking member 220 and the color filter 230 may be positioned on the upper panel 200, and in this case, one of the lower passivation layer 180p and the upper passivation layer 180q of the lower display panel 100 may be omitted. Can be.

A plurality of contact holes 185a and 185b exposing the first and second drain electrodes 175a and 175b are formed in the upper passivation layer 180q and the lower passivation layer 180p.

A plurality of pairs of first and second pixel electrodes 191a and 191b are formed on the upper passivation layer 180q. Each of the first and second pixel electrodes 191a and 191b includes a plurality of branch electrodes and a vertical connection portion connecting the first and second pixel electrodes 191a and 191b and overlaps the lower common electrode 137.

The vertical connection part of the first pixel electrode 191a extends up and down along the left side of the common electrode 137. The branch electrode positioned at an upper portion of the common voltage line 131 extends obliquely downward to the right side from the connection portion, and the branch electrode positioned at the lower portion extends obliquely upward to the right side from the connection portion.

The vertical connection portion of the second pixel electrode 191a extends up and down along the right side of the common electrode 137. The branch electrode positioned at an upper portion of the common voltage line 131 extends obliquely upward to the left side from the connection portion, and the branch electrode positioned at the lower portion extends obliquely downward to the left side from the connection portion.

The branch electrodes of the first and second pixel electrodes 191a and 191b are alternately arranged in engagement with each other at regular intervals to form a comb-tooth pattern.

The liquid crystal layer 3 between the lower panel 100 and the upper panel 200 includes liquid crystal molecules 31 having positive dielectric anisotropy, and the liquid crystal molecules 31 have two long axes in the absence of an electric field. The display panels 100 and 200 may be oriented perpendicular to the surfaces of the display panels 100 and 200.

The first and second subpixel electrodes 191a and 191b receiving the data voltage from the first and second drain electrodes 175a and 175b form a liquid crystal capacitor Clc together with a portion of the liquid crystal layer 3 therebetween. The applied voltage is maintained even after the first and second thin film transistors Qa and Qb are turned off.

The first / second pixel electrodes 191a / 191b and the common electrode 137 may further include a first / second storage capacitor Csta / Cstb using the gate insulating layer 140 and the lower and upper passivation layers 180p and 180q as a dielectric. To enhance the voltage holding capability of the liquid crystal capacitor Clc. A portion of the color filter 230 positioned between the first and second pixel electrodes 191a and 191b and the common electrode 137 may be removed to increase the storage capacitance of the first and second storage capacitors Csta and Cstb. Can be.

The first and second extensions 177a and 177b of the first and second drain electrodes 175a and 175b connected to the first and second subpixel electrodes 191a and 191b may have the gate insulating layer 140 therebetween. The first and second storage capacitors Csta / Cstb overlap with the storage extension 137 to form a first / second storage capacitor Csta / Cstb, and the first / second storage capacitor Csta / Cstb enhances the voltage holding capability of the liquid crystal capacitor Clc.

Next, the alignment layers 11 and 21 are formed on inner surfaces of the lower and upper display panels 200. The two alignment layers 11 and 21 may be horizontal alignment layers.

When the common voltage Vcom is applied to the common electrode 137 and two data voltages having different polarities are applied to the first and second pixel electrodes 191a and 191b based on the common voltage Vcom, the display panels 100 and 300 are applied. An electric field which is almost horizontal to the surface of) is generated in the liquid crystal layer 3. Then, the liquid crystal molecules 31 of the liquid crystal layer 3 are inclined such that their major axis is horizontal to the electric field, and the degree of polarization of incident light varies according to the inclination degree. Unlike the previous embodiment, in the present embodiment, in addition to the electric field generated in the liquid crystal layer 3 between the first and second pixel electrodes 191a and 191b, the common electrode 137 and the first and second pixel electrodes 191a, Due to the electric field generated in the liquid crystal layer 3 between 191b, the response speed of the liquid crystal molecules 31 can be made faster, and the transmittance of the liquid crystal display device can be further increased. On the other hand, the horizontal component of the electric field is substantially perpendicular to the branch electrodes of the first and second pixel electrodes 191a and 191b, and as shown in FIG. 15, the inclined directions of the branch electrodes are mutually based on the common voltage line 131. Since the liquid crystal molecules 31 are inclined in various directions, a wide viewing angle may be obtained.

Next, a liquid crystal panel assembly according to another exemplary embodiment of the present invention will be described with reference to FIG. 17.

17 is an equivalent circuit diagram illustrating one pixel together with the structure of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 17, the liquid crystal panel assembly according to the present exemplary embodiment also has a signal line including a plurality of gate lines Gi and a plurality of pairs of data lines Dj and Dj + 1, as in the embodiment illustrated in FIG. 14. It includes a plurality of connected pixels (PX).

Each pixel PX includes first and second switching elements Qa and Qb, a liquid crystal capacitor Clc, first and second liquid crystal capacitors Clca and Clcb connected to signal lines Gi, Dj, and Dj + 1. And first and second sustain capacitors Csta and Cstb.

However, in the present exemplary embodiment, unlike the exemplary embodiment illustrated in FIG. 14, the common electrode CE is formed on the front surface of the upper panel 200, and the first and second liquid crystal capacitors Clca / Clcb are disposed on the lower panel 100. The first and second pixel electrodes PEa / PEb and the common electrode CE of the upper panel 200 are configured as two terminals, and the liquid crystal capacitor Clc is connected to the first and second pixels of the lower panel 100. The poles PEa and PEb are two terminals.

In addition, the first and second storage capacitors Csta and Cstb are signal lines (not shown) separate from the pixel electrode PE including the first and second pixel electrodes PEa and PEb, or a front gate line directly thereon. (Not shown) is made by superimposing via an insulator.

In the present exemplary embodiment, the first and second pixel electrodes PEa and PEb, which receive data voltages having different polarities, generate an electric field horizontal to the display panels 100 and 200 in the liquid crystal layer 3. At the same time, the first and second pixel electrodes PEa and PEb of the lower panel 100 and the common electrode CE of the upper panel 200 also generate an electric field in the liquid crystal layer 3, and the first and second pixel electrodes The edge edges PEa and PEb distort the electric field together with the common electrode CE to generate a horizontal component perpendicular to the edge edges of the pixel electrodes PEa and PEb. Then, the liquid crystal molecules of the liquid crystal layer 3 having positive dielectric anisotropy are inclined parallel to the electric field, and the degree of change in polarization of incident light in the liquid crystal layer 3 varies depending on the degree of inclination.

Unlike the present exemplary embodiment, the first and second pixel electrodes PEa and PEb may overlap each other with an insulator interposed therebetween to form one storage capacitor (not shown).

Next, an example of the liquid crystal panel assembly illustrated in FIG. 17 will be described with reference to FIGS. 18 and 19.

18 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 19 is a cross-sectional view of the liquid crystal panel assembly of FIG. 18 taken along a line XIX-XIX.

The layer structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layer structure of the liquid crystal panel assembly shown in FIGS. 11 and 12.

First, the lower panel 100 will be described. A plurality of gate lines 121 and a plurality of storage electrode lines 131 including a plurality of pairs of first and second gate electrodes 124a and 124b are disposed on the insulating substrate 110. Is formed, and a gate insulating film 140 is formed thereon. On the gate insulating layer 140, a plurality of pairs of first and second linear semiconductors 151a and 151b, a plurality of pairs of first and second linear ohmic contacts 161a, and a plurality of pairs of first and second island-type ohmic contacts. 165a, and a plurality of pairs of first and second data lines 171a and 171b and a plurality of pairs of first and second drain electrodes 175a and 175b are formed in this order. The passivation layer 180, the first and second pixel electrodes 191a and 191b, and the alignment layer 11 are sequentially formed thereon.

Referring to the upper panel 200, the light blocking member 220, the color filter 230, the overcoat 250, the common electrode 270, and the alignment layer 21 are sequentially formed on the insulating substrate 210. have.

Unlike the liquid crystal panel assembly illustrated in FIGS. 11 and 12, in the present exemplary embodiment, the first and second semiconductors 151a and 151b are linear and protrude along the source electrodes 173a and 173b and the drain electrodes 175a and 175b. One first and second protrusion 154a, 154b. The linear ohmic contact 161a also includes a protrusion 163a that extends along the data lines 171a and 171b and protrudes along the source electrodes 173a and 173b. The linear semiconductors 151a and 151b have substantially the same planar shape as the data lines 171, the drain electrodes 175a and 175b, and the ohmic contacts 161a, 163a and 165a below.

In the method of manufacturing the lower panel 100 according to an exemplary embodiment of the present invention, the data lines 171a and 171b, the drain electrodes 175a and 175b, the semiconductors 151a and 151b, and the ohmic contacts 161a and 163a may be used. , 165a) is formed in one photo process.

In addition, the storage electrode line 131 is positioned between two neighboring gate lines 121 and the distances from the two gate lines 121 are approximately equal. Each of the first and second pixel electrodes 191a and 191b overlaps the storage electrode line 131 with the gate insulating layer 140 and the passivation layer 180 interposed therebetween to form first and second storage capacitors Csta and Cstb. . In this case, the passivation layer 180 where the first and second pixel electrodes 191a and 191b and the storage electrode line 131 overlap may be removed.

The first and second pixel electrodes 191a and 191b respectively include a horizontal portion and a plurality of vertical portions. The horizontal portion of the first pixel electrode 191a is positioned at the bottom thereof, and the plurality of vertical portions extend upward from the horizontal portion. The horizontal portion of the second pixel electrode 191b is positioned at the upper end, and the plurality of vertical portions extend downward from the horizontal portion. Horizontal portions and vertical portions of the first and second pixel electrodes 191a and 191b are substantially perpendicular to each other, and vertical portions of the first and second pixel electrodes 191a and 191b are alternately disposed.

In addition, various features of the liquid crystal panel assembly illustrated in FIGS. 1 to 5, 6, and 7 and the liquid crystal display apparatus including the same may be applied to the liquid crystal panel assembly illustrated in FIGS. 18 and 19.

Next, a liquid crystal panel assembly according to another exemplary embodiment of the present invention will be described with reference to FIG. 20.

20 is an equivalent circuit diagram illustrating one pixel together with the structure of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 20, the liquid crystal panel assembly according to the present exemplary embodiment also has a signal line including a plurality of gate lines Gi and a plurality of pairs of data lines Dj and Dj + 1, as in the embodiment illustrated in FIG. 8. It includes a plurality of connected pixels (PX).

In the present embodiment, each pixel PX includes first and second switching elements Qa and Qb, a liquid crystal capacitor Clc, and first and second storage capacitors connected to the signal lines Gi, Dj, and Dj + 1. Csta, Cstb).

The control terminal of the first / second switching element Qa / Qb is connected to the gate line Gi, the input terminal is connected to the data line Dj / Dj + 1, and the output terminal is connected to the first / second It is connected to the two pixel electrodes PEa / PEb.

The liquid crystal capacitor Clc has the first and second pixel electrodes PEa and PEb of the lower panel 100 as two terminals. The liquid crystal capacitor Clc includes the first and second pixel electrodes PEa and PEb as two terminals and includes the liquid crystal layer 3 therebetween as a dielectric. The distance between the first and second pixel electrodes PEa and PEb differs depending on the position. Data voltages having different polarities are applied to the first and second pixel electrodes PEa and PEb based on the common voltage Vcom. Meanwhile, the liquid crystal layer 3 has positive dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

The first and second storage capacitors Csta and Cstb may have a signal line (not shown) separate from the first and second pixel electrodes PEa and PEb, or an insulator connected to a front gate line (not shown) immediately above. This is done by overlapping each other.

Unlike the present exemplary embodiment, the first and second pixel electrodes PEa and PEb may overlap each other with an insulator interposed therebetween to form one storage capacitor (not shown).

In the present exemplary embodiment, an electric field in which the first and second pixel electrodes PEa and PEb, which receive data voltages having different polarities based on the common voltage Vcom, is substantially horizontal to the display panels 100 and 200, is applied to the liquid crystal layer 3. ), And when the distance between the first and second pixel electrodes PEa and PEb is close, a stronger electric field is generated as compared to the distant case. Therefore, the degree of inclination of the liquid crystal molecules positioned near the distance between the first and second pixel electrodes PEa and PEb to be parallel to the electric field becomes greater, thereby increasing the light transmittance. Since two regions having different light transmittances exist in one pixel PX, the side gamma curve can be as close to the front gamma curve as possible by properly adjusting the distance between the first and second pixel electrodes PEa and PEb. In this way, side visibility can be improved. In addition, when the distance between the first and second pixel electrodes PEa and PEb and the narrow portion are mixed, the transmittance of the liquid crystal display may be increased.

Other operations and effects of the liquid crystal display including the color filter CF, the polarizer (not shown), and the liquid crystal panel assembly according to the present embodiment are the same as those of FIGS. 1 to 5. Detailed description will be omitted.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 20 will be described with reference to FIGS. 21 and 22.

FIG. 21 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 22 is a cross-sectional view of the liquid crystal panel assembly of FIG. 21 taken along the line XXII-XXII.

The layer structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layer structure of the liquid crystal panel assembly shown in FIGS. 11 and 12.

First, the lower panel 100 will be described. A plurality of gate lines 121 and a plurality of storage electrode lines 131 including a plurality of pairs of first and second gate electrodes 124a and 124b are disposed on the insulating substrate 110. Is formed, and a gate insulating film 140 is formed thereon. A plurality of pairs of first and second island type semiconductors 154a and 154b, a plurality of pairs of first and second island type ohmic contact members 163a and 165a, and a plurality of pairs of first and second data are disposed on the gate insulating layer 140. Lines 171a and 171b and a plurality of pairs of first and second drain electrodes 175a and 175b are formed in this order. A passivation layer 180, first and second pixel electrodes 191a and 191b including a plurality of branch parts, and an alignment layer 11 are sequentially formed thereon. Branch portions of the first and second pixel electrodes 191a and 191b extend obliquely at approximately 45 degrees with the gate line 121 or the storage electrode line 131.

Referring to the upper panel 200, the light blocking member 220, the color filter 230, the overcoat 250, the common electrode 270, and the alignment layer 21 are sequentially formed on the insulating substrate 210. have.

In the present exemplary embodiment, unlike the exemplary embodiments illustrated in FIGS. 11 and 12, the high gradation region close to the low gradation region LA with a distance between the branches of the first and second pixel electrodes 191a and 191b is far from each other. [The remaining areas except the low gradation area LA] exist. The high gradation region is divided into three parts of the upper, lower and middle portions, and the low gradation region LA is positioned between the upper or lower portion and the middle of the high gradation region to form a '<' shape. In the low gray area LA and the high gray area, the interval between the branches of the first and second pixel electrodes 191a and 191b and the width of the branches may vary.

By varying the distance between the first and second pixel electrodes 191a and 191b in one pixel PX, the inclination angles of the liquid crystal molecules 31 may be varied, and different luminance for one image information. Can be represented. By properly adjusting the distance between the branch portions of the first and second pixel electrodes 191a and 191b, the image viewed from the side can be as close as possible to the image viewed from the front, the side visibility can be improved, and the transmittance can be increased. Can be.

In addition, the storage electrode line 131 includes a plurality of storage electrodes 137 protruding downward, and each of the first and second drain electrodes 175a and 175b overlaps the storage electrode 137 to form first and second electrodes. It forms a holding capacitor (Csta, Cstb).

In addition, the first and second data lines 171a and 171b may have a plurality of pairs of first and second source electrodes 173a bent toward the first and second gate electrodes 124a and 124b in a C shape or inverted to the left and right. 173b).

In addition, various features of the liquid crystal panel assembly illustrated in FIGS. 1 to 5, 6, and 7 and the liquid crystal display apparatus including the same may be applied to the liquid crystal panel assembly illustrated in FIGS. 21 and 22.

Next, another example of the liquid crystal panel assembly illustrated in FIG. 20 will be described with reference to FIGS. 23 to 25.

23 to 25 are layout views of the liquid crystal panel assembly according to the exemplary embodiment of the present invention, respectively.

First, the liquid crystal panel assembly shown in FIG. 23 will be described.

The liquid crystal panel assembly according to the present embodiment is usually the same as the liquid crystal panel assembly shown in FIGS. 21 and 22.

However, the lower display panel 100 or the upper display panel 200 further includes a light blocking member 220, and the light blocking member 220 prevents light leakage between the pixel electrodes 191 and opens an opening area facing the pixel electrode 191. define.

In addition, the low gradation region LA whose distance between the first and second pixel electrodes 191a and 191b is far from the high gradation region where the distance between the first and second pixel electrodes 191a and 191b is close (low gradation region ( And the gap between the first and second pixel electrodes 191a and 191b, which are located in the upper and lower portions of the remaining region except for LA).

Next, the liquid crystal panel assembly shown in FIG. 24 will be described.

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as that of the liquid crystal panel assembly shown in FIGS. 21 and 22. Hereinafter, a description will be given focusing on differences from the embodiment shown in FIGS. 21 and 22.

First, a lower panel (not shown) will be described. A plurality of gate lines 121 and a plurality of holding lines including a plurality of pairs of first and second gate electrodes 124a and 124b may be disposed on an insulating substrate (not shown). A plurality of gate conductors including the electrode lines 131 are formed.

The storage electrode line 131 includes a plurality of pairs of first and second storage electrodes 133a and 133b. The first and second storage electrodes 133a and 133b are disposed at a predetermined distance and extend up and down, respectively, and include an extension at the bottom thereof. The storage electrode line 131 including the storage electrodes 133a and 133b overlaps the first and second pixel electrodes 191a and 191b to form first and second storage capacitors Csta and Cstb.

On the gate conductors 121 and 131, a gate insulating film (not shown), a plurality of pairs of first and second island type semiconductors 154a and 154b, and a plurality of pairs of first and second island type ohmic contacts (not shown) And a plurality of pairs of first and second data lines 171a and 171b and a plurality of pairs of first and second drain electrodes 175a and 175b are formed in this order.

The first and second data lines 171a and 171b extend in a right / left direction toward the first and second gate electrodes 124a and 124b and bend in a W shape to form a plurality of pairs of first and second source electrodes 173a and 173b. ). The first / second drain electrodes 175a / 175b include a pair of rod-shaped ends and the other wide ends.

A passivation layer 180 is formed on the first and second data lines 171a and 171b, the first and second drain electrodes 175a and 175b, and the exposed portions of the semiconductors 154a and 154b, and the first and second data lines 171a and 171b are formed thereon. Second pixel electrodes 191a and 191b are formed.

The first pixel electrode 191a includes a vertical portion 192a, a horizontal portion 193a, an upper branch portion 194a, and a lower branch portion 195a. The horizontal portion 193a substantially vertically divides the vertical portion 192a and extends to the right. The upper branch 194a is positioned above the horizontal portion 193a and extends obliquely upward from the vertical portion 192a or the horizontal portion 193a. The lower branch portion 195a is positioned below the horizontal portion 193a and extends obliquely downward to the right from the vertical portion 192a or the horizontal portion 193a.

The second pixel electrode 191b includes a vertical portion 192b, an upper horizontal portion 193b1, a lower horizontal portion 193b2, an upper branch portion 194b, and a lower branch portion 195b. The vertical portion 192b faces the vertical portion 192a with the horizontal portion 193a of the first pixel electrode 191a interposed therebetween, and the upper and lower horizontal portions 193b1 and 193b2 respectively have a vertical portion 192b. It extends from the top and bottom to the left and is approximately perpendicular to the vertical portion 192b. The upper branch portion 194b is positioned above the horizontal portion 193a of the first pixel electrode 191a and is lower left from the vertical portion 192b or the upper horizontal portion 193b1 of the second pixel electrode 191b. Stretches obliquely into The lower branch portion 195b is positioned below the horizontal portion 193a of the first pixel electrode 191a and moves upward to the left from the vertical portion 192a or the lower horizontal portion 193b2 of the second pixel electrode 191b. Stretches at an angle

The branch portions 194a, 194b, 195a, and 195b of the first and second pixel electrodes 191a and 191b may form an angle of about 45 degrees with the gate line 121 or the storage electrode line 131.

The upper and lower branch portions 194a, 194b, 195a, and 195b of the first and second pixel electrodes 191a and 191b are alternately disposed and disposed between the adjacent first and second pixel electrodes 191a and 191b. The parts farther from each other are alternated. That is, the upper and lower branches 194b and 195b of the second pixel electrode 191b are adjacent to the upper and lower branches 194a and 195a of the first pixel electrode 191a which are adjacent to the lower and upper sides. Is closer to the top / bottom branches 194a / 195a. On the contrary, the upper and lower branches 194b and 195b of the second pixel electrode 191b may be closer to the upper and lower branches 194a and 195a of the first pixel electrode 191a adjacent to the lower and upper sides. .

In this way, the distance between the first pixel electrode 191a and the second pixel electrode 191b in one pixel may be alternately placed with the part close to each other to vary the intensity of the electric field generated in the liquid crystal layer 3. The inclination angle of the liquid crystal molecules 31 may also be varied, and the side visibility of the liquid crystal display may be improved and the transmittance may be increased.

Unlike the present exemplary embodiment, a plurality of portions having a large gap may be positioned after a portion having a narrow gap between the first and second pixel electrodes 191a and 191b. Alternatively, a plurality of narrow gaps may be positioned after a wide gap between the first and second pixel electrodes 191a and 191b. In addition, the distance between the first and second pixel electrodes 191a and 191b may be adjusted or the arrangement of the narrow and wide portions may be adjusted to maximize transmittance and improve side visibility.

An alignment film (not shown) is formed on the next passivation film (not shown) and the pixel electrodes 191a and 191b.

Next, the upper panel (not shown) will be described. A light blocking member (not shown), a color filter (not shown), an overcoat (not shown), and an alignment layer (not shown) may be disposed on an insulating substrate (not shown). Is formed in this order.

In addition, various features of the liquid crystal panel assembly illustrated in FIGS. 21 and 22 may be applied to the liquid crystal panel assembly illustrated in FIG. 24.

Next, the liquid crystal panel assembly shown in FIG. 25 will be described.

The liquid crystal panel assembly according to the present embodiment is also generally the same as the liquid crystal panel assembly shown in FIG. Hereinafter, a description will be given focusing on differences from the embodiment shown in FIG. 24.

Unlike the liquid crystal panel assembly shown in FIG. 24, in the present exemplary embodiment, the storage electrode line 131 is adjacent to the gate line 121 positioned below the two neighboring gate lines 121, and the first and second drain electrodes of the upper layer are disposed. First and second sustain electrodes 133a and 133b overlapping the first and second protrusions 175a and 175b, respectively. The first and second storage electrodes 133a and 133b overlap the portions having the large areas of the first and second drain electrodes 175a and 175b with the gate insulating layer 140 interposed therebetween, respectively. (Csta, Cstb).

In addition, the liquid crystal panel assembly according to the present exemplary embodiment includes the first and second pixel electrodes 191a and 191b on the passivation layer 180, and the outline of the first and second pixel electrodes 191a and 191b is generally rectangular.

The first pixel electrode 191a extends from the left vertical portion 192a that extends up and down, the right vertical portion 198a that extends shortly up and down, the upper horizontal portion 193a, and a plurality of portions extending from these 192a, 193a, and 198a. A curved branch portion 195a and a plurality of straight branch portions 197a, and a pair of central curved portions 196a extending long from bottom to top, are bent three times. The second pixel electrode 191b extends from the left vertical portion 198b shortly extending up and down, the right vertical portion 192b extending longly up and down, the lower horizontal portion 193b, and the plurality of lengths extending from these 192b, 193b, and 198b. A curved branch portion 195b and a plurality of straight branch portions 197b and a pair of central curved portions 196b extending three times from the bottom to the upper portion thereof are bent.

The bent branches 195a, the straight branches 197a, and the central bends 196a of the first pixel electrode 191a are the bent branches 195b and the straight branches 197b of the second pixel electrode 191b. And central curved portions 196b, which are alternately disposed, and the distance between neighboring curved branches 195a and 195b or the straight branch portions 197a and 197b is smaller than the distance between adjacent central curved portions 196a and 196b. far. Therefore, the strength of the electric field generated between the central bends 196a and 196b is stronger than that of the electric field generated between the bent branches 195a and 195b or the straight branches 197a and 197b and the liquid crystal layer (not shown). The angle at which the liquid crystal molecules of are inclined is larger. By varying the inclination angle of the liquid crystal molecules in one pixel PX, the luminance in one pixel PX can be varied and the distance between the pixel electrodes 191a and 191b is adjusted so that the side visibility of the liquid crystal display device is adjusted. Can make it good.

Next, a liquid crystal panel assembly according to another exemplary embodiment of the present invention will be described with reference to FIG. 26.

FIG. 26 is an equivalent circuit diagram illustrating one pixel together with the structure of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 26, each pixel PX includes a pair of first and second subpixels PXh and PXl. The first / second subpixel PXh / PXl includes a liquid crystal capacitor Clch / Clcl and a storage capacitor Csth / Cstl. At least one of the first and second subpixels PXh and PXl includes two switching elements (not shown) connected to the gate line, the data line, and the liquid crystal capacitors Clch and Clcl.

The liquid crystal capacitor Clch / Clcl has two terminals of the first subpixel electrode PEha / PEla and the second subpixel electrode PEhb / PElb of the lower panel 100, and the first subpixel electrode PEha / PEla. And the liquid crystal layer 3 between the second subpixel electrode PEhb / PElb function as a dielectric. Each of the second subpixel electrodes PEhb and PElb is connected to a separate switching element (not shown), and at least one of the first subpixel electrodes PEha and PEla is also connected to a separate switching element (not shown). It is. However, in some cases, the second subpixel electrodes PEhb and PElb may be provided in the upper panel 200. In this case, the second subpixel electrodes PEhb and PElb are not connected to the switching element and have a separate common voltage ( Vcom) can be authorized. Meanwhile, the liquid crystal molecules of the liquid crystal layer 3 have positive dielectric anisotropy and are oriented perpendicular to the display panels 100 and 200.

In the storage capacitor Csth / Cstl, which serves as a secondary role of the liquid crystal capacitor Clch / Clcl, the first subpixel electrode PEha / PEla and the second subpixel electrode PEhb / PElb of the lower panel 100 are insulators. This is nested with.

In addition, the contents of the color filter CF and the polarizer (not shown) are the same as in the previous embodiment and thus will be omitted.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 26 will be described in detail with reference to FIG. 27.

27 is an equivalent circuit diagram of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 27, the liquid crystal panel assembly according to the present exemplary embodiment includes a signal line including a gate line Gi and adjacent first and second data lines Dj and Dj + 1 and a pixel PX connected thereto. Include.

The pixel PX includes a pair of first and second subpixels PXh and PXl. The first and second subpixels PXh / PXl and the first and second switching elements Qha, Qhb / Qla, and Qlb connected to the gate line Gi and the data line Dj / Dj + 1, respectively. And liquid crystal capacitors Clch / Clcl connected thereto, and first and second storage capacitors Cstha, Csthb / Cstla, and Cstlb.

Data voltages of opposite polarity to the common voltage Vcom are applied to the first and second data lines Dj and Dj + 1.

The control terminal and the input terminal of the first switching element Qha / Qla of the first / second subpixel PXh / PXl are connected to the gate line Gi and the first data line Dj, respectively. The control terminal and the input terminal of the second switching element Qhb / Qlb of the second subpixel PXh / PXl are connected to the gate line Gi and the second data line Dj + 1, respectively. In addition, the output terminal of the first switching element Qha / Qla is connected to the liquid crystal capacitor Clch / Clcl and the first sustain capacitor Cstha / Cstla, and the output terminal of the second switching element Qhb / Qlb is liquid crystal. It is connected to a capacitor (Clch / Clcl) and a second holding capacitor (Csthb / Cstlb).

In addition, the drain and gate electrodes of the first and second switching elements Qha, Qhb / Qla, and Qlb of the first and second subpixels PXh / PXl may have first and second parasitic capacitors Cgdha, Cgdhb / Cgdla. , Cgdlb).

In this embodiment, the magnitudes of the kickback voltages at both terminals of the liquid crystal capacitors Clch and Clcl are varied by adjusting the capacitances of the first and second parasitic capacitors Cgdha, Cgdhb, Cgdla, and Cgdlb. Change the charging voltage of (PXh, PXl).

For example, 7V and -7V are applied to the first and second data lines Dj and Dj + 1, respectively, and the second parasitic capacitor Cgdhb and the second subpixel PXl of the first subpixel PXh are applied. The kickback voltage of the first parasitic capacitor (Cgdla) is 0.5V, the second parasitic capacitor (Cgdha) of the first subpixel (PXh) and the second parasitic capacitor (Cgdlb) of the second subpixel (PXl) Consider the case where the kickback voltage at) is 1V. Then, when the gate-off voltage Voff is applied to the gate line Gi, voltages at both ends of the liquid crystal capacitors Clch and Clcl are lowered by kickback voltages, respectively, and 6V and -7.5V are applied to both ends of the liquid crystal capacitor Clch. The voltage is 13.5V, 6.5V and -8V are applied to both ends of the liquid crystal capacitor Clcl, and the charging voltage is 14.5V. Accordingly, the pixel voltages of the first and second subpixels PXh and PXl may be 13.5V and 14.5, respectively, so that the inclination angles of the liquid crystal molecules may be different from each other. The transmittance of may be different. By adjusting the capacitances of the first and second parasitic capacitors Cgdha, Cgdhb, Cgdla, and Cgdlb, the visibility of the liquid crystal display can be improved and the transmittance of the liquid crystal display can be increased because the data voltage is not reduced.

Since the liquid crystal capacitors Clch and Clcl and the first and second storage capacitors Cstha, Csthb, Cstla, and Cstlb have been described above, detailed descriptions thereof will be omitted.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 27 will be described with reference to FIG. 28.

28 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

The layer structure of the liquid crystal panel assembly according to the present embodiment is generally the same as the layer structure of the liquid crystal panel assembly shown in FIGS. 21 and 22.

First, a lower display panel (not shown) will be described. A plurality of gate lines including a plurality of pairs of first gate electrodes 124ha and 124la and second gate electrodes 124hb and 124lb are disposed on an insulating substrate (not shown). Reference numeral 121 and a plurality of pairs of upper and lower sustain electrode lines 131h and 131l are formed. On it, a gate insulating film (not shown), a plurality of pairs of first semiconductors 154ha and 154la and a second semiconductor 154hb and 154lb, a plurality of pairs of first island-type ohmic contacts (not shown), and a second island-type resistivity A contact member (not shown), a plurality of pairs of first and second data lines 171a and 171b, a plurality of pairs of first drain electrodes 175ha and 175la, a second drain electrode 175hb and 175lb, and a protective film (not shown) And a plurality of pairs of first subpixel electrodes 191ha and 191la and second subpixel electrodes 191hb and 191lb are formed in this order.

Next, the upper panel (not shown) will be described. A light blocking member (not shown), a color filter (not shown), an overcoat (not shown), and an alignment layer (not shown) may be disposed on an insulating substrate (not shown). Is formed in this order.

The gate line 121 and the storage electrode lines 131h and 131l extend across the center of the pixel PX area, and the gate line 121 is positioned between the storage electrode lines 131h and 131l.

The first and second subpixel electrodes 191ha and 191hb of the first subpixel PXh are positioned above the gate line 121 and the first and second subpixel electrodes of the second subpixel PXl. 191la and 191lb are positioned below the gate line 121. In the first / second subpixel area PXh / PXl, the first and second subpixel electrodes 191ha, 191hb / 191la, and 191lb include a plurality of branch portions extending obliquely with respect to the gate line 121, and the first and second subpixel electrodes 191ha, 191hb / 191la, and 191lb. And branch portions of the second subpixel electrodes 191ha, 191hb / 191la, and 191lb are alternately arranged.

As described with reference to FIG. 27, a parasitic capacitor formed by overlapping the first and second gate electrodes 124ha, 124hb, 124la, and 124lb and the first and second drain electrodes 175ha, 175hb, 175la, and 175lb ( By adjusting the capacities of Cgdha, Cgdhb, Cgdla, and Cgdlb, the charging voltages of the first and second subpixels PXh and PXl, that is, the pixel voltages, may be changed in size, and the side visibility may be improved.

In addition, since the polarities of the data voltages applied to the first and second data lines 171a and 171b are reversed, the response voltages of the liquid crystal molecules may be increased by increasing the driving voltage and the transmittance of the liquid crystal display device.

In addition, various features in the embodiment shown in FIGS. 21 and 22 may be applied to the present embodiment.

Next, another example of the liquid crystal panel assembly illustrated in FIG. 26 will be described with reference to FIG. 29.

29 is an equivalent circuit diagram of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

In the liquid crystal panel assembly according to the present exemplary embodiment, unlike the liquid crystal panel assembly illustrated in FIG. 27, the first and second subpixels PXh / PXl include one sustaining capacitor Csth / Cstl. When one sustain capacitor Csth and Cstl is formed in each of the subpixels PXh and PXl, the aperture ratio is increased because a separate wiring for transferring the common voltage Vcom is not required.

Next, another example of the liquid crystal panel assembly illustrated in FIG. 26 will be described with reference to FIGS. 30 to 33 and FIG. 1 described above.

30 to 33 are equivalent circuit diagrams of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention, respectively.

Referring to FIG. 30, the liquid crystal panel assembly according to the present exemplary embodiment includes a gate line Gi and a signal line including neighboring first to fourth data lines Dj, Dj + 1, Dj + 2, and Dj + 3. And a pixel PX connected thereto.

The pixel PX includes a pair of first and second subpixels PXh and PXl, and each of the subpixels PXh / PXl has a gate line Gi and a data line Dj and Dj + 1 / Dj, respectively. The first and second switching elements Qha, Qhb / Qla, and Qlb connected to +2 and Dj + 3, a liquid crystal capacitor Clch / Clcl, and a storage capacitor Csth / Cstl connected thereto.

In the liquid crystal display including the liquid crystal panel assembly, the signal controller 600 receives the input image signals R, G, and B for one pixel PX and outputs the two subpixels PXh and PXl. The image signal may be converted into a DAT and transmitted to the data driver 500. Alternatively, the gray voltage generator 800 separately sets the gray voltage sets for the two sub-pixels PXh and PXl and alternately provides them to the data driver 500 or alternately selects them in the data driver 500. Different voltages may be applied to the subpixels PXh and PXl. However, at this time, the image signal may be corrected or a set of gray voltages may be made such that the composite gamma curve of the two subpixels PXh and PXl is close to the reference gamma curve at the front. For example, the composite gamma curve at the front side is made to coincide with the reference gamma curve at the front side determined to be most suitable for this liquid crystal panel assembly, and the composite gamma curve at the side is made closest to the reference gamma curve at the front side. In this way, the side visibility of a liquid crystal display device can be improved.

In addition, the transmittance and response speed are increased by increasing the driving voltage by reversing the polarity of the data voltages applied to the data lines Dj, Dj + 1 / Dj + 2 and Dj + 3 connected to the first and second subpixels PXh / PXl. Can increase.

Next, referring to FIG. 31, unlike the liquid crystal panel assembly illustrated in FIG. 30, the first and second subpixels PXh / PXl include one storage capacitor Csth / Cstl. do. In addition, various descriptions of the embodiment shown in FIG. 13 or FIG. 30 may be applied to the present embodiment.

Next, referring to FIG. 32, the liquid crystal panel assembly according to the present exemplary embodiment includes first and second gate lines Gi and Gi + 1 and first and second data lines Dj and Dj + 1 that are adjacent to each other. It includes a signal line and a pixel (PX) connected thereto.

The pixel PX includes a pair of first and second subpixels PXh and PXl, and the first and second subpixels PXh / PXl include the first and second switching elements Qha and Qhb / Qla. , Qlb) and liquid crystal capacitors Clch / Clcl connected thereto, and first and second storage capacitors Cstha, Csthb / Cstla, and Cstlb.

Unlike the liquid crystal panel assembly illustrated in FIG. 31, the liquid crystal panel assembly according to the present exemplary embodiment has first and second subpixels PXh and PXl constituting one pixel PX adjacent to each other in a column direction and have different gate lines ( Gi, Gi + 1). In the exemplary embodiment illustrated in FIG. 26, the first and second subpixels PXh and PXl receive different data voltages at the same time, whereas in the present exemplary embodiment, the first and second subpixels PXh and PXl are applied. ) Receives different data voltages with a time difference. Thus, visibility can be improved by changing pixel voltages of the head pixels PXh and PXl. In addition, as in the previous embodiments, voltages applied to both ends of the liquid crystal capacitors Clch and Clcl of the first and second subpixels PXh and PXl have different polarities and have the same effect with respect to the common voltage Vcom. .

On the other hand, in the liquid crystal panel assembly illustrated in FIG. 33, unlike the liquid crystal panel assembly illustrated in FIG. 32, the first and second subpixels PXh / PXl include one storage capacitor Csth / Cstl.

Next, another example of the liquid crystal panel assembly illustrated in FIG. 26 will be described with reference to FIG. 34.

34 is an equivalent circuit diagram of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 34, a liquid crystal panel assembly according to the present exemplary embodiment includes a signal line including a gate line Gi and neighboring first and second data lines Dj and Dj + 1 and a pixel PX connected thereto. Include. It will be described below with a focus on differences from the previous embodiment.

The pixel PX includes a pair of first and second subpixels PXh and PXl and a coupling capacitor Ccp connected to two subpixels PXh and PXl. The first subpixel PXh includes the first and second switching elements Qa and Qb, the liquid crystal capacitor Clch connected thereto, and the first and second storage capacitors Csta and Cstb. The second subpixel PXl includes a second switching element Qb connected to the coupling capacitor Ccp, a liquid crystal capacitor Clcl connected thereto, and a second storage capacitor Cstb.

The first switching element Qa applies the data voltage from the data line Dj to the liquid crystal capacitor Clch and the coupling capacitor Ccp according to the gate signal from the gate line Gi, and the second switching element Qb. ) Receives a data voltage of opposite polarity to the data voltage of the data line Dj from the data line Dj + 1 and applies it to the two liquid crystal capacitors Clch and Clcl. Then, the voltage applied to both ends of the liquid crystal capacitor Clcl of the second subpixel PXl is applied to both ends of the coupling capacitor Ccp than the voltage applied to both ends of the liquid crystal capacitor Clch of the first subpixel PXh. The voltage charged in the liquid crystal capacitor Clcl is always smaller than the voltage charged in the liquid crystal capacitor Clch because it is as small as the voltage that becomes.

The proper ratio of the charging voltage of the liquid crystal capacitors Clch and Clcl can be obtained by adjusting the capacitance of the coupling capacitor Ccp. In this way, the side visibility of a liquid crystal display device can be improved.

Various features in the foregoing embodiments can also be applied to the liquid crystal panel assembly according to the present embodiment.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 34 will be described with reference to FIG. 35.

35 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

The layered structure of the liquid crystal panel assembly according to the present embodiment is also generally the same as that of the liquid crystal panel assembly shown in FIGS. 21 and 22.

First, a lower display panel (not shown) will be described. A plurality of gate lines 121 including a plurality of pairs of first and second gate electrodes 124a and 124b may be disposed on an insulating substrate (not shown). A plurality of connection electrodes 135 including an electrode line 131 and a horizontal electrode 137 are formed. On it, a gate insulating film (not shown), a plurality of pairs of first and second semiconductors 154a and 154b, a plurality of pairs of first and second island-type ohmic contacts (not shown), and a plurality of pairs of first and second Two data lines 171a and 171b, a plurality of pairs of first and second drain electrodes 175a and 175b, a passivation layer (not shown), and a plurality of pairs of first and second subpixel electrodes 191ha and 191la. The first pixel electrode 191a and the second pixel electrode 191b are sequentially formed.

The first subpixel electrode 191ha includes upper and lower subpixel electrodes 191hau and 191had, and the second subpixel electrode 191la is positioned between the upper and lower subpixel electrodes 191hau and 191had. The upper and lower subpixel electrodes 191hau and 191had are connected to the connection electrode 135 of the lower layer through the contact holes 187d and 187u to receive the same voltage.

Upper and lower subpixel electrodes 191hau and 191had of the first subpixel electrode 191ha respectively include a vertical portion and a plurality of branch portions, and the second subpixel electrode 191la includes a horizontal portion 197la and a branch portion. The second pixel electrode 191b includes a vertical portion, a horizontal portion, and a plurality of branch portions extending upward and downward. The branch portions of the first pixel electrode 191a and the branch portions of the second pixel electrode 191b are alternately arranged. Branch portions of the first and second pixel electrodes 191a and 191b adjacent to each other and the liquid crystal layer 3 therebetween form liquid crystal capacitors Clch and Clcl, and horizontal portions of the second subpixel electrode 191la 197la overlaps the horizontal electrode 137 of the connection electrode 135 of the lower layer to which the same voltage as the first subpixel electrode 191ha is applied to form a coupling capacitor Ccp. In addition, the storage electrode line 131 and the first and second pixel electrodes 191a and 191b overlap with each other to form first and second storage capacitors Csta and Cstb.

In addition, various features of the liquid crystal panel assembly of FIG. 34 and the foregoing embodiments may be applied to the present embodiment.

Next, another example of the liquid crystal panel assembly illustrated in FIG. 26 will be described in detail with reference to FIG. 36.

36 is an equivalent circuit diagram of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 36, the liquid crystal panel assembly according to the present exemplary embodiment may include two gate lines Gi and Gi + 1, first and second data lines Dj and Dj + 1 and a common voltage line that are adjacent to each other. Signal line) and a plurality of pixels PX connected thereto.

Each pixel PX includes first and second subpixels PXh and PXl and a boost unit BU. The first / second subpixel PXh / PXl includes the first switching element Qha / Qla and the second switching element Qb, the liquid crystal capacitor Clch / Clcl, the first storage capacitor Cstha / Cstla, and the first subpixel PXh / PXl. 2 includes a holding capacitor (Cstb). The boosting unit BU includes a third switching element Qc, a fourth switching element Qb, and a boosting capacitor Cb.

The control terminal of the first switching element Qha / Qla of the first / second subpixel PXh / PXl is connected to the gate line Gi, and the input terminal is connected to the first data line Dj. The output terminal is connected to the liquid crystal capacitor Clch / Clcl and the first sustain capacitor Cstha / Cstla. The control terminal of the second switching element Qb is connected to the gate line Gi, the input terminal is connected to the second data line Dj + 1, and the output terminal is the liquid crystal capacitor Clch / Clcl and the first terminal. 2 It is connected to the holding capacitor (Cstb).

The control terminal of the third switching element Qc is connected to the gate line Gi, the input terminal is connected to a separate common voltage line (not shown) for transmitting a common voltage, and the output terminal is connected to the fourth switching element. (Qb) and boost capacitor (Cb) are connected.

The control terminal of the fourth switching element Qb is connected to the rear gate line Gi + 1, and the input terminal is the output terminal of the first switching element Qla, the liquid crystal capacitor Clcl, and the first storage capacitor Cstla. ) Is connected to the output terminal of the third switching element Qc and the boost capacitor Cb.

The operation of the liquid crystal display including the liquid crystal panel assembly according to the present embodiment is as follows.

First, a data voltage having a positive polarity is applied to the data line Dj based on the common voltage Vcom, and a data voltage having a negative polarity is applied to the data line Dj + 1. Will be explained.

When the gate-on voltage Von is applied to the gate line Gi, the first to third thin film transistors Qha, Qla, Qb, and Qc connected thereto are turned on.

Accordingly, the data voltage (+) of the data line Dj is applied to one terminal of the liquid crystal capacitors Clch and Clcl through the turned-on first switching elements Qha and Qla and the data through the second switching element Qb. The data voltage (−) of the line Dj + 1 is applied to the other terminals of the liquid crystal capacitors Clch and Clcl.

Meanwhile, the common voltage Vcom is applied to one terminal of the boost capacitor Cb through the third thin film transistor Qc so that the boost capacitor Cb is equal to the voltage of the output terminal of the first switching element Qha and the common voltage Vcom. Is charged by the difference of

Thereafter, when the gate-off voltage Voff is applied to the gate line Gi and the gate-on voltage Von is applied to the next gate line Gi + 1, the first to third thin film transistors Qha, Qla, Qb, Qc) is turned off and the fourth thin film transistor Qb is turned on.

Then, the positive charge collected at the output terminal of the first switching element Qla and the negative charge collected at the output terminal of the third switching element Qc are mixed with each other. The voltage at the output terminal is lowered and the voltage at the output terminal of the third switching element Qc is increased. When the voltage of the output terminal of the third switching element Qc, which is one terminal of the boost capacitor Cb, rises, the voltage of the output terminal of the first switching element Qha in the isolated state also increases, and accordingly, the liquid crystal capacitor Clch The voltage difference across both ends becomes large. On the other hand, since the voltage at the output terminal of the first switching element Qla falls, the voltage across the liquid crystal capacitor Clcl also drops.

On the contrary, when a data voltage having a negative polarity is applied to the first data line Dj based on the common voltage Vcom, the capacitors gather at both ends of the capacitors Clch, Clcl, Cstha, Cstla, Cb, and Cstb. The charge is the opposite of the previous explanation.

In this embodiment, the charging voltage of the liquid crystal capacitor Clch of the first subpixel PXh is always higher than the charging voltage of the liquid crystal capacitor Clcl of the second subpixel PXl regardless of the polarity of the applied data voltage. Can be. Therefore, the luminance of the two subpixels PXh and PXl may be changed by changing the charging voltages of the liquid crystal capacitors Clch and Clcl without reducing the overall luminance and transmittance.

In addition, whenever the gate-on voltage is applied to the gate line Gi, the voltage of the boost capacitor Cb is refreshed by the third thin film transistor Qc to the common voltage Vcom. Afterimage can be removed.

At the same time, data voltages having different polarities may be applied to the first and second data lines Dj and Dj + 1 to increase the transmittance and response speed of the liquid crystal display. Applicable to

Unlike the present embodiment, instead of the first storage capacitor Cstha / Cstla and the second storage capacitor Cstb, the first / second subpixel PXh / PXl may include one storage capacitor (not shown). .

Next, another example of the liquid crystal panel assembly illustrated in FIG. 2 will be described with reference to FIG. 37.

37 is an equivalent circuit diagram of two pixels of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

2 and 37, the liquid crystal panel assembly according to the present exemplary embodiment also includes lower and upper panel 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The liquid crystal panel assembly according to the present exemplary embodiment includes a signal line including a gate line Gi and neighboring first, second and third data lines Dj, Dj + 1, and Dj + 2 and first and second signals connected thereto. It includes two pixels PXn and PXn + 1.

The gate line Gi, the data lines Dj, Dj + 1 and Dj + 2, the first pixel electrode PEa and the second pixel electrode PEb are formed by patterning a metal layer. The gate line Gi and the data lines Dj, Dj + 1, and Dj + 2 are formed on different layers, and an insulator may exist between them. The first and second pixel electrodes PEa and PEb may be formed in different layers or in the same layer.

In the liquid crystal panel assembly of FIG. 37, all of the first to third data lines Dj, Dj + 1, and Dj + 2 are formed on the same layer.

Each pixel PXn and PXn + 1 includes first and second switching elements Qa and Qb, a liquid crystal capacitor Clc, and first and second storage capacitors Csta and Cstb.

The first switching element Qa of the first pixel PXn is connected to the gate line Gi and the first data line Dj, and the second switching element Qb of the first pixel PXn is the gate line. The first switching element Qa of the second pixel PXn + 1 is connected to the gate Gi and the second data line Dj + 1, and the gate line Gi and the third data line Dj + 2. The second switching element Qb of the second pixel PXn + 1 is connected to the gate line Gi and the second data line Dj + 1. That is, the second switching element Qb of the neighboring first pixel PXn and the second switching element Qb of the second pixel PXn + 1 are the same data line Dj + 1 (hereinafter referred to as shared data line). Is connected to the

The first and second switching elements Qa and Qb are three-terminal elements, such as thin film transistors, provided in the lower panel 100, and control terminals thereof are connected to the gate line (Gi) and input terminals. Is connected to the data lines Dj, Dj + 1 and Dj + 2, and the output terminal is connected to the liquid crystal capacitor Clc and the first and second sustain capacitors Csta and Cstb, respectively.

Referring back to FIG. 2, the liquid crystal layer 3 has dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels 100 and 200 in the absence of an electric field. Can be. Alternatively, the liquid crystal molecules may be aligned such that their major axes are horizontal with respect to the display panels 100 and 200 in the absence of an electric field.

In addition, since the liquid crystal capacitor Clc and the storage capacitors Csta and Cstb have been described above, a detailed description thereof will be omitted.

An operation of the liquid crystal display according to the exemplary embodiment of the present invention will now be described with reference to FIGS. 38 and 39.

38 and 39 illustrate two consecutive frames when the lowest voltage available to the liquid crystal display according to the exemplary embodiment of the present invention is 0V, the highest voltage is 14V, and the common voltage Vcom is 7V. Is a diagram showing charging voltages of liquid crystal capacitors of four neighboring pixels and voltages applied to each data line.

38 and 39, there is one data line Dj + 1 and Dj + 4 between two neighboring pixels, and two pixels PX have these data lines Dj + 1 and Dj + 4. That is, they are commonly connected to the shared data lines Dj + 1 and Dj + 4. The highest driving voltage (for example, 14 V) and the lowest driving voltage (0 V) are alternately applied to the shared data lines Dj + 1 and Dj + 4 for each frame. That is, when 0 V is applied to the shared data lines Dj + 1 and Dj + 4 as shown in FIG. 38 in one frame, the shared data lines Dj + 1 and Dj + as shown in FIG. 39 in the next frame. 14V is applied to 4).

First, referring to FIG. 38, 0V is applied to the shared data lines Dj + 1 and Dj + 4. Since the target charge voltage of the first pixel is 14V, a data voltage of 14V is applied to the first data line Dj. The target charge voltage of the second pixel is 10V, so 10V is applied to the second data line Dj + 2. Since the target charging voltage of the third pixel is 5V, 5V is applied to the third data line Dj + 3, and since the target charging voltage of the fourth pixel is 1V, 1V is applied to the fourth data line Dj + 5. . In this case, neighboring pixels may be inverted by applying voltages having opposite polarities with respect to the voltage applied to the left side, thereby improving display characteristics.

In the next frame, as shown in FIG. 39, the maximum driving voltage of 14V is applied to the shared data lines Dj + 1 and Dj + 4. Since the target charge voltage of the first pixel is 13V, a data voltage of 1V is applied to the first data line Dj, and the target charge voltage of the second pixel is 8V, so 6V is applied to the second data line Dj + 2. Since the target charging voltage of the third pixel is 6V, 8V is applied to the third data line Dj + 3. Since the target charging voltage of the fourth pixel is 3V, 11V is applied to the fourth data line Dj + 5. . Accordingly, voltages of opposite polarities to those of the previous frame are applied to each pixel, and neighboring pixels also receive voltages of opposite polarities to each other.

In the case of the present exemplary embodiment, since shared data lines are disposed between neighboring pixels, the number of data lines may be reduced to increase the aperture ratio of the liquid crystal panel assembly, and the number of data drivers may be reduced to reduce the manufacturing cost of the liquid crystal display.

A liquid crystal panel assembly according to another exemplary embodiment of the present invention will now be described in detail with reference to FIG. 40.

40 is an equivalent circuit diagram of two pixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 40, the liquid crystal panel assembly according to the present exemplary embodiment also includes a signal line including a gate line Gi and adjacent first, second and third data lines Dj, Dj + 1, and Dj + 2. First and second pixels PXn and PXn + 1 connected thereto, and each of the pixels PXn and PXn + 1 includes first and second switching elements Qa and Qb and a liquid crystal capacitor Clc. .

However, in the liquid crystal panel assembly of FIG. 40, unlike the liquid crystal panel assembly of FIG. 37, each pixel PXn and PXn + 1 includes one storage capacitor Cst to separately form a wiring for transferring the common voltage Vcom. Since it is not necessary, the aperture ratio can be increased. The storage capacitor Cst may be formed such that output terminals of the first and second switching elements Qa and Qb overlap each other with an insulator interposed therebetween.

A liquid crystal panel assembly according to another exemplary embodiment of the present invention will now be described with reference to FIGS. 41 and 42 and FIG. 1 described above.

41 and 42 are equivalent circuit diagrams of two pixels of a liquid crystal panel assembly according to various other embodiments of the present invention.

41 and 42, a liquid crystal panel assembly according to the present exemplary embodiments may include a signal line including a gate line Gi and first and second data lines Dj and Dj + 1 adjacent to each other and a first line connected thereto. First and second pixels PXn and PXn + 1 are included, and each pixel PXn and PXn + 1 includes first and second switching elements Qa and Qb and a liquid crystal capacitor Clc.

41 and 42, each pixel PXn and PXn + 1 includes a storage capacitor Cst. However, each of the pixels PXn and PXn + 1 may include first and second storage capacitors (not shown) connected to the first and second switching elements Qa and Qb, respectively.

However, unlike the liquid crystal panel assembly of FIG. 37 or FIG. 42, the liquid crystal panel assembly of FIGS. 41 to 42 does not have a data line formed between each pixel, and is formed in parallel with the gate line Gi. Dk). The shared data line Dk is not formed on the same layer as the other data lines Dj and Dj + 1, but is formed on the same layer as the gate line Gi. The shared data line Dk is not connected to the data driver 500 unlike other data lines Dj and Dj + 1. Therefore, instead of receiving a voltage from the data driver 500, a voltage that varies the highest voltage and the lowest voltage in one frame unit from the outside may be separately applied.

In the liquid crystal panel assembly of FIG. 41, the shared data line Dk is disposed on the same side as the gate line Gi with respect to the pixel PXn, and in the liquid crystal panel assembly of FIG. 42, the shared data line Dk corresponds to the liquid crystal panel assembly of FIG. The pixel PXn is disposed opposite to the gate line Gi.

The liquid crystal panel assembly of FIGS. 41 and 42 may reduce the number of data lines and the data driver 500 more than the liquid crystal panel assembly of FIG. 37 or 40, thereby improving the aperture ratio of the liquid crystal panel assembly and reducing manufacturing costs.

A liquid crystal panel assembly according to another exemplary embodiment of the present invention will now be described in detail with reference to FIGS. 2 and 42.

43 is an equivalent circuit diagram of two pixels of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

2 and 43, the liquid crystal panel assembly according to the present embodiment is mostly the same as the liquid crystal panel assembly illustrated in FIG. 37.

However, each of the pixels PXn and PXn + 1 includes first and second liquid crystal capacitors Clch and Clcl having different capacitances. As shown in FIG. 43, the distance between the two terminals of the first liquid crystal capacitor Clch is greater than that of the second liquid crystal capacitor Clcl. Therefore, even though the same voltage is applied to both ends of the first and second liquid crystal capacitors Clch and Clcl, the intensity of the electric field generated in the liquid crystal layer 3 acting as a dielectric is different and the liquid crystal molecules of the two liquid crystal capacitors Clch and Clcl are different. The degree of inclination is different. Accordingly, by controlling the distance between the terminals of the liquid crystal capacitors Clch and Clcl, the image viewed from the side of the liquid crystal display may be as close as possible to the image viewed from the front, thereby improving side visibility.

The gate line Gi, the data lines Dj, Dj + 1, Dj + 2, the first and second switching elements Qa, Qb, the storage capacitors Csta, Cstb, and the like are shown in FIG. 37. Since it is the same as the description of the embodiment, it will be omitted.

An example of the liquid crystal panel assembly illustrated in FIG. 43 will be described in detail with reference to FIGS. 44 to 47, respectively.

44 to 47 are layout views of two pixels PXn and PXn + 1 of the liquid crystal panel assembly according to the exemplary embodiment of the present invention, respectively.

First, referring to FIG. 44, the planar structure and the layer structure of the liquid crystal panel assembly according to the present exemplary embodiment are generally the same as those of the liquid crystal panel assembly illustrated in FIGS. 21 and 22. Hereinafter, a description will be given focusing on differences from the embodiment shown in FIGS. 21 and 22.

Unlike FIGS. 21 and 22, the liquid crystal panel assembly according to the present exemplary embodiment includes a plurality of shared data lines 172 positioned between the plurality of data lines 171 and the neighboring pixels PXn and PXn + 1. do.

Next, the first and second pixel electrodes 191a and 191b included in each pixel PXn and PXn + 1 will be further described.

The first pixel electrode 191a includes a left vertical portion 192a extending upward and downward, a central horizontal portion 193a extending from the center portion of the left vertical portion 192a to the right, and a plurality of upper and lower branch portions 194a. 195a). The upper branch portion 194a is positioned above the center horizontal portion 193a and extends obliquely upward from the left vertical portion 192a and the central horizontal portion 193a. The lower branch portion 195a is positioned below the center horizontal portion 193a and extends obliquely downward from the left vertical portion 192a and the central horizontal portion 193a. The interval between the upper and lower branch portions 194a and 195a is narrow in the upper and lower portions and the center portion of the pixels PXn and PXn + 1, and is wide in the remaining low gradation region LA.

The second pixel electrode 191b includes a right vertical portion 192b extending upward and downward, upper and lower horizontal portions 193b1 and 193b2 extending from the top and bottom of the right vertical portion 192b to the left, and a plurality of upper and lower portions. Lower branch portions 194b and 195b. The upper branch 194b is positioned at an upper side with respect to the center horizontal portion 193a and extends obliquely to the lower left from the right vertical portion 192b and the upper horizontal portion 193b1, and the lower branch portion 195b is centered. It is positioned below the horizontal portion 193a and extends obliquely upward to the left side from the right vertical portion 192b and the lower horizontal portion 193b2. The spacing between the upper and lower branch portions 194b and 195b is also narrow in the upper and lower portions and the center portion of the pixels PXn and PXn + 1, and wide in the remaining low gradation region LA.

In addition, the branch portions 194a, 194b, 195a, and 195b of the first and second pixel electrodes 191a and 191b are alternately arranged, and the branch portions 194a, 194b, and 195a of the low gray area LA are compared with other regions. , 195b) is wide. The effects thereof are the same as in the other embodiments including FIGS. 21 and 22 and thus will be omitted.

In each of the pixels PXn and PXn + 1, the first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b, respectively. Is together with the first and second semiconductors 154a and 154b to form the first and second thin film transistors Qa and Qb, and the channel of the first and second thin film transistors Qa and Qb is connected to the first and second sources. The first and second semiconductors 154a and 154b are formed between the electrodes 173a and 173b and the first and second drain electrodes 175a and 175b.

Two neighboring pixels PXn and PXn + 1 are connected to the shared data line 172 at right and left sides, respectively. The first pixel electrode 191a of the left pixels PXn and PXn + 1 receives a data voltage from the data line 171 through the first thin film transistor Qa and the second pixel electrode 191b receives a second voltage. The highest driving voltage or the lowest driving voltage is applied from the shared data line 172 through the thin film transistor Qb. In addition, the first pixel electrode 191a of the right pixel PXn + 1 receives the highest driving voltage or the lowest driving voltage from the shared data line 172 through the second thin film transistor Qb and receives the second pixel electrode 191b. The data voltage is applied from the data line 171 through the first thin film transistor Qa.

Next, referring to FIG. 45, the liquid crystal panel assembly according to the present exemplary embodiment is substantially the same as the liquid crystal panel assembly illustrated in FIG. 44, but the distance between the branch portions of the first and second pixel electrodes 191a and 191b is different. The wider, lower gradation region LA has a portion where the distance between the branches of the first and second pixel electrodes 191a and 191b is close.

Next, referring to FIG. 46, the layer structure of the liquid crystal panel assembly according to the present exemplary embodiment is also the same as the layer structure of the liquid crystal panel assembly illustrated in FIG. 24. Hereinafter, a description will be given focusing on differences from the embodiment shown in FIG. 24.

The liquid crystal panel assembly according to the present exemplary embodiment includes a plurality of data lines 171 and a shared data line 172 positioned between the neighboring pixels PXn and PXn + 1.

The first and second pixel electrodes 191a and 191b included in each pixel PXn and PXn + 1 will be further described.

The first pixel electrode 191a extends obliquely upward from the horizontal portion 193a and the horizontal portion 193a positioned at the bottom of each pixel PXn and PXn + 1, and is bent three times to the left and right and connected to the inequality sign ( And a plurality of bent branches 196a forming a shape. The second pixel electrode 191b also has a plurality of curved branches extending obliquely downward from the horizontal portion 193b and the horizontal portion 193b positioned at an upper end thereof, and bent three times from side to side to form an inequality sign (>) connected up and down. Section 196b. The bent branches 196a and 196b of the first and second pixel electrodes 191a and 191b are alternately disposed, and the gap between the bent branches 196a and 196b in the left portion of the pixels PXn and PXn + 1. In the near and right region, the distance between the bent branches 196a and 196b is far. The effects thereof are the same as in the other embodiments including FIGS. 21 and 22 and thus will be omitted.

In addition, descriptions of the data line 171 and the shared data line 172 and the first and second pixel electrodes 191a and 191b are the same as in the above-described embodiment, and thus the description thereof will be omitted.

Next, referring to FIG. 47, the layer structure of the liquid crystal panel assembly according to the present exemplary embodiment is also the same as the layer structure of the liquid crystal panel assembly illustrated in FIG. 25. Hereinafter, description will be given focusing on differences from the embodiment shown in FIG. 25.

The liquid crystal panel assembly according to the present exemplary embodiment also includes a plurality of shared data lines 172 positioned between the plurality of data lines 171 and the neighboring pixels PXn and PXn + 1.

The first and second pixel electrodes 191a and 191b included in each pixel PXn and PXn + 1 will be further described.

The first pixel electrode 191a extends downwardly from the left vertical portion 192a, the upper horizontal portion 193a, and the upper horizontal portion 193a, which are extended downwards and bent three times to the left and right. , A horizontal portion 197a extending from the center of the right vertical curved portion 196a to the right, a vertical portion 198a extending downward from a lower bending point of the right vertical curved portion 196a, and a plurality of diagonal branch portions. The second pixel electrode 191b extends upward from the right vertical portion 192b, the lower horizontal portion 193b, and the lower horizontal portion 193b and is bent three times to the left and right, and the vertical curved portion 196b. The upper horizontal portion 197b extending to the left at the upper bending point of the upper side), the lower horizontal portion 198b extending to the left at the lower bending point of the vertical bending portion 196b, and a plurality of diagonal branches. The diagonal branch portions of the first and second pixel electrodes 191a and 191b may form an angle of about 45 degrees with respect to the gate line 121.

The diagonal branches of the first and second pixel electrodes 191a and 191b are alternately arranged, and the intervals may be constant. The distance between the vertical bends 196a and 196b of the first and second pixel electrodes 191a and 191b is closer than the distance between the diagonal branches of the neighboring first and second pixel electrodes 191a and 191b so that the liquid crystal layer ( Since the tilt angle of the liquid crystal molecules of 3) is larger, the transmittance is also higher. In addition, the descriptions in other embodiments including FIGS. 21 and 22 may be applied.

In addition, the descriptions of the data line 171, the shared data line 172, and the first and second pixel electrodes 191a and 191b are the same as in the above embodiment, and thus the description thereof is omitted.

Thus, in the embodiments shown in FIGS. 44 to 47, the distance between the first pixel electrode 191a and the second pixel electrode 191b in one pixel PXn and PXn + 1 is alternately close to the part farther away. In addition, the intensity of the electric field generated in the liquid crystal layer 3 may be varied, the inclination angle of the liquid crystal molecules 31 may be varied, and the side visibility of the liquid crystal display may be improved and transmittance may be increased.

Alternatively, a plurality of portions having a large gap may be located after a portion having a narrow gap between the first and second pixel electrodes 191a and 191b. Alternatively, a plurality of narrow gaps may be positioned after a wide gap between the first and second pixel electrodes 191a and 191b. In addition, the distance between the first and second pixel electrodes 191a and 191b may be adjusted or the arrangement of the narrow and wide portions may be adjusted to maximize transmittance and improve side visibility.

A liquid crystal panel assembly according to another exemplary embodiment of the present invention will now be described in detail with reference to FIG. 48.

48 is an equivalent circuit diagram illustrating one pixel together with a structure of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Referring to FIG. 48, each pixel PX includes a pair of subpixels, and each subpixel includes liquid crystal capacitors Clch and Clcl and storage capacitors Csth and Cstl. At least one of the two subpixels includes two switching elements (not shown) connected to the gate line, the data line, and the liquid crystal capacitors Clch and Clcl.

The liquid crystal capacitor Clch / Clcl has two terminals of the first subpixel electrode PEha / PEla and the second subpixel electrode PEhb / PElb of the lower panel 100 and the first subpixel electrode PEha / PEla. And the liquid crystal layer 3 between the second subpixel electrode PEhb / PElb function as a dielectric. Each of the second subpixel electrodes PEhb and PElb may be connected to a separate switching element (not shown), and at least one of the first subpixel electrodes PEha and PEla may be a separate switching element (not shown). Connected with Alternatively, the second subpixel electrodes PEhb and PElb may not be separated from each other but may be connected to one switching element (not shown) as one electrode. However, in some cases, the second subpixel electrodes PEhb and PElb may be provided in the upper panel 200. In this case, the second subpixel electrodes PEhb and PElb are not connected to the switching element and have a separate common voltage ( Vcom) can be authorized. Meanwhile, the liquid crystal molecules of the liquid crystal layer 3 may have a dielectric anisotropy and may be aligned perpendicular to the display panels 100 and 200. Alternatively, the liquid crystal molecules may be aligned to be horizontal to the display panels 100 and 200.

In the storage capacitor Csth / Cstl, which serves as a secondary role of the liquid crystal capacitor Clch / Clcl, the first subpixel electrode PEha / PEla and the second subpixel electrode PEhb / PElb of the lower panel 100 are insulators. This is nested with.

In addition, the contents of the color filter CF and the polarizer (not shown) are the same as in the previous embodiment and thus will be omitted.

Next, an example of the liquid crystal panel assembly illustrated in FIG. 48 will be described in detail with reference to FIGS. 49 to 51.

49 to 51 are equivalent circuit diagrams of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention, respectively.

First, referring to FIG. 49, the liquid crystal panel assembly according to the present exemplary embodiment may include a gate line Gi, first and second data lines Dj and Dj + 1 neighboring each other, and shared data neighboring the gate lines Gi. The signal line includes a line Dk and a pixel PX connected thereto.

The pixel PX includes a pair of subpixels PXh and PXl, and each subpixel PXh / PXl is connected to a corresponding gate line Gi and a data line Dj / Dj + 1, respectively. The first and second switching elements Qha, Qhb / Qla, and Qlb, a liquid crystal capacitor Clch / Clcl connected thereto, and first and second sustain capacitors Cstha, Csthb / Cstla, and Cstlb.

The first and second storage capacitors Cstha, Csthb / Cstla, and Cstlb may be formed by separately providing electrodes with the insulator interposed between the first and second pixel electrodes PEha, PEhb / PEla, and PElb.

Alternatively, each subpixel PXh / PXl may include one sustain capacitor Csth / Cstl.

The first switching element Qha of the first subpixel PXh is connected to the gate line Gi and the first data line Dj, and the second switching element Qhb of the first subpixel PXh is It is connected to the gate line Gi and the shared data line Dk, and the first switching element Qla of the second subpixel PXl is connected to the gate line Gi and the second data line Dj + 1. The second switching element Qlb of the second subpixel PXl is connected to the gate line Gi and the shared data line Dk. That is, neighboring switching elements Qhb and Qlb are connected to the same data line Dk. Since the description of the shared data line Dk has been made above, the detailed description thereof will be omitted.

Since the description of the first and second switching elements Qha and Qlb has been described above, the detailed description thereof will be omitted.

In the liquid crystal display including the liquid crystal panel assembly, the signal controller 600 receives the input image signals R, G, and B for one pixel PX and outputs the two subpixels PXh and PXl. The image signal may be converted into a DAT and transmitted to the data driver 500. Alternatively, the gray voltage generator 800 separately sets the gray voltage sets for the two sub-pixels PXh and PXl and alternately provides them to the data driver 500 or alternately selects them in the data driver 500. Different voltages may be applied to the subpixels PXh and PXl. However, at this time, it is preferable to correct the image signal or to create a set of gradation voltages such that the composite gamma curve of the two subpixels PXh and PXl is close to the reference gamma curve at the front. For example, the composite gamma curve at the front side matches the reference gamma curve at the front side determined to be most suitable for this liquid crystal panel assembly, and the composite gamma curve at the side side is closest to the reference gamma curve at the front side.

Next, referring to FIG. 50, the liquid crystal panel assembly according to the present exemplary embodiment includes shared data neighboring the first and second gate lines Gi and Gi + 1, the data line Dj, and the gate line Gi, which are adjacent to each other. The signal line includes a line Dk and a pixel PX connected thereto. The pixel PX includes a pair of subpixels PXh and PXl, and each of the subpixels PXh / PXl includes switching elements Qha, Qhb / Qla and Qlb and liquid crystal capacitors Clch / Clcl connected thereto, And first and second sustain capacitors Cstha, Csthb / Cstla, and Cstlb.

In the liquid crystal panel assembly of FIG. 50, unlike the liquid crystal panel assembly of FIG. 49, two subpixels are adjacent to each other in a column direction and are connected to different gate lines Gi and Gi + 1.

That is, the first switching element Qha of the first subpixel PXh is connected to the first gate line Gi and the data line Dj and the second switching element Qhb of the first subpixel PXh. ) Is connected to the first gate line Gi and the shared data line Dk, and the first switching element Qla of the second subpixel PXl has a second gate line Gi + 1 and a data line The second switching element Qlb of the second subpixel PXl is connected to the second gate line Gi + 1 and the shared data line Dk. That is, the first and second switching elements Qha, Qla / Qhb, and Qlb of each subpixel PXh and PXl are connected to the same data line Dj / Dk.

The operation of the liquid crystal display including the liquid crystal capacitors Clch and Clcl and the first and second storage capacitors Cstha, Csthb / Cstla, and Cstlb, and the liquid crystal panel assembly as described above is substantially the same as in the foregoing embodiment. Description is omitted. However, in the liquid crystal display shown in FIG. 49, while the two subpixels PXh and PXl constituting one pixel PX receive a data voltage at the same time, in the present embodiment, the two subpixels PXh and PXl) Receives a data voltage with a time difference.

Next, referring to FIG. 51, a liquid crystal panel assembly according to the present exemplary embodiment includes a signal line including a gate line Gi and neighboring first to third data lines Dj, Dj + 1, and Dj + 2, and connected thereto. The pixel PX is included.

The pixel PX includes a pair of subpixels PXh and PXl, and each subpixel PXh / PXl is connected to a corresponding gate line Gi and a data line Dj / Dj + 2, respectively. A second switching element Qhb / Qlb connected to the first switching element Qha / Qla, the gate line Gi and the shared data line Dj + 1, and a liquid crystal capacitor Clch / Clcl connected thereto; First and second holding capacitors (Cstha, Csthb / Cstla, Cstlb).

The liquid crystal panel assembly according to the present exemplary embodiment is almost the same as the liquid crystal panel assembly illustrated in FIG. 49, but the shared data line Dj + 1 is not formed horizontally with the gate line Gi, and the subpixels PXh and PXl are not. It is formed in between. The shared data line Dj + 1 is formed on the same layer as the other data lines Dj and Dj + 2 and connected to the data driver 500 to receive a voltage.

Next, another example of the liquid crystal panel assembly illustrated in FIG. 48 will be described in detail with reference to FIGS. 52 to 58.

52 to 58 are equivalent circuit diagrams for two pixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention, respectively.

First, referring to FIG. 52, the liquid crystal panel assembly according to the present exemplary embodiment may include first and second gate lines Gi and Gi + 1 and first, second and third data lines Dj, Dj + 1 and Dj +. A signal line including 2) and two pixels PXn and PXn + 1 connected thereto; each pixel PXn and PXn + 1 includes a pair of subpixels PXh and PXl, and each subpixel PXh / PXl includes switching elements Qha, Qhb / Qla, and Qlb, a liquid crystal capacitor Clch / Clcl connected thereto, and first and second sustain capacitors Cstha, Csthb / Cstla, and Cstlb.

Unlike the liquid crystal panel assembly of FIG. 49, in the liquid crystal panel assembly of FIG. 49, the switching elements Qhb and Qlb adjacent in the row direction are common to the second data line Dj + 1, that is, the shared data line Dj + 1. It is connected. That is, the second switching element Qhb of the first subpixel PXh of the first pixel PXn, the second switching element Qhb of the first subpixel PXh of the second pixel PXn + 1, and the first The second switching element Qlb of the second subpixel PXl of one pixel PXn and the second switching element Qlb of the second subpixel PXl of second pixel PXn + 1 are both shared data. It is connected to the line Dj + 1.

In addition, unlike the liquid crystal panel assembly of FIG. 51, in the liquid crystal panel assembly of FIG. 51, two subpixels PXh and PXl constituting one pixel PXn / PXn + 1 are adjacent to each other in a column direction, and different gate lines Gi and Gi + are different from each other. Connected to 1). Detailed description thereof is substantially the same as the embodiment of FIG. 50, and thus detailed description thereof will be omitted.

Next, referring to FIG. 53, a liquid crystal panel assembly according to the present embodiment is connected to a signal line including a gate line Gi and adjacent first to third data lines Dj, Dj + 1, and Dj + 2. It includes two pixels PXn and PXn + 1.

Description of each pixel PXn and PXn + 1 is the same as the description of the liquid crystal panel assembly illustrated in FIG.

However, in the present exemplary embodiment, the second switching element Qb of two neighboring pixels PXn and PXn + 1 is connected to the gate line Gi and the shared data line Dj + 1.

In the liquid crystal panel assembly according to the present exemplary embodiment, the shared data line Dj + 1 is not formed horizontally with the gate line Gi but is formed between the two pixels PXn and PXn + 1. Since the description of the shared data line Dj + 1 has been made above, a detailed description thereof will be omitted.

Next, referring to FIG. 54, the liquid crystal panel assembly illustrated in FIG. 54 is the same as that of the liquid crystal panel assembly illustrated in FIG. 53. However, in the present exemplary embodiment, the shared data line Dk is disposed between the pixels PXn and PXn + 1. It is not formed but is formed horizontally with the gate line Gi. The shared data line Dk is not formed on the same layer as the other data lines Dj and Dj + 1, but is formed on the same layer as the gate line Gi. The shared data line Dk is not connected to the data driver 500 unlike the other data lines Dj and Dj + 1. Therefore, instead of receiving a voltage from the data driver 500, a voltage that varies the highest voltage and the lowest voltage in one frame unit from the outside may be separately applied.

Next, referring to FIG. 55, a liquid crystal panel assembly according to the present embodiment is connected to a signal line including a gate line Gi and adjacent first to third data lines Dj, Dj + 1, and Dj + 2. It includes two pixels PXn and PXn + 1.

Descriptions of the pixels PXn and PXn + 1 are the same as the descriptions of the liquid crystal panel assembly illustrated in FIG. 29 described above, and thus will be omitted.

However, in the present exemplary embodiment, the second switching elements Qhb and Qlb of two neighboring pixels PXn and PXn + 1 are connected to the gate line Gi and the shared data line Dj + 1.

Since the description of the shared data line Dj + 1 formed between the two pixels PXn and PXn + 1 has been made above, a detailed description thereof will be omitted.

Next, referring to FIG. 56, the liquid crystal panel assembly according to the present exemplary embodiment is substantially the same as the liquid crystal panel assembly illustrated in FIG. 55, but the shared data line Dk is formed between each pixel PXn and PXn + 1. It is not formed and is formed horizontally with the gate line Gi. Next, referring to FIG. 57, the liquid crystal panel assembly according to the present exemplary embodiment may include a gate line Gi, adjacent first to third data lines Dj, Dj + 1, and Dj + 2, and a common voltage line (not shown). Signal line) and two pixels PXn and PXn + 1 connected thereto.

Descriptions of the pixels PXn and PXn + 1 are the same as the descriptions of the liquid crystal panel assembly illustrated in FIG. 36, which will be omitted.

However, in the present exemplary embodiment, the second switching element Qb of two neighboring pixels PXn and PXn + 1 is connected to the gate line Gi and the shared data line Dj + 1.

Next, referring to FIG. 58, the liquid crystal panel assembly according to the present exemplary embodiment is almost the same as the liquid crystal panel assembly illustrated in FIG. 57, but the shared data line Dk is not formed between the pixels PXn and PXn + 1. It is formed horizontally with the gate line Gi.

The driving method shown in FIGS. 38 and 39 may also be applied to the liquid crystal display including the liquid crystal panel assembly illustrated in FIGS. 37 to 57. In addition, the liquid crystal molecules of the liquid crystal layer may have a positive dielectric anisotropy and may be aligned perpendicular to the display panels 100 and 200 in the absence of an electric field. In this case, when an electric field is generated in the liquid crystal layer, the liquid crystal molecules are inclined parallel to the electric field direction to change the polarization state of light. When the liquid crystal molecules having positive dielectric anisotropy are used, the rotational viscosity is lower than that of the liquid crystal molecules having negative dielectric anisotropy, so that a faster response speed can be obtained, and the tilting direction of the liquid crystal molecules 31 is certainly in the direction of the electric field. Because of this definition, even if disturbance occurs in the arrangement of the liquid crystal molecules 31 due to external influences, it can be quickly rearranged to exhibit good display characteristics.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram illustrating a pixel with a structure of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a simplified cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a diagram illustrating a voltage and a pixel applied to a data line of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a diagram illustrating a pixel electrode and a texture portion of a liquid crystal display according to an exemplary embodiment of the present invention.

7 is a simplified cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

8 is a view showing a procedure of a driving method of a liquid crystal display according to an embodiment of the present invention, FIG. 9 is a view showing a driving method according to an embodiment of the present invention, and FIG. Figure is a view showing a driving method according to another embodiment,

FIG. 11 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view of the liquid crystal panel assembly of FIG. 11 taken along the line XII-XII.

13 and 14 are equivalent circuit diagrams illustrating one pixel together with the structure of a liquid crystal panel assembly according to another embodiment of the present invention;

15 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

FIG. 16 is a cross-sectional view of the liquid crystal panel assembly of FIG. 15 taken along a line XVI-XVI.

17 is an equivalent circuit diagram showing one pixel together with the structure of a liquid crystal panel assembly according to an embodiment of the present invention;

18 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

FIG. 19 is a cross-sectional view of the liquid crystal panel assembly of FIG. 18 taken along the line XIX-XIX.

20 is an equivalent circuit diagram showing one pixel together with the structure of a liquid crystal panel assembly according to an embodiment of the present invention;

FIG. 21 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

FIG. 22 is a cross-sectional view of the liquid crystal panel assembly of FIG. 21 taken along the line XXII-XXII.

23 to 25 are layout views of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, respectively.

FIG. 26 is an equivalent circuit diagram illustrating one pixel together with the structure of a liquid crystal panel assembly according to an embodiment of the present invention; FIG.

27 is an equivalent circuit diagram of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

28 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

29 to 34 are equivalent circuit diagrams of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

35 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

36 is an equivalent circuit diagram of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

37 is an equivalent circuit diagram of two pixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

38 and 39 illustrate two consecutive frames when the lowest voltage available to the liquid crystal display according to the exemplary embodiment of the present invention is 0V, the highest voltage is 14V, and the common voltage Vcom is 7V. Is a diagram showing the charging voltages of the liquid crystal capacitors of four neighboring pixels and the voltages applied to the data lines,

40 to 43 are equivalent circuit diagrams for two pixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

44 to 47 are layout views of two pixels PXn and PXn + 1 of the liquid crystal panel assembly according to the exemplary embodiment of the present invention, respectively.

48 is an equivalent circuit diagram illustrating one pixel together with a structure of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

49 to 51 are equivalent circuit diagrams of two subpixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention, respectively.

52 to 58 are equivalent circuit diagrams for two pixels of a liquid crystal panel assembly according to another exemplary embodiment of the present invention, respectively.

Claims (84)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete First and second substrates facing each other, A liquid crystal layer interposed between the first and second substrates and including liquid crystal molecules; A gate line formed on the first substrate and transferring a gate signal, and First, second, and third data lines formed on the first substrate and transferring first, second, and third data voltages, respectively; Including, The first and second substrates and the liquid crystal layer are divided into a plurality of pixels, The first pixel of the plurality of pixels A first switching element connected to the gate line and the first data line, A second switching element connected to the gate line and the second data line, and First and second pixel electrodes connected to the first and second switching elements, respectively, to generate an electric field in the liquid crystal layer. Including, The second pixel of the plurality of pixels A third switching element connected to the gate line and the second data line, A fourth switching element connected to the gate line and the third data line, and Third and fourth pixel electrodes connected to the third and fourth switching elements, respectively, to generate an electric field in the liquid crystal layer. Including; The second data voltage may vary the first level and the second level at regular intervals regardless of the gray level. Liquid crystal display. The method of claim 47, The liquid crystal layer has a positive dielectric anisotropy. The method of claim 48, And the liquid crystal layer is vertically or horizontally aligned. delete The method of claim 47, Wherein the first level is the highest voltage that the liquid crystal display can use, and the second level is the lowest voltage that the liquid crystal display can use. The method of claim 47, And the period is one frame. The method of claim 47, The first to third data lines are formed on the same layer. The method of claim 47, And the second data line is formed on the same layer as the gate line. The method of claim 47, And a storage electrode line formed on the first substrate. The method of claim 47, The first and second pixel electrodes include a plurality of branch electrodes, The branch electrode of the first pixel electrode and the branch electrode of the second pixel electrode are alternately arranged. The method of claim 56, The distance between the branch electrodes of the adjacent first pixel electrode and the branch electrodes of the second pixel electrode varies depending on the position. A pixel comprising a first subpixel and a second subpixel, A gate line formed on the substrate, and First, second, and third data lines formed on the substrate Including, The first subpixel may include a first switching element connected to the gate line and the first data line, a second switching element connected to the gate line and the second data line, and the first and second switching elements. A first liquid crystal capacitor connected thereto, The second subpixel may include a third switching element connected to the gate line and the second data line, a fourth switching element connected to the gate line and the third data line, and the third and fourth switching elements. A second liquid crystal capacitor connected thereto; The first subpixel and the second subpixel receive different data voltages obtained from one piece of image information. The voltage applied to the second data line varies the first level and the second level at regular intervals regardless of the gray level. Liquid crystal display. The method of claim 58, And the first and second liquid crystal capacitors include a liquid crystal layer having positive dielectric anisotropy. The method of claim 59, And the liquid crystal layer is vertically or horizontally aligned. delete The method of claim 58, The first to third data lines are formed on the same layer. The method of claim 58, And the second data line is formed on the same layer as the gate line. The method of claim 58, And a storage electrode line formed on the substrate. A plurality of pixels arranged in a matrix form, each pixel including a first subpixel and a second subpixel; A plurality of first and second gate lines formed on the substrate, and A plurality of first and second data lines formed on the substrate Including, The plurality of pixels includes a first pixel, The first subpixel included in the first pixel may include a first switching element connected to the first gate line and the first data line, and a second switching element connected to the first gate line and the second data line. And a first liquid crystal capacitor connected to the first and second switching elements, The second subpixel included in the first pixel may be a third switching element connected to the second gate line and the first data line, and a fourth switching element connected to the second gate line and the second data line. And a second liquid crystal capacitor connected to the third and fourth switching elements, The first subpixel and the second subpixel included in the first pixel receive different data voltages obtained from one image information. The voltage applied to the second data line varies the first level and the second level at regular intervals. Liquid crystal display. 66. The method of claim 65, And the first and second liquid crystal capacitors include a liquid crystal layer having positive dielectric anisotropy. 67. The method of claim 66, And the liquid crystal layer is vertically or horizontally aligned. delete 66. The method of claim 65, And the second data line is formed on the same layer as the first and second gate lines. 66. The method of claim 65, A plurality of third data lines formed on the substrate; The plurality of pixels further includes a second pixel neighboring the first pixel, The first subpixel of the second pixel is a fifth switching element connected to the first gate line and the third data line, a sixth switching element connected to the first gate line and the second data line, and A third liquid crystal capacitor connected to the fifth and sixth switching elements, The second subpixel of the second pixel is a seventh switching element connected to the second gate line and the third data line, an eighth switching element connected to the second gate line and the second data line, and A fourth liquid crystal capacitor connected to the seventh and eighth switching elements, The first and second subpixels of the second pixel receive different data voltages obtained from one image information. Liquid crystal display. 66. The method of claim 65, And a storage electrode line formed on the substrate. A first pixel and a second pixel, each of which includes a coupling capacitor, a first subpixel, and a second subpixel, and which are adjacent to each other, A gate line formed on the substrate, and First, second, and third data lines formed on the substrate Including, The first subpixel of the first pixel may include a first switching element connected to the gate line and the first data line, a second switching element connected to the gate line and the second data line, and the first and second pixels. A first liquid crystal capacitor connected to the second switching element, The coupling capacitor of the first pixel is connected to the first switching element, The second subpixel of the first pixel includes the second switching element and a second liquid crystal capacitor connected between the coupling capacitor and the second switching element. The first subpixel of the second pixel is a third switching element connected to the gate line and the second data line, a fourth switching element connected to the gate line and the third data line, and the third and the third pixel. A third liquid crystal capacitor connected to the four switching elements, The coupling capacitor of the second pixel is connected to the fourth switching element, The second subpixel of the second pixel includes the third switching element and a fourth liquid crystal capacitor connected between the coupling capacitor and the third switching element, The voltage applied to the second data line varies the first level and the second level at regular intervals. Liquid crystal display. 73. The first to fourth liquid crystal capacitors include a liquid crystal layer having positive dielectric anisotropy. 74. The method of claim 73, And the liquid crystal layer is vertically or horizontally aligned. delete 73. The first to third data lines are formed on the same layer. 73. And the second data line is formed on the same layer as the gate line. delete delete delete delete delete delete delete

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