JP5486850B2 - Display panel, liquid crystal display device including the same, and manufacturing method thereof - Google Patents

Description

  The present invention relates to a display panel, a liquid crystal display device including the display panel, and a method for manufacturing the same.

  The liquid crystal display device is one of the most widely used flat panel display devices at present, and includes two display plates on which electrodes for generating an electromagnetic field such as a pixel electrode and a common electrode are formed, and a space between them. The image is generated by applying a voltage to the electrode that generates the electromagnetic field to generate an electromagnetic field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of the incident light. indicate.

  The liquid crystal display device includes a switching element connected to each pixel electrode and a number of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode.

  Among such liquid crystal display devices, a vertically aligned mode liquid crystal display device in which major axes of liquid crystal molecules are arranged perpendicular to a display plate in a state where no electromagnetic field is applied is a contrast device. It is in the spotlight because of its large ratio and wide reference viewing angle. Here, the reference viewing angle means a viewing angle with a contrast ratio of 1:10 or a luminance inversion limit angle between gradations.

  In the case of such a liquid crystal display device, in order to make the side visibility close to front visibility, the transmittance is obtained by dividing one pixel into two subpixels and applying different voltages to the two subpixels. There has been proposed a method for differentiating.

Republic of Korea Patent Application Publication No. 2007-011984

  In such a method, there is a method of adjusting the voltages of the two sub-pixels using a storage capacitor. Such a method can bring side visibility closer to front visibility, but is visible from the side. The video may not look natural.

  The problem to be solved by the present invention is to bring side visibility closer to front visibility so that the screen display from the side becomes natural.

A display panel according to an embodiment of the present invention is connected to a pixel electrode including a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode that are separated from each other, and the first subpixel electrode. A first thin film transistor, a second thin film transistor connected to the second subpixel electrode, a gate line connected to the first thin film transistor and the second thin film transistor, and the gate line in an electrically insulated state, data lines connected to the first thin film transistor and a second thin film transistor, and is parallel to the gate line is extended across the first sub-pixel electrode, first the voltage Ru is supplied with a period smaller than one frame The first thin film transistor and the second thin film transistor are connected to the gate line. A drain electrode connected to the source line and the first subpixel electrode and the second subpixel electrode, respectively, wherein the drain electrode of the first thin film transistor or the second thin film transistor is the third subpixel. Overlapping with electrodes.

The liquid crystal display according to an embodiment of the present invention includes a first substrate, a gate line formed on the first substrate, and a data line that intersects the gate line in an electrically insulated state. A plurality of pixels each including a sub-pixel electrode, a second sub-pixel electrode, and a third sub-pixel, and a voltage parallel to the gate line and extending across the first sub-pixel electrode and having a period of less than one frame There a first storage electrode line that will be supplied, and a second substrate including a common electrode to apply a reference voltage, and a liquid crystal layer interposed between the first substrate to the second substrate, the first subpixel electrode A first liquid crystal capacitor formed by the common electrode and the liquid crystal layer, a first thin film transistor connected to the first subpixel electrode, and a second thin film transistor connected to the second subpixel electrode, Previous The first thin film transistor and the second thin film transistor include a first sustain electrode line overlapping with the first sub pixel electrode and the second sub pixel electrode, and a second sustain electrode overlapping with the second sub pixel electrode and the third sub pixel electrode. The first thin film transistor and the second thin film transistor are respectively connected to the gate electrode connected to the gate line, the source electrode connected to the data line, the first subpixel electrode, and the second subpixel electrode. The pixel includes a drain capacitor of the first thin film transistor or the second thin film transistor and a coupling capacitor formed to overlap with the third sub-pixel electrode.

  At least one of the first to third subpixel electrodes may include a plurality of slits for promoting movement of liquid crystal molecules.

  The display panel may further include a second storage electrode line extending across the second subpixel electrode or the third subpixel electrode.

  The voltage applied to the first subpixel electrode is higher than the voltage applied to the second subpixel electrode, and the voltage applied to the second subpixel electrode is applied to the third subpixel electrode. Higher than voltage.

  The voltage applied to the first subpixel electrode may be 0.5 to 1.5 V higher than the voltage applied to the second subpixel electrode, and the voltage applied to the second subpixel electrode is The voltage applied to the third subpixel electrode may be 0.1 to 1.0 V higher.

  A method of manufacturing a liquid crystal display according to an embodiment of the present invention includes forming a gate line, a gate electrode, and a first storage electrode line parallel to the gate line, and forming the gate line on the gate line and the first storage electrode line. Forming a gate insulating film; forming a plurality of semiconductor islands on the gate insulating film; forming a protective film including a plurality of contact holes exposing the drain electrode and the gate line; and A pixel electrode including a separated first subpixel electrode, a second subpixel electrode, and a third subpixel electrode, wherein the first subpixel electrode and the second subpixel electrode are each connected to the drain electrode through a contact hole; The first storage electrode line extends across the first subpixel electrode, and at least one of the drain electrodes is overlapped with the third subpixel electrode. .

  Specific matters of other embodiments are included in the detailed description and the drawings.

  According to the present invention, the screen from the side can be recognized as a natural image while making the side visibility close to the front visibility.

1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. 4 is an equivalent circuit for a structure of a liquid crystal display device according to an embodiment of the present invention and three sub-pixels. 1 is an equivalent circuit diagram for one pixel of a liquid crystal display device according to an embodiment of the present invention. 1 is a layout view of a liquid crystal panel assembly according to an embodiment of the present invention. FIG. 5 is a cross-sectional view of the liquid crystal panel assembly shown in FIG. 4 taken along line VV. FIG. 5 is a cross-sectional view of the liquid crystal panel assembly shown in FIG. 4 taken along line VI-VI. FIG. 4 is a signal diagram of three subpixel voltages applied to one pixel of a liquid crystal display device according to an embodiment of the present invention. 5 is a graph illustrating front and side gamma curves of a liquid crystal panel assembly according to another embodiment of the present invention. 3 is a graph illustrating front and side gamma curves of a liquid crystal panel assembly according to an embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily implement the embodiments. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein.

  In the drawings, the thickness is shown enlarged to clearly show the various layers and regions. Similar parts are denoted by the same reference numerals throughout the specification. When a layer, film, region, plate, etc. is “on top” of another part, this includes not only if it is “above” another part, but also if there are other parts in between . When a part that is opposite is “directly above” another part, it means that there is no other part in between.

  A liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is a structure of the liquid crystal display device according to an embodiment of the present invention and an equivalent circuit diagram for three subpixels. These are the equivalent circuit diagrams with respect to 1 pixel of the liquid crystal display device by one Embodiment of this invention.

  As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, a sustain electrode driver 700, and a gray voltage generator. Part 800 and signal control part 600. The gate driver 400 may include a pair of drivers disposed on each side surface of the liquid crystal panel assembly 300.

  As shown in FIG. 1, the liquid crystal panel assembly 300 is connected to a plurality of signal lines (G1-Gn, D1-Dm, SLa1-SL1n) when viewed in an equivalent circuit, and is generally in the form of a matrix. It includes a plurality of pixels (PX1, PX2, and PX3) arranged. On the other hand, when viewed in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes the lower and upper display panels 100 and 200 facing each other, and the liquid crystal layer 3 interposed therebetween.

  The signal lines (G1-Gn, D1-Dm, SLa1-SL1n) are a plurality of gate lines (G1-Gn) that transmit gate signals (referred to as “scanning signals”) and a plurality of data that transmit data voltages (Vd). It includes a line (D1-Dm) and a plurality of storage electrode lines (SLa1-SLan) for transmitting storage electrode signals. The gate lines (G1-Gn) and the storage electrode lines (SLa1-SLan) extend in the horizontal direction in the drawing and are substantially parallel to each other, and the data lines (D1-Dm) extend in the vertical direction in the drawing and It is almost parallel.

  Each pixel (PX1, PX2, and PX3) includes three subpixels, ie, first, second, and third subpixels (PXa, PXb, PXc). Each pixel includes a liquid crystal capacitor (Clca, Clcb and Clcc), and the first and second sub-pixels (PXa and PXb) include switching elements (Qa and Qb) connected to the respective signal lines.

  The first / second / third switching element (Qa / Qb / Qc) is a three-terminal element such as a thin film transistor formed on the lower display panel 100, and its control terminal is connected to the gate line (Gn). The input terminal is connected to the data line (Dm), and the output terminal is connected to the liquid crystal capacitor (Clca or Clcb), the coupling capacitor (Ccp), or the maintenance capacitor (Csta).

  The liquid crystal capacitor (Clca, Clcb or Clcc) is connected to the switching element (Qa, Qb or Qc), and the liquid crystal capacitor (Clca, Clcb or Clcc) is formed on the lower display panel 100 as two terminals. The sub-pixel electrode (PEa, PEb or PEc) and the common electrode 270 of the upper display panel 200, and the liquid crystal layer 3 between the sub-pixel electrode (PEa, PEb or PEc) and the common electrode 270 as a dielectric are formed. . The three subpixel electrodes (PEa, PEb, and PEc) are separated from each other to form one pixel electrode (PE). The common electrode 270 is formed on the entire surface of the upper display panel 200 and receives a common voltage (Vcom). The liquid crystal layer 3 has a negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned so that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electromagnetic field. Sometimes.

  The first subpixel (PXa) also includes a first storage capacitor (Csta) connected to the first switching element (Qa) and the first storage electrode line (SLa). The first sustain capacitor (Csta), which is an auxiliary capacitor for the first liquid crystal capacitor, is formed by overlapping the storage electrode line (SLa) formed on the lower display panel 100 and the first subpixel electrode (PEa) via an insulator. Is done. An alternating voltage that vibrates with a predetermined amplitude is supplied to the signal line.

  The second subpixel (PXb) includes a second switching element (Qb) and may include a second storage capacitor (not shown).

  The third subpixel (PXc) may include a third storage capacitor (not shown) formed by overlapping the second switching element (Qb) and the third subpixel electrode (PEc) via an insulator.

  On the other hand, in order to implement color display, each pixel (PX1, PX2, and PX3) displays one of the primary colors (primary color) uniquely (primary color) or displays primary colors alternately according to time. (Time division) so that a desired hue is recognized by the spatial and temporal sum of these primary colors. Examples of primary colors include three primary colors such as red, green, and blue. FIG. 2 shows that each pixel (PX1, PX2, and PX3) forms a color filter 230 indicating one of the primary colors in the area of the upper display panel 200 as an example of space division. Unlike FIG. 2, the color filter 230 may be formed on or under the sub-pixel electrodes (PEa, PEb, PEc) of the lower display panel 100.

  In this manner, the pixels (PX1, PX2, and PX3) indicating the three primary colors form one dot (DT) that is a basic unit for displaying an image.

  Polarizers (not shown) are formed on the outer surfaces of the display panels 100 and 200, but the polarization axes of the two polarizers can be orthogonal. In the case of a reflective liquid crystal display device, one of the two polarizers 12 and 22 can be omitted. In the case of an orthogonal polarizer, incident light that enters the liquid crystal layer 3 without an electromagnetic field is blocked.

  Referring to FIG. 1, the gate driver 400 is connected to the gate lines G1-Gn of the liquid crystal panel assembly 300, and includes a gate signal (Vg) composed of a combination of a gate-on voltage (Von) and a gate-off voltage (Voff). ) Is applied to the gate lines (G1-Gn).

  The data driver 500 is connected to the data lines (D1-Dm) of the liquid crystal panel assembly 300, selects the grayscale voltage from the grayscale voltage generator 800, and uses this as a data signal for the data line (D1). -Dm). However, when the gray voltage generator 800 does not provide all voltages for all gray levels, but only provides a predetermined number of reference gray voltages, the data driver 500 generates the reference gray voltages. The voltage is divided to generate gradation voltages for the entire gradation, and a data signal is selected.

  The gate driver 400 and the data driver 500 may be directly mounted on the liquid crystal panel assembly 300 in the form of at least one IC chip. In contrast, the gate driver 400 and the data driver 500 are formed on a flexible printed circuit film (FPC) (not shown) in the form of a tape carrier package (TCP) attached to the liquid crystal panel assembly 300. It can also be mounted on a separate printed circuit board (not shown). In another embodiment, the gate driver 400 and the data driver 500 may be formed with the liquid crystal panel assembly 300, signal lines (G1-Gn, D1-Dm) and switching elements.

  The signal controller 600 controls the gate driver 400, the data driver 500, the sustain electrode driver 700, and the like.

  A liquid crystal panel assembly according to an embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6 together with FIGS.

  FIG. 4 is a layout view of a liquid crystal panel assembly according to an embodiment of the present invention. FIGS. 5 and 6 illustrate the liquid crystal panel assembly shown in FIG. 4 along lines VV and VI-VI, respectively. It is sectional drawing cut | disconnected.

  4 to 6, a liquid crystal display according to an exemplary embodiment of the present invention includes a lower display panel 100 and an upper display panel 200 facing each other, and a liquid crystal layer 3 interposed between the two display panels 100 and 200. including.

  First, the lower display panel 100 will be described.

  A plurality of gate lines 121 and a plurality of storage electrode lines are formed on the insulating substrate 110.

  The gate lines 121 are separated from each other and transmit gate signals, and mainly extend in the lateral direction. Each gate line 121 includes a plurality of gate electrodes (124a and 124b) in each pixel. The first and second gate electrodes 124a and 124b extend separately from the gate line 121, but are integrally formed.

  The gate line 121 may be made of aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo) series metal, chromium (Cr), tantalum (Ta), titanium (Ti), or the like. However, these can also be constituted by a multilayer structure including two conductive films (not shown) having different physical properties. Among them, the conductive film is made of a metal having a low specific resistance, such as an aluminum-based metal alloy, a silver-based metal alloy, or a copper-based metal alloy so that signal delay and voltage drop can be reduced. In contrast, other conductive films may be materials having excellent physical, chemical, and electrical contact characteristics with other materials, particularly ITO (indium tin oxide) and IZO (indium zinc oxide), for example, molybdenum-based materials. It is formed from a metal alloy, chromium, tantalum, titanium or the like.

  The side surface of the gate line 121 is inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

  The first storage electrode line 131a is extended across the first sub-pixel (PXa) in the horizontal direction and receives an AC voltage having a predetermined amplitude. The storage electrode line 131a is located between adjacent gate lines and includes at least one storage electrode 137a in the first subpixel PXa. Although not shown in the drawing, another storage electrode line extends across the second subpixel (PXb) or the third subpixel (PXc) in order to maintain the data voltage applied to each subpixel. Can do.

  A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121.

  A plurality of island-shaped semiconductors 154a and 154b made of hydrogenated amorphous silicon (amorphous silicon is abbreviated as a-Si) or polycrystalline silicon (polysilicon) are formed on the gate insulating film 140. Is formed.

  The semiconductors 154a and 154b are located on the first gate electrode and the second gate electrodes 124a and 124b, respectively. The semiconductors 154a and 154b are integrally formed like the first and second gate electrodes 124a and 124b, and can be formed separately according to the form of the first and second gate electrodes 124a and 124b. .

  A plurality of island-shaped resistive contact members 163a and 163b are formed on the semiconductors 154a and 154b. The resistive contact members 163a and 163b may be formed of a material such as n + hydrogenated amorphous silicon doped with an n-type impurity such as phosphorus at a high concentration, and may be formed of silicide. The resistive contact members 163a and 163b are arranged in pairs 163a and 165a on the respective semiconductors 154a and 154b.

  Side surfaces of the semiconductors 154a and 154b and the resistive contact members 163a and 163b are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

  A plurality of data lines 171 and a plurality of first drain electrodes and second drain electrodes 175a and 175b are formed on the resistive contact members 163b and 165b and the gate insulating film 140.

  The data line 171 transmits a data voltage, extends mainly in the vertical direction, and crosses the gate line 121. Each data line 171 includes a source electrode portion 173a, 173b extending toward the gate electrode portion 124a, 124b and a wide end portion 179 for connection to another layer or an external driving circuit. Each of the source electrodes 173a and 173b is bent in a U shape or a W shape, and includes a plurality of first and second source electrodes 173a and 173b connected to each other.

  The first to second drain electrodes 175a and 175b are separated from each other and are also separated from the data line 171. The first or second drain electrodes 175a and 175b are opposed to the first source electrode and the second source electrodes 173a and 173b with the first and second gate electrodes 124a and 124b as the center.

  Each drain electrode 175a, 175b has a wide end on one side and an end on the other side of the bar shape, and the end of the bar shape is surrounded by a U-shape with source electrodes 173a, 173b. It is. In addition, each drain electrode 175a, 175b is extended to be connected to another layer, and includes an extended portion that is not opposed to the first source electrode or the second source electrode 173a, 173b.

  The first gate electrode to second gate electrode 124a and 124b, the first source electrode to second source electrode 173a and 173b, and the first drain electrode to second drain electrode 175a and 175b include a first channel portion to a second channel portion 154a. 154b together with a first thin film transistor to a second thin film transistor (TFT) (Qa, Qb). Each thin film transistor (Qa, Qb) includes a first source electrode to a second source electrode 173a, 173b and a first thin film transistor (Qa, Qb). Channel portions formed between the drain electrode and the second drain electrodes 175a and 175b are included.

  First source electrode to second source electrode 173a, 173b, first gate electrode to second gate electrode 124a, 124b, and first semiconductor forming the first thin film transistor to the second thin film transistor (Qa, Qb) integrally formed The second semiconductors 154a and 154b may be formed separately from each other.

  A passivation layer 180 is formed on the exposed portions of the data line 171, the drain electrodes 175a and 175b, and the semiconductors 154a and 154b. The protective film 180 is made of an inorganic insulator such as silicon nitride and silicon oxide. However, the protective film 180 can be formed of an organic insulator and can have a flat surface. In the case of an organic insulator, it may have photosensitivity, and its dielectric constant may be about 4.0 or less. The protective film 180 may have a double-layer structure of a lower inorganic film and an upper organic film so as not to damage the exposed semiconductors 154a and 154b while taking advantage of the excellent insulating properties of the organic film.

  A contact hole 182 exposing the end 179 of the data line 171 and a plurality of contact holes 185a and 185b exposing the first and second drain electrodes 175a and 175b are formed in the passivation layer 180. Yes. A plurality of contact holes 181 exposing the end portions 129 of the gate lines 121 are formed in the protective film 180 and the gate insulating film 140.

  A plurality of pixel electrodes 191 and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. These may be configured to include a transparent conductor such as ITO or IZO or a reflective metal such as Al, Ag, Cr or an alloy thereof.

  Each pixel electrode 191 includes a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode 191a, 191b, 191c that are separated from each other. Each sub-pixel electrode 191a, 191b, 191c is generally rectangular and is arranged in a line vertically. The first pixel electrode, the second subpixel electrode, and the third subpixel electrode 191a, 191b, and 191c can be divided by a plurality of chevron patterns formed by openings or protrusions, for example. In addition, each subpixel electrode may include a plurality of micro slits (not shown) having a width of 2.5 times or less of a cell gap, which is a distance between the substrates, in order to promote movement of liquid crystal molecules.

  The first subpixel electrode 191a is connected to the first drain electrode 175a through the contact hole 185a, and the second subpixel electrode 191b is connected to the second drain electrode 175b through the contact hole 185b. The third subpixel electrode 191c overlaps with a part of the first drain electrode 175a or the second drain electrode 175b to form a coupling capacitor (Ccp). The coupling capacitor (Ccp) has two terminals, a third subpixel electrode (PEc) and a first drain electrode or second drain electrodes 175a and 175b, and a third subpixel electrode (PEc) and a drain electrode as dielectrics. A protective film 180 located between them is included. The capacitance of the coupling capacitor (Ccp) is adjusted by a region where the sub-pixel electrode 191c and the first drain electrode or the second drain electrodes 175a and 175b overlap.

  Next, the upper display panel 200 will be described with reference to FIGS. 4 and 5.

  A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass or plastic. The light blocking member 220 is also called a black matrix and prevents light leakage. The light blocking member 220 includes a linear portion corresponding to the data line 171 and the gate line 121 and a planar portion corresponding to the thin film transistor, and prevents light leakage between the pixel electrodes 191.

  A plurality of color filters 230 are also formed on the substrate 210. The color filter 230 is almost present in the region covered with the light shielding member 220, and can be extended in the vertical direction of the drawing along the pixel electrode 191 column. Each color filter 230 may display one of primary colors such as the three primary colors red, green, and blue.

  An overcoat film 250 is formed on the color filter 230 and the light blocking member 220. The overcoat film 250 may include an (organic) insulator and prevent the flat color filter 230 from being exposed. The overcoat film 250 may be omitted.

  Meanwhile, the light blocking member 220 or the color filter 230 may be formed on the lower substrate 100.

  A common electrode 270 is formed on the overcoat film 250 so that a reference voltage is applied to the liquid crystal panel assembly 300. The common electrode 270 may include a transparent conductor such as ITO or IZO. In addition, the common electrode 270 may be divided by a plurality of chevron patterns formed by openings or protrusions parallel to the sub-pixel electrode chevron pattern. Further, the common electrode 270 may include a plurality of slits (not shown) having a width of 2.5 times or less of the cell gap in order to promote the movement of liquid crystal molecules.

  Alignment layers 11 and 21 are formed on the inner side surfaces of the display panels 100 and 200, which can be vertical alignment films.

  Polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, but the polarization axes of the two polarizers 12 and 22 are orthogonal to each other, and one of the polarization axes is relative to the gate line 121. It is preferable that they are parallel. In the case of a reflective liquid crystal display device, one of the two polarizers 12 and 22 can be omitted.

  The liquid crystal display device may further include at least one retardation plate (not shown) for compensating for the phase delay of the liquid crystal layer 3. The retardation plate has birefringence and causes a phase delay opposite to the liquid crystal layer 3. The retardation plate includes a uniaxial or biaxial optical compensation film, and may particularly include a negative uniaxial compensation film.

  The liquid crystal display device may include polarizers 12 and 22, phase difference plates, display plates 100 and 200, and a backlight unit (not shown) that supplies light to the liquid crystal layer 3.

  The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned so that the major axis thereof is perpendicular to the surfaces of the two display panels in the absence of an electromagnetic field.

  The operation of such a liquid crystal display device will be described in detail with reference to FIG. 8 and the above-described FIGS.

  First, referring to FIG. 1, the signal controller 600 receives an input video signal (R, G, B) and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input video signal (R, G, B) includes luminance information of each pixel (PX), and the luminance is a predetermined number, for example, 1024 (= 210), 256 (= 28) or 64 (= 26). There are gray levels. Examples of the input control signal include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a main clock signal (MCLK), and a data enable signal (DE).

  The signal control unit 600 appropriately processes the input video signal (R, G, B) according to the operating condition of the liquid crystal panel assembly 300 based on the input video signal (R, G, B) and the input control signal. Then, after generating the gate control signal (CONT1), the data control signal (CONT2), the sustain electrode control signal (CONT3), etc., the gate control signal (CONT1) is sent to the gate driver 400, and the data control signal (CONT2) The processed video signal (DAT) is sent to the data driver 500, and the sustain electrode control signal (CONT3) is sent to the sustain electrode driver 700.

  In response to the input video signal (R, G, B), the signal control unit 600 processes the input video signal (R, G, B) and sends the output video signal (DAT) to the data driver 500. The output video signal (DAT) is a digital signal and has a predetermined number of values (or gradations).

  In order to drive one row of pixels (PX) according to the data control signal (CONT2), the data driver 500 receives the output video signal (DAT), and the gradation voltage generator 800 converts each output video signal (DAT) to an analog level. The voltage is converted into a regulated voltage, and the analog gradation voltage is applied to the corresponding data line (D1-Dm).

  First, referring to FIGS. 1, 3 and 4, the gate driver applies a gate-on voltage (Von) to one of the gate lines (G1-Gn) according to the gate control signal (CONT1). The switching elements (Qa, Qb) connected to the line are turned on. Then, the data voltage (Vd) applied to the data line (DL) is transmitted to the first and second subpixel electrodes 191a and 191b through the contact holes 185a and 185b. Accordingly, the data voltage is applied to the first liquid crystal capacitor, the second liquid crystal capacitor (Clca, Clcb), and the first sustain capacitor (Csta).

  Next, the third subpixel electrode 191c is charged with the coupling voltage (Vc) because the data low voltage (Vd) is applied to the drain electrode (175a or 175c) overlapping therewith. The coupling voltage (Vc) can be expressed as follows.

Vc = (ClccVcom + CcpVd) / (Clcc + Ccp)
Accordingly, the coupling voltage (Vc) is applied to the third liquid crystal capacitor (Clcc) and the coupling capacitor (Ccp).

  As shown in FIG. 7, the first and second thin film transistors (Qa, Qb) are applied to the first, second and third liquid crystal capacitors until they are turned off by the gate-off voltage (Voff) applied to the gate line 121n. Each subpixel electrode voltage (Pa, Pb and Pc) increases to a predetermined level. When the first thin film transistor and the second thin film transistor (Qa, Qb) are turned off, the first subpixel electrode, the second subpixel electrode, and the third subpixel electrode 191a, 191b, 191c are in a floating state, and the drain electrodes 175a, 175b The parasitic capacitance between the gate line 121n and the subpixel electrode voltages Pa, Pb, and Pc always causes a negative voltage shift regardless of the polarity, that is, the kickback voltage drops (Vkb).

  Further, a voltage is applied to the first storage electrode line (SLa) in response to the maintenance control signal (CON3), and the first subpixel electrode voltage (Pa) changes to a high level of both polarities. The polarity of the voltage applied to the first storage electrode line (SLa) can change at a period of less than one frame time, for example, 16.7 ms.

  As shown in FIG. 7, the first subpixel electrode voltage (Pa) increases by ΔPa in proportion to the voltage change of the first storage electrode line (SLa). The second subpixel electrode voltage and the third subpixel electrode voltage (Pb, Pc) maintain their levels regardless of the voltage change of the first sustain electrode line (SLa).

  Accordingly, the first subpixel voltage, the second subpixel voltage, and the third subpixel voltage with respect to the common voltage (Vcom) are Vpa1, Vpa2, and Vpa3, respectively. The absolute value of the subpixel voltage is Vpa1> Vpb1> Vpc1. These sub-pixel voltages maintain their voltage levels for one frame.

  As described above, when a potential difference is generated between both ends of the first to third liquid crystal capacitors (Clca, Clcb, Clcc), a main electromagnetic field (primary electric field) substantially perpendicular to the surfaces of the display panels 100 and 200 is generated in the liquid crystal layer 3. Generated. Then, the liquid crystal molecules of the liquid crystal layer 3 are tilted so that the major axis is perpendicular to the direction of the electromagnetic field in response to the electromagnetic field, and the degree of change in polarization of incident light changes in the liquid crystal layer 3 depending on the degree of tilt of the liquid crystal molecules. . Such a change in polarization appears as a change in transmittance due to the polarizer, whereby the liquid crystal display device displays an image.

  The angle at which the liquid crystal molecules are tilted varies depending on the strength of the electromagnetic field, but the voltages of the three liquid crystal capacitors (Clca, Clcb, Clcb) are different from each other. Different. Therefore, if the voltages of the three liquid crystal capacitors (Clca, Clcb, Clcb) are appropriately matched, the image viewed from the side can be brought as close as possible to the image seen from the front, that is, the side gamma curve can be brought as close as possible to the front gamma curve. In this way, side visibility can be improved.

  In response to the gate control signal, the gate driver uses one horizontal cycle (also referred to as “1H”, which is the same as one cycle of the horizontal synchronization signal (Hsync) and the data enable signal (DE)) as a unit. A gate-on voltage (Von) is sequentially supplied to apply a data voltage (Vd) to all the pixels (PX), and the liquid crystal panel assembly displays one frame image.

  When one frame is finished, the next frame is started and applied to the data driver 500 so that the polarity of the data voltage (Vd) applied to each pixel (PX) is opposite to that of the previous frame. The state of the inversion control signal (RVS) is controlled (“frame inversion”).

  That is, referring to FIG. 7, the polarity of the data voltage applied to each pixel in the next frame is reversed by the data driver 500 that supplies the inversion control signal, and the same process as in the previous frame is repeated, thereby The voltage of the pixel electrode 191a is Vpa2, the voltage of the second subpixel electrode 191b is Vpb2, the voltage of the third subpixel electrode 191c is Vpc2, and the absolute value of the subpixel electrode voltage is Vpa2> Vpb2> Vpc2. .

  On the other hand, even within one frame, the polarity of the data voltage (Vd) flowing through one data line can be changed according to the characteristics of the inversion signal (RVS) (eg, row inversion, point inversion) and applied to a group of pixels. The polarities of the data voltage (Vd) can be changed with each other (eg, column inversion, point inversion).

  A liquid crystal panel assembly according to another embodiment of the present invention will be described in detail with reference to FIGS.

  FIG. 8 is a graph illustrating front and side gamma curves of a liquid crystal panel assembly according to another embodiment of the present invention. FIG. 9 is a graph illustrating front and side gamma curves of a liquid crystal panel assembly according to an embodiment of the present invention.

  A prior art liquid crystal panel assembly includes a plurality of pixels having two sub-pixels separated from each other. In FIG. 8, the visibility index is 0.250, which is generally better than the visibility index when the pixel electrode is not divided. Here, the visibility index is a numerical value obtained by quantifying the difference between the overall luminance contrast and the side luminance contrast. However, an inflection point at which the gamma curve suddenly changes occurs at the A portion of the side gamma curve, and the curve becomes convex at the B portion. Thus, when the side gamma curve does not change slowly, the hue or luminance change is not natural on the side of the liquid crystal display device, and a phenomenon of abrupt change occurs, and the screen is not visually recognized naturally.

  Such a phenomenon occurs because the liquid crystal molecules suddenly move when a sub-pixel having a relatively low voltage among the two sub-pixels starts to contribute to the overall voltage at a certain gradation or higher.

  Meanwhile, the visibility index of the liquid crystal panel assembly according to an embodiment of the present invention is 0.204, which is superior to the prior art. As shown in FIG. 9, it can be seen that the side face gamma curve of the liquid crystal panel assembly according to the present invention is expressed relatively slowly without the inflection point phenomenon and the convex phenomenon. Therefore, when a sub-pixel having a relatively low voltage starts to contribute to the entire pixel voltage at a certain gradation or more, even if the corresponding liquid crystal molecule moves suddenly, it is distributed to the two parts, thus reducing the influence. Let the side gamma curve be slow.

  In the case of the liquid crystal display device shown in FIG. 3, in order to secure a sufficient visibility index while preventing the phenomenon of convexity of the side gamma curve and the inflection point phenomenon, the first sub-gamma curve is used. The pixel electrode voltage (Vpa1) is 0.5V to 1.5V higher than the third subpixel electrode voltage (Vpc1) with respect to the common voltage (Vcom), and the second subpixel electrode voltage (Vpb1) is equal to the common voltage (Vcom). ) Is preferably 0.1V to 1.0V higher than the third subpixel electrode voltage (Vpc1). According to the present invention, it is possible to improve the defect of the screen generated on the side surface of the liquid crystal display device while maintaining the visibility index excellent as compared with the case where the pixel electrode is divided into two.

  The preferred embodiments of the present invention have been described in detail above. However, the scope of the present invention is not limited to these, and various modifications by those skilled in the art using the basic concept of the present invention defined in the following claims. Variations and improvements are also within the scope of the present invention.

  The display panel of the present invention, a liquid crystal display device including the display panel, and a method for manufacturing the same are in the field of flat panel display devices, which are explosively increasing due to excellent screen contrast ratio and improved side visibility. It will be a very useful technique.

300 Liquid crystal display panel assembly 400 Gate driver 500 Data driver 600 Signal controller 700 Sustain electrode driver 800 Gray voltage generator

Claims (11)

A pixel electrode including a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode that are separated from each other;
A first thin film transistor connected to the first subpixel electrode;
A second thin film transistor connected to the second subpixel electrode;
A gate line connected to the first thin film transistor and the second thin film transistor;
A data line intersecting the gate line in an electrically insulated state and connected to the first thin film transistor and the second thin film transistor;
The parallel with the gate lines, are extended across the first sub-pixel electrode, a first storage electrode line line to which the voltage Ru is supplied with a period smaller than one frame,
The first thin film transistor and the second thin film transistor are connected to the gate electrode connected to the gate line, the source electrode connected to the data line, and the first sub-pixel electrode and the second sub-pixel electrode, respectively. A display panel including a drain electrode, wherein the drain electrode of the first thin film transistor or the second thin film transistor overlaps the third subpixel electrode.   The display panel of claim 1, wherein at least one of the first to third subpixel electrodes includes a plurality of slits for promoting movement of liquid crystal molecules.   The display panel of claim 1, further comprising a second storage electrode line extending across the second subpixel electrode or the third subpixel electrode.   The voltage applied to the first subpixel electrode is higher than the voltage applied to the second subpixel electrode, and the voltage applied to the second subpixel electrode is applied to the third subpixel electrode. The display panel according to claim 1, which is higher than a voltage. The voltage applied to the first subpixel electrode is 0.5 to 1.5 V higher than the voltage applied to the second subpixel electrode, and the voltage applied to the second subpixel electrode is the third voltage. The display panel according to claim 4 , wherein the voltage is 0.1 to 1.0 V higher than the voltage applied to the subpixel electrode. A first substrate;
A gate line formed on the first substrate;
A data line that intersects the gate line in an electrically insulated state; and
A plurality of pixels each including a first subpixel electrode, a second subpixel electrode, and a third subpixel that are separated from each other;
Parallel to the gate line is extended across the first sub-pixel electrode, a first storage electrode line voltage having a period smaller than one frame Ru is supplied,
A second substrate including a common electrode to apply a reference voltage;
A liquid crystal layer interposed on the first substrate and the second substrate;
A first liquid crystal capacitor formed by the first subpixel electrode, the common electrode and the liquid crystal layer;
A first thin film transistor connected to the first subpixel electrode;
A second thin film transistor connected to the second subpixel electrode;
Including
The first thin film transistor and the second thin film transistor include a first sustain electrode line overlapping the first sub pixel electrode and the second sub pixel electrode, and a second sustain electrode overlapping the second sub pixel electrode and the third sub pixel electrode. The first thin film transistor and the second thin film transistor are respectively connected to the gate electrode connected to the gate line, the source electrode connected to the data line, the first subpixel electrode, and the second subpixel electrode. A liquid crystal display device including: a drain electrode connected; and the pixel including a drain electrode of the first thin film transistor or the second thin film transistor and a coupling capacitor formed to overlap the third sub pixel electrode. The liquid crystal display device according to claim 6 , wherein at least one of the first subpixel electrode to the third subpixel electrode and the common electrode includes a plurality of slits for promoting movement of liquid crystal molecules. The liquid crystal display of claim 6 , further comprising a second storage electrode line extending across the second subpixel electrode or the third subpixel electrode. The voltage applied to the first subpixel electrode is higher than the voltage applied to the second subpixel electrode, and the voltage applied to the second subpixel electrode is applied to the third subpixel electrode. The liquid crystal display device according to claim 6 , wherein the liquid crystal display device is higher than the voltage. The voltage applied to the first subpixel electrode is 0.5 to 1.5 V higher than the voltage applied to the second subpixel electrode, and the voltage applied to the second subpixel electrode is the third voltage. The liquid crystal display device according to claim 9, which is 0.1 to 1.0 V higher than a voltage applied to the subpixel electrode. A light shielding member including a linear portion corresponding to the data line and the gate line in order to prevent light leakage between the pixels on the first substrate or the second substrate;
A plurality of color filters arranged in a region covered with the light shielding member on the first substrate or the second substrate;
The liquid crystal display device according to claim 9 , comprising:

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