KR20070101549A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display apparatus is provided to select tilt directions of liquid crystal particles by a cutting part and a projecting part and disperse a tilt direction of the liquid crystal particles by accurately installing the selected tilt directions, thereby improving side visibility and increasing an aperture ratio and transmittance. A liquid crystal display apparatus comprises the following parts: a circuit board; first and second sustain electrode lines which are formed on the circuit board; and a plurality of pixel electrodes, which is formed in the circuit board, including first and second sub-pixel electrodes. The pixel electrode(191a,191b) has a first surrounding part and a second surrounding part and is connected to the first surrounding part. The second surrounding part of the pixel electrode includes a saw tooth-shaped projecting part.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a connection relationship of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

4 is a layout view of a first pixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

5, 6, and 7 are cross-sectional views of the liquid crystal panel assembly shown in FIG. 4 taken along the lines V-V, VI-VI, and VIII-VIII.

8 is a layout view illustrating a pixel electrode and a common electrode of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

9 is a layout view of a second pixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

10 is a graph illustrating a gamma curve of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 11 is a graph illustrating a luminance change rate when the voltage of the first subpixel electrode of the liquid crystal display according to the exemplary embodiment is changed. FIG.

FIG. 12 is a graph illustrating a luminance change rate when the second subpixel electrode voltage of the liquid crystal display according to the exemplary embodiment is changed. FIG.

13 is a schematic diagram showing sustain voltage lines of a liquid crystal display according to an embodiment of the present invention.

14 is a waveform diagram illustrating pixel voltages along with other voltages when inverting a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 15 is a waveform diagram illustrating pixel voltages along with other voltages when inverting a liquid crystal display according to another exemplary embodiment of the present invention; FIG.

16 is a diagram illustrating polarities of respective pixels when spot driving of a liquid crystal display according to another exemplary embodiment of the present invention is performed.

FIG. 17 is a waveform diagram of a voltage during inversion driving shown in FIG. 16; FIG.

FIG. 18 is a waveform diagram showing pixel voltages along with other voltages in the inversion driving shown in FIG. 16; FIG.

<Description of Drawing>

12, 22: polarizing plates 11, 21: alignment film

71, 72, 73a, 73a, 74a, 74b, 75a, 75b: common electrode incision

81, 81a, 81b, 82: contact auxiliary member

91a, 91b, 92a, 92b, 93: pixel electrode cutout

94: gap 110, 210: substrate

121 and 129: gate line 124: gate electrode

131: sustain electrode line 137: sustain electrode

140: gate insulating film 151, 154: semiconductor

161, 163a, 165a, 163b, and 165b: ohmic contact members

171 and 179: data lines 173a and 173b: source electrode

175a and 175b: drain electrode 180: protective film

181, 182, 185a, 185b: contact hole

191, 191a, and 191b: pixel electrodes

220: light blocking member 230: color filter

250: overcoat 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

800: gray voltage generator

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the flat panel display devices most widely used. The liquid crystal display includes two display panels on which field generating electrodes, such as a pixel electrode and a common electrode, are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light to display an image.

Among such liquid crystal displays, a liquid crystal display having a vertically aligned mode in which the long axis of the liquid crystal molecules is perpendicular to the display panel without an electric field applied to the liquid crystal display is attracting attention due to its high contrast ratio and wide reference viewing angle.

Specific methods for implementing a wide reference viewing angle in a vertical alignment liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the cutout and the protrusion determine the tilt direction of the liquid crystal molecules, the reference viewing angle can be widened by appropriately arranging them to disperse the inclined directions of the liquid crystal molecules in various directions.

However, in a liquid crystal display device in which the pixel electrode is in a rectangular shape parallel to the gate line and the data line, an array of liquid crystal molecules is disturbed due to an electric field generated between adjacent pixel electrodes, thereby resulting in a texture, thereby reducing transmittance.

The technical problem to be achieved by the present invention is to increase the aperture ratio and transmittance, and also to improve side visibility.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a substrate, first and second storage electrode lines formed on the substrate, and the first and second portions. A plurality of pixel electrodes including a pixel electrode, the pixel electrode having a pair of first peripheral sides facing each other and a pair of second peripheral sides connected to the first peripheral sides and facing each other, A second peripheral side of the pixel electrode includes a sawtooth-shaped protrusion, the first subpixel electrode overlaps the first or second storage electrode line, and the second subpixel electrode is the first and second storage. It overlaps with an electrode line.

A first thin film transistor connected to the first subpixel electrode, a second thin film transistor connected to the second subpixel electrode, a gate line connected to the first and second thin film transistors, and the first and second thin film transistors The display device may further include a first data line connected to the second thin film transistor and crossing the gate line.

The first data line may at least partially overlap the second subpixel electrode.

The first data line may not overlap the first subpixel electrode.

The display device may further include a second data line adjacent to the first data line, wherein the second subpixel electrode may overlap the first data line and the second data line at the same time.

An area where the second subpixel electrode overlaps the first data line may be substantially the same as an area where the second subpixel electrode overlaps the second data line.

Polarities of the data voltages applied to the first data line and polarities of the data voltages applied to the second data line may be opposite to each other.

The first and second data lines may be bent at least once.

The first data line may include a first semiconductor overlapping the first data line, substantially the same as the flat shape of the first data line, and a light blocking layer overlapping the first semiconductor line.

The light blocking layer may be made of the same material as the first and second gate lines.

The width of the first semiconductor may be greater than the width of the first data line.

The display device may further include an organic layer formed between the first data line and the pixel electrode.

The storage electrode signal applied to the first storage electrode line and the storage electrode signal applied to the second storage electrode line may be opposite in phase.

The sustain electrode signal applied to the first sustain electrode line and the sustain electrode signal applied to the second sustain electrode line may be alternating voltages that change at intervals of 1H or more.

The first and second thin film transistors may be alternately positioned on the right or left side of the data line in at least one row.

Pixel electrodes adjacent in the column direction may have opposite polarities.

Pixel electrodes adjacent in the row direction may have opposite polarities.

An area of the second subpixel electrode may be larger than an area of the first subpixel electrode.

The voltage of the first subpixel electrode may be different from the voltage of the second subpixel electrode.

An area of the first subpixel electrode may be higher than a voltage of the second subpixel electrode.

The pixel electrode may include a plurality of cutouts that form an oblique angle with the first peripheral portion.

The display device may further include a common electrode facing the pixel electrode, and the common electrode may include a plurality of cutouts formed at an oblique angle with the first peripheral portion.

A liquid crystal display device according to another aspect of the present invention is a liquid crystal display device including a plurality of pixels, wherein each pixel includes first and second liquid crystal capacitors, first terminals connected to the second liquid crystal capacitors, and a first liquid crystal display device. A first storage capacitor having a second terminal to which the first storage electrode signal is applied, a first terminal connected to the second liquid crystal capacitor, and a second storage electrode signal that is opposite in phase to the first storage electrode signal; A third storage capacitor having a second storage capacitor having two terminals, and a first terminal connected to the first liquid crystal capacitor, and a second terminal receiving the first storage electrode signal or the second storage electrode signal. Wherein the first liquid crystal capacitor has a first subpixel electrode, and the second liquid crystal capacitor has a second subpixel electrode which forms a pixel electrode together with the first subpixel electrode, The pixel electrode has a pair of first peripheral sides facing each other and a pair of second peripheral sides connected to the first peripheral side and facing each other, and the second peripheral side of the pixel electrode has a sawtooth-shaped protrusion. It includes.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of two subpixels of the liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a sustain electrode driver 700 connected thereto. ), A gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. In contrast, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”), and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ) and a plurality of pairs of first and second storage electrode lines Su and Sd that transmit the storage electrode signal. The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

The signal line also includes a first sustain electrode line Su for transmitting the first sustain electrode signal and a second sustain electrode line Sd for transmitting the second sustain electrode signal. The phases of the first sustain electrode signal and the second sustain electrode signal are opposite to each other.

Each pixel PX includes first and second subpixels PX1 and PX2, and each of the subpixels PX1 and PX2 includes switching elements Q1 and Q2 and liquid crystal capacitors Clc1 and Clc2. ) And holding capacitors Cst1, Cst2, Cst3. The first subpixel PX1 includes the storage capacitor Cst1, and the second subpixel PX2 includes two storage capacitors Cst2 and Cst3.

The first and second switching elements Q1 and Q2 include a control terminal connected to the gate line G, an input terminal connected to the data line D, and the liquid crystal capacitors Clc1 and Clc2 and the storage capacitor Cst1. , Cst2 and Cst3).

The liquid crystal capacitors Clc1 / Clc2 have two terminals, the subpixel electrodes 191a / 191b of the lower panel 100 and the common electrode 270 of the upper panel 200 as two terminals, and are common with the subpixel electrodes 191a / 191b. The liquid crystal layer 3 between the electrodes 270 functions as a dielectric. The pair of subpixel electrodes 191a and 191b are separated from each other and form one pixel electrode 191. The common electrode 270 is formed on the entire surface of the upper panel 200 and receives a common voltage Vcom. The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

The storage capacitor Cst1 of the first subpixel PX1 is connected to the switching element Q1 and the first storage electrode line Su, and one storage capacitor Cst2 of the second subpixel PX2 is a switching element ( It is connected to Q2) and the first storage electrode line Su, and another storage capacitor Cst3 of the second subpixel PX2 is connected to the switching element Q2 and the second storage electrode line Sd. The holding capacitances of the two storage capacitors Cst2 and Cst3 of the second subpixel PX2 may be the same.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the subpixel electrodes 191a and 191b of the lower panel 100.

Polarizers (not shown) are provided on the outer surfaces of the display panels 100 and 200, and one of the two polarizers may be omitted in the case of a reflective liquid crystal display. The polarization axes of the two polarizers may be orthogonal, and in the case of the orthogonal polarizer, incident light entering the liquid crystal layer 3 having no electric field is blocked.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The storage electrode driver 700 is connected to the first and second storage electrode lines Su and Sd, and receives the pair of storage electrode signals Vcst-u and Vcst-d having opposite phases, respectively. It applies to sustain electrode lines Su and Sd.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be formed together with the signal lines G ₁ -G _n , D ₁ -D _m , Su, Sd and the thin film transistor switching elements Q1 and Q2. It may be integrated at 300. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the arrangement of the liquid crystal panel assembly will be described in detail with reference to FIG. 3.

3 is a diagram illustrating a pixel arrangement of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the data voltage flowing through two data lines (eg, D _j and D _{j + 1} ) connected to a pair of subpixel electrodes PEa and PEb constituting one pixel electrode PE may be used. The polarities are opposite to each other. That is, the polarity of the data voltage flowing through the data line D _j positioned on the left side of the pixel electrode PE is positive polarity (+), and the data flowing through the data line D _{j + 1} located on the right side of the pixel electrode PE. The polarity of the voltage is negative. The polarities of the plurality of data lines D _j , D _{j + 1} , D _{j + 2} , D _{j + 3} , and D _{j + 4} repeat the same polarity once as '+,-, +,-, +' Polarity changes after the operation.

Each first subpixel electrode PEa is connected to the first switching element Qa, and each second subpixel electrode PEb is connected to the second switching element Qb.

The first and second thin film transistors Qa and Qb are connected to the right or the left side based on one data line D _j , D _{j + 1} , D _{j + 2} , D _{j + 3} , and D _{j + 4} . have. That is, when the first and second thin film transistors Qa and Qb are arranged on the right side of the data lines D _j , D _{j + 1} , D _{j + 2} , D _{j + 3} and D _{j + 4} in one row. In the next row, the first and second thin film transistors Qa and Qb are disposed on the left side of the data lines D _j , D _{j + 1} , D _{j + 2} , D _{j + 3} , and D _{j + 4} . In FIG. 3, the positions of the first and second thin film transistors Qa and Qb are changed every other row, but the positions of the first and second thin film transistors Qa and Qb may be changed every other row.

In more detail, the first and second thin film transistors Qa and Qb are disposed on the left side of the pixel electrode PE disposed in the first row. Hereinafter, the pixel PX having such a connection relationship is referred to as a first pixel PXa.

In the pixel electrode PE disposed in the second row, the pixel electrode PE has first and second thin film transistors Qa and Qb disposed on the right side. Hereinafter, the pixel PX having such a connection relationship is referred to as a second pixel PXb.

That is, the row including the first pixel PXa and the row including the second pixel PXb are alternately repeated.

As described above, the polarities of the adjacent data lines D _j , D _{j + 1} , D _{j + 2} , D _{j + 3} , and D _{j + 4} are opposite to each other and adjacent pixel electrodes PE in the row direction or the column direction ) Polarity is opposite to each other.

A liquid crystal panel assembly according to an exemplary embodiment of the present invention will now be described in more detail with reference to FIGS. 4 to 9.

FIG. 4 is a layout view of a first pixel PXa of a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 5, 6, and 7 illustrate the liquid crystal display shown in FIG. 4 through V-V and VI-VI. And a cross-sectional view taken along the line VIII-VIII, and FIG. 8 is a diagram illustrating a pixel electrode and a common electrode of the liquid crystal display shown in FIG. 4.

4 to 7, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 3 interposed between the two display panels 100 and 200. It includes.

First, the lower panel 100 will be described.

A plurality of gate lines 121, a plurality of pairs of first and second storage electrode lines 131u and 131d, and a plurality of light blocking layers on an insulating substrate 110 made of transparent glass or plastic. A plurality of gate conductors including 120 are formed.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction, and is positioned above and below, respectively.

The gate line 121 includes a plurality of gate electrodes 124 protruding upward and a wide end portion 129 for connection with another layer or the gate driver 400. When the gate driver 400 is integrated on the substrate 110, the gate line 121 may extend to be directly connected thereto.

The first and second storage electrode lines 131u and 131d are applied with a predetermined voltage and extend substantially in parallel with the gate line 121 and are adjacent to each other. The first storage electrode line 131u positioned above includes the first and second storage electrodes 137u1 and 137u2 that are alternately arranged and alternately arranged. And third and fourth sustain electrodes 137d1 and 137d2 shown and alternately arranged. The second sustain electrode 137u2 and the fourth sustain electrode 137d2 face each other, and the first sustain electrode 137u1 and the fourth sustain electrode 137d1 are alternately disposed. However, the shape and arrangement of the storage electrode lines 131u and 131d may be modified in various ways.

The light blocking film 120 mainly extends in the vertical direction and includes a plurality of regions 120u and 120d spaced apart from each other. That is, it is divided into various parts so as not to be short-circuited with the gate line 121 and the storage electrode line 131 extending mainly in the horizontal direction.

The gate conductors 120, 121, 131u, and 131d include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, and molybdenum It may be made of molybdenum-based metal such as (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 120, 121, 131u, and 131d may be made of various other metals or conductors.

Side surfaces of the gate conductors 120, 121, 131u, and 131d are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 120, 121, 131u, and 131d.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (hereinafter referred to as a-Si) or polysilicon are formed on the gate insulating layer 140. The linear semiconductor 151 mainly extends in the longitudinal direction and includes a plurality of projections 154 extending toward the gate electrode 124.

A plurality of linear ohmic contacts 161, a first island type ohmic contact 165a, and a second island type ohmic contact 165b are formed on the semiconductors 151 and 154. The ohmic contacts 161, 165a, and 165b may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The linear ohmic contact 161 has a plurality of first protrusions 163a and second protrusions 163b, and the first and second protrusions 163a and 163b and the first and second island-type resistive contact members ( The 165a and 165b are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductors 151 and 154 and the ohmic contacts 161, 165a and 165b are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175a and 175b are disposed on the ohmic contacts 161, 165a and 165b and the gate insulating layer 140. A data conductor is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121 and the storage electrode line 131. Each data line 171 is not in a straight line throughout and is bent at least once.

Each of the data lines 171 may include a plurality of pairs of the first and second source electrodes 173a and 173b extending toward the first and second gate electrodes 124 and the other layer or the data driver 500. It includes a wide end portion 179 for connection. When the data groove 500 is integrated on the substrate 110, the data line 171 may be extended to be directly connected thereto. The first and second source electrodes 173a and 173b are connected to each other.

The first and second drain electrodes 175a and 175b are separated from each other and also separated from the data line 171.

The first and second drain electrodes 175a and 175b face the first and second source electrodes 173a and 173b with respect to the gate electrode 124, and the rod-shaped end portions are bent to the first and second source electrodes. Partly surrounded by (173a / 173b).

The first drain electrode 175a extends substantially in parallel with the data line 171 starting at the rod-shaped end portion and includes an extension having a large area. In addition, the first drain electrode 175a includes an extension part 176a that is bent in the clockwise direction from the extension part and inclinedly extends to the gate line 121 and the data line 171.

The second drain electrode 175b extends at the rod-shaped end portion and includes a wide area extension. In addition, the second drain electrode 175b includes an extension part 176b extending from the extension part.

The gate electrode 124, the first / second source electrode 173a / 173b, and the first / second drain electrode 175a / 175b together with the semiconductor 154 may include a first / second thin film transistor, TFTs Qa / Qb, and the channels of the first and second thin film transistors Qa / Qb are the first and second source electrodes 173a and 173b and the first and second drain electrodes 175a. / 175b) is formed in the semiconductor 154.

The data conductors 171, 175a, and 175b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film. It may have a multilayer structure including (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data conductors 171, 175a, and 175b may be made of various other metals or conductors.

The data conductors 171, 175a, and 175b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161, 165a, and 165b exist only between the semiconductor 154 below and the data conductors 171, 175a, and 175b thereon, and lower the contact resistance therebetween. The semiconductor 154 has portions exposed between the source electrodes 173a and 173b and the drain electrodes 175a and 175b and not covered by the data conductors 171, 175a and 175b.

The linear semiconductor 151, the data conductors 171, 175a, and 175b, and the ohmic contacts 161, 165a, and 165b thereunder, have substantially the same planar shape. However, the width of the linear semiconductor 151 is larger than the width of the data line 171. Therefore, looking at the cross section, both ends protrude from the data line 171 in the width direction of the linear semiconductor 151.

A passivation layer 180 is formed on the data conductors 171, 175a, and 175b and the exposed portion of the semiconductor 154. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. The organic insulator preferably has a dielectric constant of 4.0 or less, and may have photosensitivity. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 154 while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 includes a plurality of contact holes 182, 185a, and 185b respectively exposing the end portion 179 of the data line 171 and one portion of the first and second drain electrodes 175a and 175b, respectively. ) Is formed, and a plurality of contact holes 181 exposing the end portions 129 of the gate line 121 are formed in the passivation layer 180 and the gate insulating layer 140. In addition, the passivation layer 180 is removed at a portion where the sustain electrode 137 and the pixel electrode 191 overlap each other.

A plurality of pixel electrodes 191 and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. They may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver, chromium or an alloy thereof.

Each pixel electrode 191 includes a pair of first and second subpixel electrodes 191a and 191b separated from each other.

The first and second subpixel electrodes 191a and 191b are physically and electrically connected to the first and second drain electrodes 175a and 175b through the contact holes 185a and 185b to form the first and second drain electrodes ( Data voltage is applied from 175a / 175b). Different data voltages, which are set in advance with respect to one input image signal, are applied to the pair of subpixel electrodes 191a and 191b, the size of which is set according to the size and shape of the subpixel electrodes 191a and 191b. Can be. The areas of the subpixel electrodes 191a and 191b may be different from each other. For example, the second subpixel electrode 191b receives a higher voltage than the first subpixel electrode 191a and has a smaller area than the first subpixel electrode 191a.

The first and third storage electrodes 137u1 and 137d1 alternately overlap the first subpixel electrode 191a, and the second and fourth storage electrodes 137u2 and 137d2 simultaneously with the second subpixel electrode 191b. Overlap.

The pixel electrode 191 to which the data voltage is applied is formed between the two electrodes 191 and 270 by generating an electric field together with the common electrode 270 of the common electrode display panel 200 to which the common voltage is applied. The direction of the liquid crystal molecules 31 of the liquid crystal layer 3 is determined. The polarization of light passing through the liquid crystal layer 3 varies according to the direction of the liquid crystal molecules 31 determined as described above. The pixel electrode 191 and the common electrode 270 form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The first subpixel electrode 191a overlaps the first or third storage electrodes 137u1 and 137d1 to form a first storage capacitor Cst1. In addition, the second subpixel electrode 191b overlaps the second storage electrode 137u2 to form a second storage capacitor Cst2, and overlaps the fourth storage electrode 137d2 to form a third storage capacitor Cst3. These holding capacitors Cst1, Cst2, Cst3 enhance the voltage holding capability of the liquid crystal capacitors Clc1, Clc2. In this case, since only the gate insulating layer 140 exists between the pixel electrode 191 and the storage electrode line 131, the distance between the pixel electrode 191 and the storage electrode line 131 is shortened and the voltage holding capability is improved.

Each pixel electrode 191 has a substantially rectangular outer boundary.

The pair of first and second subpixel electrodes 191a and 191b constituting one pixel electrode 191 are engaged with each other with a gap 94 therebetween, and the first subpixel electrode 191a is It is inserted in the center of the second subpixel electrode 191b.

Upper cutouts 91a and 92a, lower cutouts 91b and 92b, and a central cutout 93 are formed in the second subpixel electrode 191a, and the second subpixel electrode 191b includes these cutouts. By 9191-93, it divides into several area | regions. The cutouts 91a-93 are almost inverted symmetric with respect to the sustain electrode line 131.

The lower and upper cutouts 91a-93b extend obliquely from the right side of the pixel electrode 191 to the left side, the upper side, or the lower side. The lower and upper cutouts 91a-93b are positioned at the lower half and the upper half with respect to the storage electrode line 131, respectively. The lower and upper cutouts 91a-93b extend perpendicular to each other at an angle of about 45 ° with respect to the gate line 121.

The central cutout 93 extends along the storage electrode line 131 and has an inlet at the left side.

Referring to FIG. 8, the second subpixel electrode 191b has a pair of first peripheral sides 193 and 194 facing each other and a pair of second peripheral sides 195 and 196 connected thereto. The first peripheral sides 193 and 194 are substantially parallel to the gate line 121, and the second peripheral sides 195 and 196 are formed along the data line 171. The left corner of the pixel electrode 191 is chamfered to form a hypotenuse, and the oblique hypotenuse forms an angle of about 45 ° with respect to the gate line 121.

A plurality of pairs of first line segments 192a and second line segments 192b are repeatedly formed on the second peripheral sides 195 and 196 of the pixel electrode 191. The angle formed by the first line segment 192a, the upper cutouts 91a and 92a, and the gap 94 is smaller than about 45 degrees.

The pixel electrode 191 overlaps the data line 171 with the passivation layer 180 interposed therebetween. One data line 171 overlaps all of the neighboring pixel electrodes 191. The data line 171 is bent several times instead of extending in a straight line to overlap both the magnetic pixel electrode 191 and the magnetic pixel electrode 191 and the neighboring pixel electrode 191 connected through the first thin film transistor. Take form.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portions 179 and 129 of the data line 171 and the gate line 121 and the external device.

The upper panel 200 will now be described.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass, plastic, or the like. The light blocking member 220 is also called a black matrix and prevents light leakage. The light blocking member 220 includes a linear portion (not shown) corresponding to the data line 171 and a planar portion corresponding to the thin film transistor, and prevents light leakage between the pixel electrodes 191 and faces the pixel electrodes 191. An opening area is defined. However, the light blocking member 220 may have a plurality of openings (not shown) facing the pixel electrode 191 and having substantially the same shape as the pixel electrode 191.

A plurality of color filters 230 is also formed on the substrate 210 and the light blocking member 220. The color filter 230 is mostly present in an area surrounded by the light blocking member 230, and may extend long along the column of pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be made of an (organic) insulator, which prevents the color filter 230 from being exposed and provides a flat surface. The overcoat 250 may be omitted.

The common electrode 270 is formed on the overcoat 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO.

The plurality of cutouts 71, 72, 73a, 73b, 74a, and 74b are formed in the common electrode 270.

One set of cutouts 71 to 74b faces the first pixel electrode 191 and faces the first and second center cutouts 71 and 72, the upper cutouts 73a and 74a, and the lower cutouts 73b, respectively. 74b). Each of the cutouts 71 to 74b is disposed between adjacent cutouts 91 to 94b of the pixel electrode 191. In addition, each cutout 71 to 74b includes at least one diagonal branch extending in parallel with the lower cutouts 93a and 94a or the upper cutouts 93b and 94b of the pixel electrode 191.

Each of the lower and upper cutouts 73a to 74b includes diagonal branches and horizontal branches. The oblique branches extend substantially parallel to the lower or upper cutouts 92a to 93b of the pixel electrode 191 from the right side of the pixel electrode 191 to the left, upper or lower side thereof. The horizontal and vertical branches extend from each end of the diagonal branch along the sides of the pixel electrode 191 and form an obtuse angle with the diagonal branch.

The first central cutout 71 includes a central transverse branch, a pair of oblique branches and a pair of longitudinal longitudinal branches. The central horizontal branches extend from the right side of the pixel electrode 191 to the left along the horizontal center line of the pixel electrode 191, and the pair of diagonal lines extend from the end of the central horizontal branch toward the left side of the pixel electrode 191, respectively. It extends almost parallel to the lower and upper incisions 73a, 73b, 74a, 74b. The vertical longitudinal branches extend along the left side of the pixel electrode 191 from each end of the diagonal branches and form an obtuse angle with the diagonal branches.

The second central cutout 72 includes a central termination branch, a pair of oblique branches and a pair of longitudinal longitudinal branches. The pair of oblique branches and the pair of longitudinal longitudinal branches of the second central incision 72 are parallel to the pair of the oblique branches and the pair of longitudinal longitudinal branches of the first central incision 71, and the central termination branches Connect oblique branches of a pair.

The number and direction of the cutouts 71 to 74b may also vary depending on design elements.

Alignment layers 11 and 21 are formed on inner surfaces of the display panels 100 and 200, and they may be vertical alignment layers.

Polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, and the polarization axes of the two polarizers 12 and 22 are orthogonal to each other, and one of the polarization axes is relative to the gate lines 121a and 121b. Side by side is preferred. In the case of a reflective liquid crystal display, one of the two polarizers 12 and 22 may be omitted.

The liquid crystal display may include a polarizer 12 and 22, a phase retardation film, display panels 100 and 200, and a backlight unit (not shown) for supplying light to the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 191, an electric field (electric field) substantially perpendicular to the surfaces of the display panels 100 and 200 is generated. In response to the electric field, the liquid crystal molecules attempt to change their long axis to be perpendicular to the direction of the electric field. From now on, the pixel electrode 191 and the common electrode 271 will be referred to as an electric field generating electrode.

On the other hand, the incisions 91 to 93b of the pixel electrodes of the field generating electrodes 191 and 270 and the incisions 71 to 74b of the common electrode and the hypotenuse of the pixel electrode 191 parallel to these distort the electric field to form a liquid crystal. Create horizontal components that determine the direction of the molecules' oblique directions. The horizontal component of the electric field is perpendicular to the hypotenuse of the cutouts 91a to 93 and 71 to 74b and the hypotenuse of the pixel electrode 191.

Referring to FIG. 8, one common electrode cutout set 71 to 74b and pixel electrode cutout set 91 to 93b divide the pixel electrode 191 into a plurality of sub-areas. The region has two major edges that form an oblique angle with the peripheral side of the pixel electrode 191. Most of the liquid crystal molecules on each subregion are inclined in a direction perpendicular to the periphery thereof, and thus, the inclination directions are approximately four directions. As described above, when the liquid crystal molecules are inclined in various directions, the reference viewing angle of the liquid crystal display is increased.

At least one of the cutouts 91-93b and 71-74b may be replaced by a protrusion or a depression, and the shape and arrangement of the cutouts 91-93b and 71-74b may be modified.

A second pixel PXb of the liquid crystal display according to the exemplary embodiment of the present invention will now be described in detail with reference to FIG. 9.

9 is a layout view of the second pixel PXb of the liquid crystal display according to the exemplary embodiment of the present invention.

Referring to FIG. 9, the first pixel PXa of the liquid crystal display according to the exemplary embodiment may also be disposed between the lower panel (not shown), the upper panel (not shown), and the two display panels that face each other. Liquid crystal layer (not shown).

The layer structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layer structure of the liquid crystal panel assembly shown in Figs.

Referring to the lower panel, a plurality of gate conductors including a plurality of gate lines 121, a plurality of storage electrode lines 131, and a light blocking layer 120 are formed on an insulating substrate (not shown). Each gate line 121 includes a gate electrode 124 and an end portion 129, and each storage electrode line 131 includes a storage electrode 137. A gate insulating film (not shown) is formed on the gate conductors 121 and 131. Semiconductors 151 and 154 are formed on the gate insulating film, and a plurality of ohmic contacts (not shown) are formed thereon. A data conductor including a plurality of data lines 171 and a plurality of first and second drain electrodes 175a and 175b is formed on the ohmic contact member and the gate insulating layer. The data line 171 includes a plurality of first and second source electrodes 173a and 173b and an end portion 179. A passivation layer (not shown) is formed on the data conductors 171, 175a, and 175b and the exposed portion of the semiconductor 154, and a plurality of contact holes 181, 182, 185a, and 185b are formed in the passivation layer and the gate insulating layer. It is. First and second subpixel electrodes 191a and 191b and a plurality of contact assistants 81 and 82 are formed on the passivation layer. An alignment layer (not shown) is formed on the pixel electrode 191, the contact auxiliary members 81 and 82, and the passivation layer.

Unlike the first pixel PXa illustrated in FIGS. 4 through 8, the second pixel PXb illustrated in FIG. 9 may include a semiconductor 154 and a first / second source electrode 173a on the right side of the pixel electrode 191. And first and second thin film transistors Qa and Qb each including the / 173b and the first and second drain electrodes 175a and 175b are disposed.

The first drain electrode 175a is bent in a counterclockwise direction starting at the end of the bar and extends obliquely to the data line 171, and has a wide area. The contact portion 185a is formed in the extension portion. In addition, the first drain electrode 175a includes an extension portion 176c that is bent in a counterclockwise direction near the rod-shaped end portion and protrudes substantially parallel to the data line 171.

The second drain electrode 175b extends in parallel to the gate line 124 by bending counterclockwise at the rod-shaped end portion and includes an extension having a large area. The contact portion 185b is formed in the extension portion. In addition, the second drain electrode 175b includes an extension part 176d extending from the extension part.

4 and 9, the positions of the first and second thin film transistors Qa and Qb are different from each other, but the first and second drain electrodes 175a and 175b have substantially the same shape. That is, even though the connection relationship between the pixel electrode 191 and the first and second thin film transistors Qa and Qb is different from each other in the first and second pixels PXa and PXb, the electro-optical characteristics of the pixels PXa and PXb are different from each other. The same can be adjusted. Accordingly, there is no difference in luminance or the like in the front or viewing angle directions of each of the first and second pixels PXa and PXb.

Although the shapes of the first and second drain electrodes 175a and 175b have been described with reference to FIGS. 4 and 9, the present invention is not limited thereto, and planar shapes of the first and second pixels PXa and PXb may be provided. Many of these same forms may be employed.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 applies the input image signals R, G, and B to the operating conditions of the liquid crystal panel assembly 300 and the data driver 500 based on the input image signals R, G, and B and the input control signal. After appropriately processing and generating the gate control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are processed. ) Is output to the data driver 500. The output video signal DAT has a predetermined number (or gradation) as a digital signal.

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a horizontal synchronization start signal STH indicating the start of image data transmission for a group of pixels PX and a load signal LOAD for applying the data signal Vd to the liquid crystal panel assembly 300. ) And a data clock signal HCLK. The data control signal CONT2 also inverts the voltage polarity of the data signal Vd relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal relative to the common voltage "). It may further include an inversion signal RVS.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for a group of pixels, and the gray voltage corresponding to each digital image signal DAT. By converting the digital image signal DAT to an analog data signal Vd, it is applied to the corresponding data line 171. In this case, data signals Vd having different polarities are applied to the adjacent data lines 171.

The gate driver 400 applies a gate-on voltage Von to the gate line 121 in response to the gate control signal CONT1 from the signal controller 600, and switches the switching elements Q1 and Q2 connected to the gate line 121. Turn on). Then, the data signal Vd applied to the data line 171 is applied to the corresponding subpixels PX1 and PX2 through the turned-on switching elements Q1 and Q2.

Subsequently, the gate-off voltage Voff is applied to the gate line G to turn off the switching elements Q1 and Q2.

On the other hand, the first and second storage electrode signals having opposite phases are applied to the first storage electrode line 131u and the second storage electrode line 131d, respectively, after the switching elements Q1 and Q2 are turned off. The voltage levels of the second sustain electrode signals are inverted, respectively. Then, the voltage of the first subpixel electrode 191a receiving only one of the first and second sustain electrode signals increases or decreases, and the second subpixel PX2 receives both the first and second sustain electrode signals. The voltage of the sub-pixel electrode 191b of N is canceled by the rising and falling portions so that the voltage change is almost unchanged. At this time, the voltage of the sustain electrode signal applied to the first subpixel PX1 to which the positive data voltage Vd is applied is increased, on the contrary, the data voltage Vd of the negative polarity is applied. The voltage of the sustain electrode signal applied to the received first subpixel PX1 is decreased. In this case, the voltage of the first subpixel electrode 191a is higher than the voltage of the second subpixel electrode 191b, so that the voltage across the first liquid crystal capacitor Clc1 is opposite the second liquid crystal capacitor Clc2. Higher than the voltage.

In this way, when a potential difference occurs between both ends of the first or second liquid crystal capacitors Clc1 and Clc2, a primary electric field substantially perpendicular to the surfaces of the display panels 100 and 200 is generated in the liquid crystal layer 3. [Hereinafter, the pixel electrode 190 and the common electrode 270 will be referred to as " field generating electrode. &Quot; The angle of inclination is perpendicular, and the degree of change in polarization of incident light in the liquid crystal layer 3 varies according to the degree of inclination of the liquid crystal molecules. This change in polarization is represented by a change in transmittance by the polarizer, through which the liquid crystal display displays an image.

The angle at which the liquid crystal molecules are inclined depends on the intensity of the electric field. Since the voltages of the two liquid crystal capacitors Clc1 and Clc2 are different from each other, the angles at which the liquid crystal molecules are inclined are different, and thus the luminance of the two subpixels PX1 and PX2 is different. . Therefore, if the voltage of the first liquid crystal capacitor Clc1 and the voltage of the second liquid crystal capacitor Clc2 are properly adjusted, the image viewed from the side can be as close as possible to the image viewed from the front, that is, the side gamma curve is the front gamma curve. As close as possible to this, side visibility can be improved.

In addition, when the area of the first subpixel electrode 191a having a high voltage is smaller than the area of the second subpixel electrode 191b, the side gamma curve may be closer to the front gamma curve.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), in order for all the gate lines G in order. The image signal of one frame is displayed by applying the data signal Vd to all the pixels PX by applying the gate-on voltage Von.

When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is changed such that the polarity of the data signal Vd applied to each pixel PX is opposite to that of the previous frame. Controlled ("frame inversion").

Next, a driving method of the liquid crystal display will be described in more detail with reference to FIGS. 10 to 12.

FIG. 11 is a graph illustrating a gamma curve of a pixel electrode for each gray level, FIG. 12 is a graph illustrating a change rate of total luminance according to a voltage change of the first subpixel electrode 191a, and FIG. 13 is a second subpixel electrode ( 191b) is a graph showing the rate of change of the total luminance according to the voltage change.

Parasitic capacitance is generated between the data line 171 and the pixel electrode 191. The pixel electrode voltage is affected by this parasitic capacitance and changes. Since different voltages are applied to the first subpixel electrode 191a and the second subpixel electrode 191b, the first subpixel electrode 191a and the second subpixel may be changed even if the pixel electrode voltage is changed by the same amount according to the parasitic capacitance. The luminance change rate of the pixel electrode 191b is different.

Referring to FIG. 10, a gamma curve 31 of the first subpixel electrode for each gray level, a gamma curve 32 of the second subpixel electrode, and an average gamma curve 30 of the pixel electrode are illustrated. In low gradations in which luminance changes sensitively to small voltage variations, the voltage change rate of the first subpixel electrode is large, and the voltage change rate of the second subpixel electrode is off. In high gradations in which luminance does not change sensitively due to voltage fluctuations, the voltage change rate of the first subpixel electrode is small and the voltage change rate of the second subpixel electrode is large.

Referring to FIGS. 11 and 12, the luminance change rate of the first subpixel electrode 191a reaches 9% at low gray levels. On the contrary, since the second subpixel electrode 191b is in the off state in the low gradation, the luminance change rate is close to 0%, and the luminance change rate increases with the high gradation. However, the rate of change of luminance at high gradation of the second subpixel electrode 191b is very small compared to the rate of change of luminance of the first subpixel electrode 191a at a maximum of 0.45%.

Accordingly, when the first subpixel electrode 191a, which is more sensitive to the change in luminance, does not overlap the data line 171, the change in luminance due to parasitic capacitance may be prevented. In addition, the aperture ratio can be ensured by overlapping the data line 171 with the second subpixel electrode 191b having a relatively low luminance change rate.

Next, operations of the liquid crystal display according to various embodiments of the present invention will be described in detail with reference to FIGS. 13 to 18.

FIG. 13 is a schematic diagram illustrating a sustain voltage line of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 14 illustrates pixel voltages along with other voltages when inverting a liquid crystal display according to an exemplary embodiment of the present invention. This is a waveform diagram.

Referring to FIG. 13, the first storage electrode line Su is connected to the first storage signal bar La, and the second storage electrode line Su is connected to the second storage signal bar Lb. . This connection relationship is the same for all the first and second storage electrode lines Su and Sd, and the first and second storage electrode lines Su and Sd are formed by only two storage signal bars La and Lb in one liquid crystal display. The sustain electrode signal is applied to the.

Referring to FIG. 14, the sustain electrode signals applied from the first and second sustain signal bars La and Lb are AC voltages having a period of 2H. At this time, the first and second sustain electrode signals Vcst-u and Vcst-d emitted from the first and second sustain signal bars La and Lb are respectively opposite in phase.

When the gate signal is changed from the gate off voltage Vgoff to the gate on voltage Vgon, a positive data voltage is applied to the pixel electrode 191 to be charged. Then, the pixel electrode voltage, for example, the first subpixel electrode voltage Vpixa rises according to the data voltage, and after 1H, the gate signal changes to the gate off voltage Vgoff. At this time, the first sustain electrode signal Vcst-u is a positive electrode (+) and the second sustain electrode signal Vcst-d is a negative polarity (−). The second subpixel electrode 191b that is affected by both the first and second sustain electrode signals Vcst-u and Vcst-d has no voltage change. However, the first subpixel electrode voltage Vpixa is periodically affected by one of the first and second sustain electrode signals Vcst-u and Vcst-d, for example, the first sustain electrode signal Vcst-u. The average value is higher than the previous value. Therefore, when looking at the difference from the common electrode voltage, the first subpixel electrode voltage Vpixa is greater than the second subpixel electrode voltage.

On the other hand, when the data voltage is negative, when the gate signal is changed from the gate-off voltage Vgoff to the gate-on voltage Vgon, the pixel electrode voltage, for example, the first subpixel electrode voltage Vpixa, is applied to the data voltage. Descend accordingly. In this case, since the second subpixel electrode 191b is affected by both the first and second sustain electrode signals Vcst-u and Vcst-d, the second subpixel electrode 191b has no voltage change. However, the first subpixel electrode voltage Vpixa is periodically affected by any one of the first and second sustain electrode signals Vcst-u and Vcst-d, for example, the second sustain electrode signal Vcst-d. The average value is lower than the previous value. Therefore, when looking at the difference from the common electrode voltage, the first subpixel electrode voltage Vpixa is greater than the second subpixel electrode voltage.

That is, the voltage of the first subpixel electrode may be maintained higher than the voltage of the second subpixel electrode during the driving of the positive (+) and the negative (-) driving.

A driving method of a liquid crystal display according to another exemplary embodiment of the present invention will now be described with reference to FIG. 15.

15 is a waveform diagram illustrating a signal for driving a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 15, the periods of the first and second sustain electrode signals Vcst-u and Vcst-d are longer than those of FIG. 14. Accordingly, the value of the first subpixel electrode voltage Vpixa whose voltage periodically changes according to the period of the first or second sustain electrode signals Vcst-u and Vcst-d also changes in a longer period than in the case of FIG. 14. That is, the delay of the sustain electrode signal applied to the sustain electrode lines Su and Sd can be prevented and crosstalk can be prevented.

A driving method of a liquid crystal display according to another exemplary embodiment of the present invention will now be described in detail with reference to FIGS. 16 to 18.

FIG. 16 is a diagram illustrating polarities of pixels in driving spots of a liquid crystal display according to another exemplary embodiment of the present invention, FIG. 17 is a waveform diagram of voltages in inversion driving shown in FIG. 16, and FIG. 18 is FIG. A waveform diagram showing pixel voltages along with other voltages during inversion driving shown in FIG.

Referring to FIG. 16, the first and second storage electrode lines 131u and 131d are connected to the first and second signal lines Sh and Sl through the third and fourth switching elements Q3 and Q4, respectively. The control terminal of the third / fourth switching element Q3 / Q4 is connected to the rear gate line 121, the input terminal is connected to the first / second signal line Sh / Sl, and the output terminal The first / second storage electrode lines 131u / 131d are connected.

Referring to FIG. 17, the first sustain electrode signal Vsu and the second sustain electrode signal Vsd applied to the first sustain electrode line 131u are opposite in phase and change in level every frame. That is, after charging all the pixels PX, the voltage levels of the first sustain electrode signal Vsu and the second sustain electrode signal Vsd are changed.

When the gate signal is changed from the gate off voltage Vgoff to the gate on voltage Vgon, a positive data voltage is applied to the pixel electrode 191 to be charged. Then, the pixel electrode voltage, for example, the first subpixel electrode voltage Vpixa rises according to the data voltage, and after 1H, the gate signal changes to the gate off voltage Vgoff. At this time, the first sustain electrode signal Vcst-u is a positive electrode (+) and the second sustain electrode signal Vcst-d is a negative polarity (−). The second subpixel electrode 191b that is affected by both the first and second sustain electrode signals Vcst-u and Vcst-d has no voltage change. However, the first subpixel electrode voltage Vpixa is affected by any one of the first and second sustain electrode signals Vcst-u and Vcst-d, for example, the first sustain electrode signal Vcst-u. Periodically changes, the average value is higher than the previous value. Therefore, when looking at the difference from the common electrode voltage, the first subpixel electrode voltage Vpixa is greater than the second subpixel electrode voltage.

On the other hand, when the data voltage is negative, when the gate signal is changed from the gate-off voltage Vgoff to the gate-on voltage Vgon, the pixel electrode voltage, for example, the first subpixel electrode voltage Vpixa, is applied to the data voltage. Descend accordingly. In this case, since the second subpixel electrode 191b is affected by both the first and second sustain electrode signals Vcst-u and Vcst-d, the second subpixel electrode 191b has no voltage change. However, the first subpixel electrode voltage Vpixa is periodically affected by any one of the first and second sustain electrode signals Vcst-u and Vcst-d, for example, the second sustain electrode signal Vcst-d. The average value is lower than the previous value. Therefore, when looking at the difference from the common electrode voltage, the first subpixel electrode voltage Vpixa is greater than the second subpixel electrode voltage.

However, as described above, since the voltage of the liquid crystal capacitor Clc2 of the second subpixel PX does not change, the luminance of the first subpixel PX1 is always higher than that of the second subpixel PX2.

According to the present invention, the aperture ratio and the transmittance can be increased, and the side visibility can also be improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (23)

Board, First and second storage electrode lines formed on the substrate, and A plurality of pixel electrodes formed on the substrate and including first and second subpixel electrodes Including, The pixel electrode has a pair of first peripheral sides facing each other and a pair of second peripheral sides connected to the first peripheral side and facing each other, The second peripheral side of the pixel electrode includes a sawtooth protrusion, The first subpixel electrode overlaps the first or second storage electrode line, and the second subpixel electrode overlaps the first and second storage electrode line. Liquid crystal display. In claim 1, A first thin film transistor connected to the first subpixel electrode, A second thin film transistor connected to the second subpixel electrode, A gate line connected to the first and second thin film transistors, and A first data line connected to the first and second thin film transistors and crossing the gate line Liquid crystal display further comprising. In claim 2, The first data line at least partially overlaps the second subpixel electrode. In claim 3, The first data line does not overlap the first subpixel electrode. In claim 3, A second data line adjacent to the first data line; And the second subpixel electrode overlaps the first data line and the second data line at the same time. In claim 5, And an area where the second subpixel electrode and the first data line overlap is substantially the same as an area where the second subpixel electrode and the second data line overlap. In claim 5, The polarity of the data voltage applied to the first data line and the polarity of the data voltage applied to the second data line are opposite to each other. In claim 5, The first and second data lines are bent at least once. In claim 2, A first semiconductor overlapping the first data line below the first data line, the first semiconductor being substantially the same as the flat shape of the first data line, and A light blocking film overlapping the first semiconductor Liquid crystal display comprising a. In claim 9, The light blocking layer is formed of the same material as the first and second gate lines. In claim 9, The width of the first semiconductor is greater than the width of the first data line. In claim 2, And an organic layer formed between the first data line and the pixel electrode. In claim 1, The liquid crystal display of claim 1, wherein the storage electrode signal applied to the first storage electrode line and the storage electrode signal applied to the second storage electrode line are opposite in phase. In claim 1, And a sustain electrode signal applied to the first sustain electrode line and a sustain electrode signal applied to the second sustain electrode line are alternating current voltages changed at a period of 1H or more. In claim 2, The first and second thin film transistors are alternately positioned at the right or left side of the data line every at least one row. In claim 1, Pixel electrodes adjacent in the column direction have opposite polarities. In claim 1, Pixel electrodes adjacent in the row direction have opposite polarities. In claim 1, The area of the second subpixel electrode is larger than the area of the first subpixel electrode. In claim 1, The voltage of the first subpixel electrode is different from the voltage of the second subpixel electrode. The method of claim 19, The area of the first subpixel electrode is higher than the voltage of the second subpixel electrode. In claim 1, The pixel electrode includes a plurality of cutouts forming an oblique angle with the first peripheral portion. In claim 1, Further comprising a common electrode facing the pixel electrode, The common electrode includes a plurality of cutouts that form an oblique angle with the first peripheral portion. A liquid crystal display device comprising a plurality of pixels, Each pixel, First and second liquid crystal capacitors, A first storage capacitor having a first terminal connected to the second liquid crystal capacitor and a second terminal receiving a first storage electrode signal; A second storage capacitor having a first terminal connected to the second liquid crystal capacitor and a second terminal receiving a second storage electrode signal opposite in phase to the first storage electrode signal; and A third storage capacitor having a first terminal connected to the first liquid crystal capacitor and a second terminal receiving the first storage electrode signal or the second storage electrode signal, respectively; The first liquid crystal capacitor has a first subpixel electrode, the second liquid crystal capacitor has a second subpixel electrode which forms a pixel electrode together with the first subpixel electrode, The pixel electrode has a pair of first peripheral sides facing each other and a pair of second peripheral sides connected to the first peripheral side and facing each other, The second peripheral side of the pixel electrode includes a sawtooth protrusion Liquid crystal display.

Images