CN100514168C - Pixel structure and its manufacturing method - Google Patents
Pixel structure and its manufacturing method Download PDFInfo
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- CN100514168C CN100514168C CNB2007101401381A CN200710140138A CN100514168C CN 100514168 C CN100514168 C CN 100514168C CN B2007101401381 A CNB2007101401381 A CN B2007101401381A CN 200710140138 A CN200710140138 A CN 200710140138A CN 100514168 C CN100514168 C CN 100514168C
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Abstract
The utility model discloses a dot structure and the manufacturing method thereof. Firstly, the first graphic conductor layer is formed on the base plate and comprises a grid and a data line, and then a grid isolation layer is formed on the base plate, so as to cover the first graphic conductor layer. Also, a semiconductor channel layer is formed on the grid isolation layer above the grid. Afterwards, the second graphic conductor layer is formed on the grid isolation layer and the semiconductor channel layer. Such second graphic conductor layer comprises a scan line, a common electrode wire, a source electrode and a drain electrode. The scan line is electrically connected with the grid; the common electrode wire is arranged above the data line, while the source electrode and the drain electrode are situated on the semiconductor channel layer. In addition, the source electrode is electrically connected with the data line. At the same time, the protective layer is formed on the base plate to cover the second graphic conductor layer, and then the pixel element electrode is formed on the protective layer. Meanwhile, the electrical connection is made between the pixel element electrode and the drain electrode.
Description
Technical field
The present invention relates to a kind of dot structure and manufacture method thereof, and particularly relevant for a kind of dot structure and manufacture method thereof with high aperture (aperture ratio).
Background technology
In the middle of the life in 3C epoch, many a feast for the eyes information equipments are arranged on the market, for example digitization tools such as mobile phone, digital camera, digital camera, mobile computer and desktop PC develop towards direction more convenient, multi-functional and attractive in appearance invariably.In most information equipment, all be with flat-panel screens as main communication interface, by the Presentation Function of flat-panel screens, make the user more convenient in the operation of product.Wherein, power saving, high image quality, space utilization efficient are good because of having for LCD, low consumpting power, advantageous characteristic such as radiationless, have become the main flow in market.
Generally speaking, the dot structure of LCD comprises sweep trace, data line, active member and pixel electrode.In dot structure, the stray capacitance between data line and the pixel electrode (Capacitancebetween pixel and data line, C
Pd) be one of factor that influences aperture opening ratio.In detail, when the distance of data line and pixel electrode shortens, the stray capacitance (C between data line and the pixel electrode
Pd) can increase, for fear of the stray capacitance (C between data line and the pixel electrode. thereupon
Pd) crosstalk effect (cross talk) that caused; the deviser can allow data line and pixel electrode maintain a certain distance usually, reducing vertical crosstalk effect (vertical cross talk), yet; the distance of data line and pixel electrode is far away more, causes the decline of pixel aperture ratio also many more.
For reducing the crosstalk effect of above-mentioned dot structure, the aperture opening ratio of dot structure is maintained to a certain degree, existing many dot structures are suggested in succession.For example, can between pixel electrode and data line, dispose thicker insulation course to reduce the effect of stray capacitance.Yet, common insulating layer material is an organic material, for example be acryl resin, except having the shortcoming that easy absorption aqueous vapor causes the adhesion variation, in technology, also have to make the shortcoming of penetration decline of dot structure integral body because material itself can't decolour fully (bleach).
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of one pixel structure process method, with reduce pixel electrode and data line too near the time, the crosstalk effect that is produced.
The present invention provides a kind of dot structure in addition, and it has high aperture opening ratio.
The present invention proposes a kind of one pixel structure process method.At first, form first patterning conductor layer on substrate, it comprises grid and data line.Then, on substrate, form gate insulator, covering first patterning conductor layer, and on the gate insulator of grid top, form the channel semiconductor layer.Then, form second patterning conductor layer on gate insulator and channel semiconductor layer, it comprises sweep trace, common electrode wire and source electrode and drain electrode.Sweep trace and grid electrically connect, and common electrode wire is positioned at the data line top, and source electrode and drain electrode are positioned on the channel semiconductor layer, and source electrode electrically connects data line.Thereupon, on substrate, form protective seam,, then, on protective seam, form pixel electrode to cover second patterning conductor layer, and pixel electrode and drain electrode electric connection.
In one embodiment of this invention, above-mentioned pixel electrode and common electrode wire partly overlap, to constitute a storage capacitors.
In one embodiment of this invention, the method for above-mentioned formation channel semiconductor layer may further comprise the steps.At first, on gate insulator, form semiconductor material layer, and deposit or doping process, form ohmic contact layer with upper surface in semiconductor material layer.Then, the patterned semiconductor material layer is to form the channel semiconductor layer.
In one embodiment of this invention, the method of above-mentioned formation gate insulator for example is prior to forming first dielectric layer on the substrate, and then in first dielectric layer, form first contact hole and second contact hole, to expose the subregion of grid and data line respectively.
In one embodiment of this invention, above-mentioned sweep trace electrically connects by first contact hole and grid.
In one embodiment of this invention, above-mentioned source electrode electrically connects by second contact hole and data line.
In one embodiment of this invention, the method for above-mentioned formation protective seam comprises prior to forming second dielectric layer on the substrate, and covers second patterning conductor layer, then forms the 3rd contact hole in second dielectric layer, to expose the subregion of drain electrode.
In one embodiment of this invention, above-mentioned pixel electrode electrically connects by the 3rd contact hole and drain electrode.
In one embodiment of this invention, above-mentioned one pixel structure process method also is included in when forming first patterning conductor layer, forms the articulamentum of a side that is positioned at grid.In addition, after forming the channel semiconductor layer and before forming second patterning conductor layer, more can form one the 4th contact hole in gate insulator, to expose the part articulamentum, so that after the formation of second patterning conductor layer, drain electrode electrically connects by the 4th contact hole and articulamentum.
In one embodiment of this invention; above-mentioned one pixel structure process method also is included in behind the formation protective seam and forms before the pixel electrode; form one the 5th contact hole in protective seam with gate insulator in; to expose the part articulamentum; and make after the pixel electrode formation, pixel electrode electrically connects articulamentum by the 5th contact hole.
According to the one pixel structure process method of the foregoing description, the present invention proposes a kind of dot structure in addition, and it is suitable for being disposed on the substrate.This dot structure comprises first patterning conductor layer, gate insulator, semiconductor channel layer, second patterning conductor layer, protective seam and pixel electrode.First patterning conductor layer comprises grid and data line, and gate insulator covers first patterning conductor layer.The semiconductor channel layer is disposed on the gate insulator of grid top, and second patterning conductor layer is disposed on gate insulator and the channel semiconductor layer.Second patterning conductor layer comprises sweep trace, common electrode wire and source electrode and drain electrode, and wherein sweep trace and grid electrically connect, and common electrode wire is positioned at the data line top, and source electrode and drain electrode are positioned on the channel semiconductor layer, and source electrode electrically connects data line.In addition, protective seam covers second patterning conductor layer, and pixel electrode is disposed on the protective seam, and pixel electrode and drain electrode electric connection.
In one embodiment of this invention, the upper surface of above-mentioned channel semiconductor layer also comprises an ohmic contact layer.
In one embodiment of this invention, above-mentioned gate insulator has one first contact hole and one second contact hole, lays respectively at grid and data line top.Simultaneously, sweep trace electrically connects by first contact hole and grid, and source electrode electrically connects by second contact hole and data line.
In one embodiment of this invention, above-mentioned protective seam has the 3rd contact hole that is positioned at the drain electrode top, and pixel electrode electrically connects by the 3rd contact hole and drain electrode.
In one embodiment of this invention, the first above-mentioned patterning conductor layer also comprises an articulamentum, is positioned at drain electrode and pixel electrode below.In addition, gate insulator for example has the 4th contact hole, so that drain electrode electrically connects articulamentum by the 4th contact hole.In addition, protective seam is for example to have the 5th contact hole with gate insulator, so that pixel electrode electrically connects articulamentum by the 5th contact hole.
The present invention reintroduces a kind of dot structure, is suitable for being disposed on the substrate.This dot structure comprises first patterning conductor layer, gate insulator, semiconductor channel layer, second patterning conductor layer, protective seam and pixel electrode.First patterning conductor layer is disposed on the substrate, and first patterning conductor layer comprises grid and articulamentum at least.Gate insulator covers first patterning conductor layer.The semiconductor channel layer is disposed on the gate insulator of grid top.Second patterning conductor layer is disposed on gate insulator and the channel semiconductor layer, and second patterning conductor layer comprises source electrode and drain electrode at least.Data line and sweep trace that first patterning conductor layer, semiconductor channel layer and second patterning conductor layer constitute thin film transistor (TFT) jointly and electrically connect with thin film transistor (TFT).Protective seam covers second patterning conductor layer.Pixel electrode then is disposed on the protective seam, and pixel electrode electrically connects by articulamentum and drain electrode.
In one embodiment of this invention, above-mentioned data line comprises one first line segment and one second line segment, and first line segment is made of part first patterning conductor layer, and second line segment is made of second patterning conductor layer and electrically connects with first line segment.
The present invention also proposes a kind of display panels, and it comprises first substrate, second substrate and liquid crystal layer.First substrate comprises as each described dot structure among the above-mentioned embodiment, and second substrate is provided with the first substrate subtend.Simultaneously, liquid crystal layer is arranged between first substrate and second substrate.
In dot structure of the present invention and the manufacture method thereof, common electrode wire is disposed between pixel electrode and the data line aperture opening ratio that helps to reduce the effect of stray capacitance and improve dot structure.In addition, the present invention forms an articulamentum so that pixel electrode and drain electrode electrically connect by articulamentum when forming first patterning conductor layer.Thus, the situation that does not have broken string between pixel electrode and drain electrode takes place, and dot structure of the present invention is when being applied to LCD, and common electrode wire is positioned at the toppling direction that the articulamentum top also helps auxiliary liquid crystal molecule.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Description of drawings
Figure 1A to Fig. 1 F be one embodiment of the invention one pixel structure process method on look synoptic diagram;
Fig. 2 A to Fig. 2 F distinctly for Figure 1A in Fig. 1 F along hatching line AA ',, hatching line BB ', the hatching line CC ' sectional view of doing;
Fig. 3 A be another embodiment of the present invention dot structure on look synoptic diagram;
The sectional view that Fig. 3 B does for the hatching line D-D ' along Fig. 3 A;
Fig. 4 is for looking synoptic diagram on the dot structure of another embodiment of the present invention;
Fig. 5 is a kind of display panels of one embodiment of the invention.
Wherein, Reference numeral:
100: 110: the first patterning conductor layer of substrate
112: grid 114,414: data line
116: articulamentum 120: gate insulator
120a: 122: the first contact holes of first dielectric layer
126: the four contact holes of 124: the second contact holes
130: channel semiconductor layer 132: ohmic contact layer
132a: 140: the second patterning conductor layer of patterning doped semiconductor material layer
142,418: sweep trace 144: common electrode wire
146: source electrode 148,446: drain electrode
150: 152: the three contact holes of protective seam
Contact hole 160 in 154: the five: pixel electrode
170,300,400,540: dot structure 180: thin film transistor (TFT)
414A: the first line segment 414B: second line segment
Contact hole 500 in 416: the six: display panels
520: the second substrates of 510: the first substrates
530: liquid crystal layer Cst: storage capacitors
Embodiment
Figure 1A to Fig. 1 F be one embodiment of the invention one pixel structure process method on look synoptic diagram, and the sectional view that Fig. 2 A distinctly does along hatching line AA ', hatching line BB ' and hatching line CC ' in Fig. 1 F for Figure 1A to Fig. 2 F.The one pixel structure process method of present embodiment comprises each step of the following stated.At first, please form first patterning conductor layer 110 on substrate 100 earlier with reference to Figure 1A and Fig. 2 A, wherein first patterning conductor layer 110 comprises grid 112 and data line 114.The mode that forms first patterning conductor layer 110 comprises prior to forming the first conductor layer (not shown) on the substrate 100, and with the first conductor layer (not shown) patterning.
In the present embodiment, substrate 100 for example is transparent substrates such as glass substrate or plastic base, and the material of first conductor layer is applied to that grid 112 is made and data line 114 is made in can the technical field of the invention any or various material.For example, the material of first patterning conductor layer 110 for example is aluminium (Al), copper (Cu), molybdenum (Mo), silver (Ag), gold (Au), or the alloy that these metals constituted, multiple layer metal layer or complex metal layer.
Then please refer to Figure 1B and Fig. 2 B, on substrate 100, form the first dielectric layer 120a covering first patterning conductor layer 110, and the first dielectric layer 120a in grid 112 tops goes up and forms channel semiconductor layer 130.In the present embodiment, the mode that forms the first dielectric layer 120a for example is a chemical vapour deposition technique.For instance, the material of the first dielectric layer 120a for example is dielectric materials such as silicon dioxide, silicon nitride or silicon oxynitride.
In addition, the method for formation channel semiconductor layer 130 may further comprise the steps.At first, on gate insulator 120, form semiconductor material layer (not shown) such as amorphous silicon, and carry out doping process, form the doped semiconductor material layer (not shown) with upper surface, as N type doped semiconductor material layer (N+doped semiconductor layer) in the semiconductor material layer (not shown).Then, patterned semiconductor material layer (not shown) is positioned at the channel semiconductor layer 130 of grid 112 tops and the patterning doped semiconductor material layer 132a of upper surface thereof with formation.
Then please refer to Fig. 1 C and Fig. 2 C, in the first dielectric layer 120a, form first contact hole 122 and second contact hole 124, to form gate insulator 120.By Fig. 1 C and Fig. 2 C as can be known, first contact hole 122 can expose the subregion of grid 112, and second contact hole 124 can expose the subregion of data line 114.In the present embodiment, first contact hole 122 among the first dielectric layer 120a and second contact hole 124 for example are to form by lithography technology.
Then, please refer to Fig. 1 D and Fig. 2 D, go up in gate insulator 120, semiconductor channel layer 130 and patterning doped semiconductor material layer 132a and form second patterning conductor layer 140.Particularly, the mode that forms second patterning conductor layer 140 for example is to form the second conductor layer (not shown) on gate insulator 120 and channel semiconductor layer 130, and with the second conductor layer (not shown) patterning, to form second patterning conductor layer 140.It should be noted that when the second conductor layer (not shown) carries out patterning the patterning doped semiconductor material layer 132a of part can be removed together.In detail, after the second conductor layer (not shown) is patterned, can form sweep trace 142, common electrode wire 144, source electrode 146 and drain electrode 148, and can be removed to form ohmic contact layer 132 by the source electrode 146 and the 148 patterning doped semiconductor material layer 132a that covered that drain, till the channel semiconductor layer 130 of part is exposed.
By Fig. 1 D and 2D as can be known, sweep trace 142 electrically connects by first contact hole 122 with grid 112, and common electrode wire 144 is positioned at data line 114 tops.In addition, source electrode 146 electrically connects data line 114 by second contact hole 124.
Then, please refer to Fig. 1 E and Fig. 2 E, on gate insulator 120, form protective seam 150, to cover second patterning conductor layer 140.The method that forms protective seam 150 comprises prior to forming the second dielectric layer (not shown) that is covered on the gate insulator 120 and second patterning conductor layer 140 on the substrate 100; then in the second dielectric layer (not shown), form the 3rd contact hole 152, to expose the subregion of drain electrode 148.In the present embodiment, the material of protective seam 150 comprises monox, silicon nitride or silicon oxynitride.
Thereupon, please refer to Fig. 1 F and Fig. 2 F, on protective seam 150, form pixel electrode 160, so that pixel electrode 160 is to electrically connect by the 3rd contact hole 152 and drain electrode 148.The generation type of pixel electrode 160 can be the transparency conducting layer (not shown) that forms indium tin oxide, indium-zinc oxide or other material on protective seam 150, and with transparency conducting layer (not shown) patterning to form pixel electrode 150.In addition, common electrode wire 144 for example is to overlap with pixel electrode 160 parts and constitute a storage capacitors Cst.
By Fig. 1 F and Fig. 2 F as can be known, dot structure 170 is to be disposed on the substrate 100, and it comprises first patterning conductor layer 110, gate insulator 120, channel semiconductor layer 130, second patterning conductor layer 140, protective seam 150 and pixel electrode 160.Specifically, gate insulator 120 covers first patterning conductor layer 110.Semiconductor channel layer 130 is disposed on the gate insulator 120, and second patterning conductor layer 140 is disposed on gate insulator 120 and the channel semiconductor layer 130.In addition, protective seam 150 covers second patterning conductor layer 140, and pixel electrode 160 is disposed on the protective seam 150.
In detail, first patterning conductor layer 110 comprises grid 112 and data line 114, and second patterning conductor layer 140 comprises sweep trace 142, common electrode wire 144 and source electrode 146 and drain electrode 148.Simultaneously, channel semiconductor layer 130 is positioned at grid 112 tops, and common electrode wire 144 is positioned at data line 114 tops, and source electrode 146 is positioned on the channel semiconductor layer 130 with drain electrode 148.In addition, gate insulator 120 for example has first contact hole 122 that is positioned at grid 112 tops and is positioned at second contact hole 124 of data line 114 tops and sweep trace 142 electrically connects by first contact hole 122 and grid 112, and source electrode 146 electrically connects data lines 114 by second contact hole 124.In addition, protective seam 150 for example has the 3rd contact hole 152,148 electrically connects with pixel electrode 160 so that drain.Generally speaking, first patterning conductor layer 110, channel semiconductor layer 130 and second patterning conductor layer, 140 common data line 114 and the sweep traces 142 that constitute thin film transistor (TFT) 180 and electrically connect with thin film transistor (TFT) 180.
In general, data line 114 is near more with the distance of pixel electrode 160, and stray-capacity effect therebetween is big more, and makes the voltage of pixel electrode 160 be subjected to the different voltage influences that data line 114 is transmitted easily, and then tangible crosstalk effect takes place.For fear of the influence of crosstalk effect, can reduce the overlapping area between data line 114 and the pixel electrode 160 usually, but this measure makes aperture opening ratio be restricted.In the dot structure 170 of present embodiment, because the common electrode wire 144 that is disposed between data line 114 and the pixel electrode 160 can be covered data line 114 and 160 stray-capacity effects that produced of pixel electrode, so the configuration that makes pixel electrode 160 not can thereby limited, and can improve the aperture opening ratio of dot structure 170 effectively.Further, the data line 114 that is made of part first patterning conductor layer 110 is continuous segments, so the data line 114 difficult situations that broken string takes place, and helps to promote the quality of dot structure 170.
In the present embodiment, part overlaps and constitutes a storage capacitors Cst between common electrode wire 144 and the pixel electrode 160.Simultaneously, it should be noted that common electrode wire 144 for example is to be configured between the two adjacent data lines 114, and center on the edge (shown in Fig. 1 F) of pixel electrode 160.Therefore, the configuration of common electrode wire 144 can not make the aperture opening ratio of dot structure 170 glide significantly.When the common electrode wire 144 around pixel electrode 160 edges has energising pressure altogether, help to form the distortion electric field that changes to dot structure 170 centers by dot structure 170 edges.Therefore, dot structure 170 is applied to can make in the display panels liquid crystal molecule to have reaction rate faster, and liquid crystal molecule can be toppled over towards correct direction.Certainly, dot structure 170 of the present invention does not limit common electrode wire 144 around pixel electrode 160.In other words, common electrode wire 114 also can present the distribution of linearity or alternate manner.
Certainly, first patterning conductor layer 110, channel semiconductor layer 130 can connect by other different connected mode with second patterning conductor layer 140, with data line 114 and the sweep trace 142 that constitutes thin film transistor (TFT) 180 and electrically connect with thin film transistor (TFT) 180.Fig. 3 A be another embodiment of the present invention dot structure on look synoptic diagram, and the sectional view of Fig. 3 B for doing along the hatching line D-D ' of Fig. 3 A.Please earlier with reference to Fig. 3 A, dot structure 300 is roughly the same with the element of dot structure 170, and its difference part is as described below.In the dot structure 300, first patterning conductor layer 110 also comprises an articulamentum 116, is positioned at drain electrode 148 and pixel electrode 160 belows.Simultaneously, please refer to Fig. 3 A and Fig. 3 B, in the dot structure 300, for example have the 4th contact hole 126 in the gate insulator 120, so that drain 148 by the 4th contact hole 126 and articulamentum 116 electric connections.In addition, protective seam 150 with gate insulator 120 in for example have the 5th contact hole 154 so that pixel electrode 160 electrically connects articulamentums 116 by the 5th contact hole 154.At this moment, drain electrode 148 for example electrically connects by articulamentum 116 and pixel electrode 160.
Specifically, drain electrode 148 and the method that pixel electrode 160 electrically connects be may further comprise the steps.At first, when forming first patterning conductor layer 110, for example can form the articulamentum 116 of a side that is positioned at grid 112.That is to say that articulamentum 116 can directly be formed on the substrate 100 in the present embodiment.In addition, before forming channel semiconductor layer 130 back and forming second patterning conductor layer 140, for example can form the 4th contact hole 126 in gate insulator 120, with after second patterning conductor layer 140 forms, drain electrode 148 is electrically connected by the 4th contact hole 126 and articulamentum 116.In addition; before forming protective seam 150 backs and forming pixel electrode 160; for example form the 5th contact hole 154 in protective seam 150 with gate insulator 120 in, and make after pixel electrode 160 forms, pixel electrode 160 electrically connects articulamentums 116 by the 5th contact hole 154.
When forming the 4th contact hole 126 with the 5th contact hole 154, it is outer and expose articulamentum 116 part substrate 100 on every side to make the scope of contact hole (126 or 154) exceed the scope of articulamentum 116 because of the error of aiming on the technology.After forming drain electrode 148 or pixel electrode 160, the drain electrode 148 or part zone of pixel electrode 160 can directly be formed on the substrate 100.At this moment, the part of drain electrode 148 and pixel electrode 160 can be extended to a side of articulamentum 116 and still be the rete of a successive sedimentation by the upper surface of articulamentum 116.In other words, nearmis is arranged even form the technology of contact hole (126 or 154), pixel electrode 160 and articulamentum 116 and articulamentum 116 with drain 146 to be connected situation still quite good.Also promptly, the dot structure 300 of present embodiment has high technology yield.
In addition, the articulamentum 116 of present embodiment is positioned at common electrode wire 144 belows of ring-type, so pixel electrode 160 peripheral regions for example can be subjected to the influence of the common electric voltage of common electrode wire 144.At this moment, when dot structure 300 was applied to display panels, the common electric voltage that common electrode wire 144 is had helped arranging towards specific direction of auxiliary liquid crystal molecule.Furthermore, when exerting pressure (for example with the finger presses display panels) when the display panels with dot structure 300 is subjected to single-point, owing to the configuration of common electrode wire 144 makes liquid crystal molecule can recover its correct orientation apace.That is to say that the design of dot structure 300 helps to improve the quality of display panels.
In addition, dot structure of the present invention also can have the design of other kind.For example, Fig. 4 is for looking synoptic diagram on the dot structure of another embodiment of the present invention.Please refer to Fig. 4, dot structure 400 is roughly similar to dot structure 300, its difference is: the data line 414 of dot structure 400 can be divided into two line segments, and wherein the first line segment 414A is made of and the second line segment 414B is made of second patterning conductor layer first patterning conductor layer.In other words, the data line of dot structure 400 is not only to be made by one deck conductor layer.
The first line segment 414A and the second line segment 414B are electrically connected to each other by the 6th contact hole 416, and to drain 446 for example be directly to be connected with the second line segment 414B.That is to say that the drain electrode 446 and second line segment 414B is for example made by second patterned metal layer.In addition, sweep trace 418 is made of first patterning conductor layer with grid 112 in the dot structure 400.Simultaneously, the second line segment 414B is across sweep trace 142 tops and electrically connect the first line segment 414A.Wherein, drain electrode 148 also electrically connects by an articulamentum 116 and pixel electrode 160.The cross-talk phenomenon that the common electrode wire 144 of dot structure 400 is produced in the time of also can avoiding data line 414 transmission signals, and help to make display panels to have good quality.
Fig. 5 is a kind of display panels of one embodiment of the invention.Please refer to Fig. 5, display panels 500 comprises first substrate 510, second substrate 520 and liquid crystal layer 530.First substrate 510 comprises a plurality of dot structures 540, and second substrate 520 and the 510 subtend settings of first substrate.Second substrate 520 can be colored filter for example.Simultaneously, liquid crystal layer 530 is arranged between first substrate 510 and second substrate 520.Dot structure 540 is any dot structure among the above embodiment, and the design of its common electrode wire can reduce the stray capacitance between pixel electrode and the data line, and can avoid the generation of crosstalk effect.Can adopt same conductor layer to form data line in the dot structure 540, so that the reduction of the contact impedance of data line, so the quality of data transmission is quite good, the display panels 500 that also promptly has this dot structure 540 has good quality.Simultaneously, can make between drain electrode and the pixel electrode by an articulamentum in the dot structure 540 to electrically connect, with avoid draining and pixel electrode between the situation of broken string takes place, and help to improve the technology yield of display panels 500.Furthermore, in the dot structure of the present invention, common electrode wire is disposed at around the pixel electrode, and its common electric voltage helps the Liquid Crystal Molecules Alignment of auxiliary liquid crystal layer 530.Particularly, the common electric voltage of common electrode wire can make and be positioned at the other correct orientation of liquid crystal molecule tendency of thin film transistor (TFT), and makes display panels 500 keep superior display quality.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; being familiar with those of ordinary skill in the art ought can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (18)
1. an one pixel structure process method is characterized in that, comprising:
Form one first patterning conductor layer on a substrate, this first patterning conductor layer comprises a grid and a data line;
Form a gate insulator on this substrate, to cover this first patterning conductor layer;
Form the semiconductor channel layer on this gate insulator of this grid top;
Form one second patterning conductor layer on this gate insulator and this channel semiconductor layer, this second patterning conductor layer comprises one scan line, a common electrode line and an one source pole and a drain electrode, wherein this sweep trace and this grid electrically connect, this common electrode wire is positioned at this data line top, and this source electrode and this drain electrode are positioned on this channel semiconductor layer, and this source electrode electrically connects this data line;
Form a protective seam on this substrate, to cover this second patterning conductor layer; And
Form a pixel electrode on this protective seam, and this pixel electrode and this drain electrode electric connection, this common electrode wire and this pixel electrode part overlap and constitute a storage capacitors.
2. one pixel structure process method according to claim 1 is characterized in that, the method that forms this channel semiconductor layer comprises:
Form the semiconductor material layer on this gate insulator;
Carry out a doping process, form an ohmic contact layer with upper surface in this semiconductor material layer; And
This semiconductor material layer of patterning is to form this channel semiconductor layer.
3. one pixel structure process method according to claim 1 is characterized in that, the method that forms this gate insulator comprises:
Form one first dielectric layer on this substrate; And
Form one first contact hole and one second contact hole in this first dielectric layer, with the subregion that exposes this grid respectively and the subregion of this data line.
4. one pixel structure process method according to claim 3 is characterized in that, this sweep trace electrically connects by this first contact hole and this grid and this source electrode electrically connects by this second contact hole and this data line.
5. one pixel structure process method according to claim 1 is characterized in that, the method that forms this protective seam comprises:
Form one second dielectric layer on this substrate, and cover this second patterning conductor layer; And
Form one the 3rd contact hole in this second dielectric layer, to expose the subregion of this drain electrode.
6. one pixel structure process method according to claim 5 is characterized in that, this pixel electrode electrically connects by the 3rd contact hole and this drain electrode.
7. one pixel structure process method according to claim 1 is characterized in that, also is included in when forming this first patterning conductor layer, and formation one is positioned at the articulamentum of a side of this grid.
8. one pixel structure process method according to claim 7, it is characterized in that, also be included in and form behind this channel semiconductor layer and form before this second patterning conductor layer, form one the 4th contact hole in this gate insulator, to expose this articulamentum of part, so that after this second patterning conductor layer formation, this drain electrode electrically connects by the 4th contact hole and this articulamentum.
9. one pixel structure process method according to claim 8; it is characterized in that; also be included in and form behind this protective seam and form before this pixel electrode; form one the 5th contact hole in this protective seam and this gate insulator; to expose this articulamentum of part; and make after this pixel electrode formation, this pixel electrode electrically connects this articulamentum by the 5th contact hole.
10. a dot structure is suitable for being disposed on the substrate, it is characterized in that, this dot structure comprises:
One first patterning conductor layer is disposed on this substrate, and this first patterning conductor layer comprises a grid and a data line;
One gate insulator covers this first patterning conductor layer;
The semiconductor channel layer is disposed on this gate insulator of this grid top;
One second patterning conductor layer, be disposed on this gate insulator and this channel semiconductor layer, this second patterning conductor layer comprises one scan line, a common electrode line and an one source pole and a drain electrode, this sweep trace and this grid electrically connect, this common electrode wire is positioned at this data line top, and this source electrode and this drain electrode are positioned on this channel semiconductor layer, and this source electrode electrically connects this data line;
One protective seam covers this second patterning conductor layer; And
One pixel electrode is disposed on this protective seam, and this pixel electrode and this drain electrode electric connection, and this common electrode wire and this pixel electrode part overlap and constitute a storage capacitors.
11. dot structure according to claim 10 is characterized in that, this gate insulator has one first contact hole and one second contact hole, lays respectively at this grid and this data line top.
12. dot structure according to claim 11 is characterized in that, this sweep trace electrically connects by this first contact hole and this grid and this source electrode electrically connects by this second contact hole and this data line.
13. dot structure according to claim 10 is characterized in that, this protective seam has one the 3rd contact hole, is positioned at this drain electrode top, and this pixel electrode electrically connects by the 3rd contact hole and this drain electrode.
14. dot structure according to claim 10 is characterized in that, this first patterning conductor layer also comprises an articulamentum, is positioned at this drain electrode and this pixel electrode below.
15. dot structure according to claim 14 is characterized in that, this gate insulator has one the 4th contact hole, so that this drain electrode electrically connects this articulamentum by the 4th contact hole.
16. dot structure according to claim 14 is characterized in that, this this protective seam and this gate insulator have one the 5th contact hole, so that this pixel electrode electrically connects this articulamentum by the 5th contact hole.
17. a dot structure is suitable for being disposed on the substrate, it is characterized in that, this dot structure comprises:
One first patterning conductor layer is disposed on this substrate, and this first patterning conductor layer comprises a grid and an articulamentum at least;
One gate insulator covers this first patterning conductor layer;
The semiconductor channel layer is disposed on this gate insulator of this grid top;
One second patterning conductor layer, be disposed on this gate insulator and this channel semiconductor layer, this second patterning conductor layer comprises an one source pole and a drain electrode at least, it is characterized in that a common data line and the one scan line that constitutes a thin film transistor (TFT) and electrically connect of this first patterning conductor layer, this channel semiconductor layer and this second patterning conductor layer with this thin film transistor (TFT);
One protective seam covers this second patterning conductor layer; And
One pixel electrode is disposed on this protective seam, and this pixel electrode electrically connects by this articulamentum and this drain electrode.
18. dot structure according to claim 17, it is characterized in that, this data line comprises one first line segment and one second line segment, and this first line segment is made of this first patterning conductor layer of part, and this second line segment is made of this second patterning conductor layer and with the electric connection of this first line segment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101401381A CN100514168C (en) | 2007-04-05 | 2007-08-06 | Pixel structure and its manufacturing method |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710093727.9 | 2007-04-05 | ||
| CN 200710093727 CN101030555A (en) | 2007-04-05 | 2007-04-05 | Pixel structure and its production |
| CNB2007101401381A CN100514168C (en) | 2007-04-05 | 2007-08-06 | Pixel structure and its manufacturing method |
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| CN100514168C true CN100514168C (en) | 2009-07-15 |
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| CN103969902B (en) * | 2013-01-25 | 2017-04-12 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof, as well as liquid crystal display device |
| KR102081599B1 (en) * | 2013-06-28 | 2020-02-26 | 엘지디스플레이 주식회사 | Array substrate for Liquid Crystall Display Device and methode for fabricating the same |
| TWI662526B (en) * | 2018-05-02 | 2019-06-11 | 友達光電股份有限公司 | Semiconductor structure and pixel structure |
| CN115101024B (en) * | 2022-07-07 | 2023-07-21 | 惠科股份有限公司 | Pixel structure, array substrate and display panel |
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