CN217655405U

CN217655405U - Array substrate, display panel and display device

Info

Publication number: CN217655405U
Application number: CN202221514896.1U
Authority: CN
Inventors: 黄世帅; 郑浩旋
Original assignee: HKC Co Ltd; Chuzhou HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chuzhou HKC Optoelectronics Technology Co Ltd
Priority date: 2022-06-16
Filing date: 2022-06-16
Publication date: 2022-10-25
Anticipated expiration: 2032-06-16

Abstract

The utility model belongs to the technical field of display panel, especially, relate to an array substrate, display panel and display device, wherein, array substrate includes many data lines, many scanning lines and pixel array, the pixel array includes the sub-pixel that the array was arranged, the source electrode of each sub-pixel's charge sharing thin film transistor passes through conducting structure and is connected with adjacent another polarity opposite data line, discharge through another adjacent data line, need not to set up the common electrode who runs through the structure on the array substrate, the aperture ratio of array substrate has been promoted, and simultaneously, discharge to another adjacent data line, can reduce the voltage of current sub-pixel, make current sub-pixel's main pixel and sub-pixel present bright and dark change, realize the multi-domain display effect, display panel's display effect has been promoted.

Description

Array substrate, display panel and display device

Technical Field

The application belongs to the technical field of display panels, and particularly relates to an array substrate, a display panel and a display device.

Background

With the continuous development of display technology, the quality demand of people for display screens is also increasing, wherein the demand for large viewing angles is particularly obvious, so that companies adopt various ways to increase the large viewing angles, and the multi-domain pixel structure is generated.

In the multi-domain pixel structure, a pixel electrode is divided into a plurality of display domains in different directions, and the space of an array substrate is limited.

Meanwhile, in order to improve visual color difference or visual color shift, the sub-pixels are generally divided into a main pixel and a sub-pixel, the main pixel and the sub-pixel are sequentially arranged along a row direction, the main pixel comprises a main pixel electrode and a main thin film transistor, the sub-pixel comprises a sub-pixel electrode, a sub-thin film transistor and a charge sharing thin film transistor, the main thin film transistor charges the main pixel electrode, the sub-thin film transistor charges the sub-pixel electrode, and the charge sharing thin film transistor discharges the sub-pixel electrode, so that the main pixel and the sub-pixel generate different potentials to increase a viewing angle, wherein the charge sharing thin film transistor is connected with a common electrode on the array substrate, and the common electrode is caused to penetrate through the charge sharing thin film transistors connected to each column through the discharge of the common electrode, and the aperture ratio of the array substrate is reduced.

SUMMERY OF THE UTILITY MODEL

The present disclosure provides an array substrate, in which a charge-sharing thin film transistor is connected to adjacent data lines of opposite polarities, so as to increase an aperture ratio of the array substrate.

A first aspect of the embodiments of the present application provides an array substrate, including a plurality of data lines, a plurality of scan lines, and a pixel array, where the plurality of data lines are used to input data signals with opposite polarities, the scan lines are used to input row-by-row start signals, the pixel array includes sub-pixels arranged in an array, and each sub-pixel includes a main pixel and a sub-pixel connected to the same data line and the same scan line, respectively;

the main pixel comprises a main pixel electrode and a main thin film transistor, and the main pixel electrode is correspondingly connected with the data line and the scanning line through the main thin film transistor; the sub-pixel comprises a sub-pixel electrode, a sub-thin film transistor and a charge sharing thin film transistor; the sub pixel electrode is correspondingly connected with the data line and the scanning line through the sub thin film transistor;

the grid electrode of the charge sharing thin film transistor is connected with the corresponding scanning line, the drain electrode of the charge sharing thin film transistor is connected with the sub-pixel electrode, and the source electrode of the charge sharing thin film transistor is connected with the adjacent other data line through a conductive structure.

Optionally, each of the sub-pixels further includes a routing area, and the routing area is located between the main pixel electrode and the sub-pixel electrode of each of the sub-pixels;

the scanning line, the main thin film transistor, the secondary thin film transistor and the charge sharing thin film transistor are correspondingly arranged in the wiring area.

Optionally, the main thin film transistor and the sub thin film transistor are disposed close to a data line to which the current sub-pixel is connected, and the charge sharing thin film transistor is disposed close to another adjacent data line and connected to another adjacent data line through a conductive structure.

Optionally, the conductive structure and the data line are disposed in the same layer, and the data line and the scan line are disposed in different layers.

Optionally, the conductive structure is connected to the corresponding data line along the upper part of the scanning line;

or connected to the corresponding data lines in a layered staggered manner with the scanning lines.

Optionally, a main pixel electrode and a sub-pixel electrode of each sub-pixel are oppositely provided with a notch, respectively, the notch is arranged near the data line and the wiring area, and a via hole is arranged at a position corresponding to each notch;

the main thin film transistor is connected with the main pixel electrode through a through hole, and the secondary thin film transistor and the charge sharing thin film transistor are connected with the secondary pixel electrode through a through hole.

Optionally, the main pixel electrode and the sub-pixel electrode respectively include four display domains;

the data line connected close to the current sub-pixel in the main pixel electrode and a display domain close to the wiring area are provided with the unfilled corner;

and the data line connected close to the current sub-pixel in the sub-pixel electrode and a display domain close to the wiring area are provided with the unfilled corner.

Optionally, the array substrate further includes:

the first common electrode, every said main pixel electrode overlaps with the edge part of said first common electrode and forms the main storage capacitance, every said secondary pixel electrode overlaps with the edge part of said first common electrode and forms the secondary storage capacitance;

the conductive structure is arranged in a different layer from the first common electrode.

A second aspect of the embodiments of the present application provides a display panel, including a color film substrate, a liquid crystal layer, and the array substrate as described above, where the liquid crystal layer is disposed between the color film substrate and the array substrate.

A third aspect of the embodiments of the present application provides a display device, which includes a backlight module, a display panel driving circuit, and the display panel as described above, where the display panel driving circuit is correspondingly connected to the display panel, and the backlight module is disposed opposite to the display panel.

Compared with the prior art, the embodiment of the application has the advantages that: in the array substrate, a source electrode of a charge sharing thin film transistor of each sub-pixel is connected with another adjacent data line with opposite polarity through a conductive structure, and discharges through another adjacent data line, a common electrode penetrating through the structure is not required to be arranged on the array substrate, so that the aperture opening ratio of the array substrate is improved, and meanwhile, another adjacent data line discharges, the voltage of the current sub-pixel can be reduced, the main pixel and the sub-pixel of the current sub-pixel show brightness change, the multi-domain display effect is realized, and the display effect of the display panel is improved.

Drawings

Fig. 1 is a first circuit schematic diagram of an array substrate according to an embodiment of the present disclosure;

fig. 2 is a second circuit schematic diagram of an array substrate according to an embodiment of the present disclosure;

fig. 3 is a schematic view of a first structure of an array substrate according to a second embodiment of the present application;

fig. 4 is a schematic view of a second structure of an array substrate according to a second embodiment of the present application;

fig. 5 is a schematic structural diagram of an array substrate according to a third embodiment of the present application;

fig. 6 is a schematic structural diagram of a via hole in an array substrate according to a third embodiment of the present application;

fig. 7 is a schematic view of a second structure of a via hole in an array substrate according to a third embodiment of the present application;

fig. 8 is a schematic structural diagram of a display panel according to a fourth embodiment of the present application;

fig. 9 is a schematic structural diagram of a display device according to a fifth embodiment of the present application.

Wherein, each reference mark in the figure is:

100-display panel, 200-display panel driving circuit, 300-backlight module, 1-array substrate, 2-color film substrate, 3-liquid crystal layer, 10-sub-pixel, 20-data line, 30-scanning line, 11-main pixel, 12-sub-pixel, 13-conductive structure, 14-wiring area, 15-via hole, 111-main pixel electrode, 112-first common electrode, 121-sub-pixel electrode, 114-conductive film, T1-main thin film transistor T1, T2-sub thin film transistor, T3-charge sharing thin film transistor, C1-main liquid crystal capacitor, C2-sub-liquid crystal capacitor and CF _ COM-color film substrate common electrode.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Example one

A first aspect of the embodiments of the present application provides an array substrate 1.

The array substrate 1 comprises a plurality of data lines 20, a plurality of scanning lines 30 and a pixel array, wherein the data lines 20 are arranged at intervals along the horizontal direction, the scanning lines 30 are sequentially arranged along the vertical direction, the data lines 20 and the scanning lines 30 are arranged in a crossed manner, the data lines 20 are used for inputting data signals with opposite polarities, the scanning lines 30 are used for inputting row-by-row starting signals, the pixel array comprises sub-pixels 10 arranged in an array, and the sub-pixels 10 are correspondingly connected with the data lines 20 and the scanning lines 30 and are controlled to be charged or discharged.

As shown in fig. 1 or fig. 2, each sub-pixel 10 includes a main pixel 11 and a sub-pixel 12 connected to the same data line 20 and the same scan line 30, respectively;

the main pixel 11 includes a main pixel electrode 111 and a main thin film transistor T1, the main pixel electrode 111 is correspondingly connected to the data line 20 and the scan line 30 through the main thin film transistor T1; the sub-pixel 12 includes a sub-pixel electrode 121, a sub-thin film transistor T2, and a charge sharing thin film transistor T3; the sub-pixel electrode 121 is correspondingly connected with the data line 20 and the scanning line 30 through a sub-thin film transistor T2;

the gate of the charge-sharing tft T3 is connected to the corresponding scan line 30, the drain of the charge-sharing tft T3 is connected to the sub-pixel electrode 121, and the source of the charge-sharing tft T3 is connected to another adjacent data line 20 through the conductive structure 13.

In this embodiment, the gate of the main thin film transistor T1 is connected to the scan line 30 corresponding to the sub-pixel 10, the source of the main thin film transistor T1 is connected to the data line 20 corresponding to the sub-pixel 10, the drain of the main thin film transistor T1 is connected to the main pixel electrode 111, and the main pixel electrode 111 and the common electrode CF _ COM of the color filter substrate 2 form a main liquid crystal capacitor C1.

The gate of the sub-thin film transistor T2 is connected to the scan line 30 corresponding to the sub-pixel 10, the source of the sub-thin film transistor T2 is connected to the data line 20 corresponding to the sub-pixel 10, the drain of the sub-thin film transistor T2 is connected to the sub-pixel electrode 121, and the sub-pixel electrode 121 and the common electrode CF _ COM of the color filter substrate 2 form a sub-liquid crystal capacitor C2.

The gate of the charge-sharing tft T3 is connected to the corresponding scan line 30 of the sub-pixel 10, the drain of the charge-sharing tft T3 is connected to the sub-pixel electrode 121 of the sub-pixel 10, and the source of the charge-sharing tft T3 is connected to another adjacent data line 20 with opposite polarity through the conductive structure 13, for example, as shown in fig. 1, the current sub-pixel 10 is connected to the nth data line 20, the charge-sharing tft T3 of the current sub-pixel 10 is connected to the (n-1) th data line 20, or as shown in fig. 2, is connected to the (n + 1) th data line 20, wherein, as shown in fig. 3, the adjacent data lines 20 have opposite polarity, that is, the polarity of the data signal on the (n-1) th data line 20 is opposite to that on the nth data line 20, and the polarity of the data signal on the nth data line 20 is opposite to that on the (n + 1) th data line 20.

The sub-pixels 10 in the row and the sub-pixels 10 in the other row in the same column are sequentially driven row by row, that is, the sub-pixels 10 in the row input a row start signal in the front, the sub-pixels 10 in the other row input a row start signal in the back, so that the corresponding thin film transistors are sequentially turned on row by row and corresponding data signals are input, and thus the main thin film transistor T1 charges the main pixel electrode 111, the sub-thin film transistor T2 charges the sub-pixel electrode 121, and the charge sharing thin film transistor T3 discharges the sub-pixel electrode 121, so that the main pixel 11 and the sub-pixels 12 generate different potentials to increase the viewing angle.

The charge-sharing thin film transistor T3 realizes the discharge operation through another adjacent data line 20, and referring to fig. 3, a common electrode penetrating through the structure does not need to be arranged on the array substrate 1, thereby increasing the aperture ratio of the array substrate 1.

Meanwhile, the discharge is performed on another adjacent data line 20, so that the driving voltage of the current sub-pixel 12 can be reduced, and the main pixel 11 and the sub-pixel 12 of the current sub-pixel 10 are changed in brightness, thereby realizing a multi-domain display effect and improving the display effect of the display panel.

The connection mode of the conductive structure 13 and another adjacent data line 20 can be selected correspondingly according to the layout modes of the data line 20, the scan line 30, and the pixel electrode, for example, the via 15 or direct connection, and the specific mode is not limited.

Meanwhile, the conductive structure 13 may be made of a corresponding type of material, and in order to ensure the display effect and the discharge effect, the conductive structure 13 is an Indium Tin oxide semiconductor (ITO) transparent conductive film.

The main pixel electrode 111 and the sub-pixel electrode 121 respectively include a plurality of display domains, which may include two display domains, four display domains, and the like, wherein when the two display domains are included, the display panel 100 has a four-domain pixel structure, and when the four display domains are included, the display panel 100 has an eight-domain pixel structure.

In order to improve the viewing angle performance of the panel, in an embodiment of the present invention, the main pixel electrode 111 and the sub-pixel electrode 121 respectively include four display domains, and the rotation angles of the liquid crystal molecules of the four display domains of the main pixel electrode 111 and the four display domains of the sub-pixel electrode 121 are different, so as to improve color shift, and the eight-domain pixel structure may be a PSVA (polymer Stabilized vertical alignment) pixel.

Meanwhile, optionally, the array substrate 1 further includes:

the first common electrode 112, the edge part of every main pixel electrode 111 and first common electrode 112 overlaps and forms the main storage capacitance, every secondary pixel electrode 121 overlaps and forms the secondary storage capacitance with the edge part of first common electrode 112;

the conductive structure 13 is disposed in a different layer from the first common electrode 112.

In this embodiment, the main pixel electrodes 111 and the first common electrode 112 are partially overlapped to form a main storage capacitor, the sub pixel electrodes 121 and the first common electrode 112 are partially overlapped to form a sub storage capacitor, so as to ensure that the sub pixels 10 normally display the image when the main thin film transistor T1 and the sub thin film transistor T2 are turned off, the common electrode voltage signals with the same size are connected to the first common electrodes 112, so as to ensure the stability of the common electrode voltage signals, and the voltage signals of the first common electrode 112 on the array substrate 1 and the common electrode CF _ COM on the color film substrate 2 are the same, so that irregular electric fields at the edges of the pixels are shielded, and dark fringes caused by disordered liquid crystal molecule guiding are avoided.

Compared with the prior art, the embodiment of the application has the advantages that: in the array substrate 1, the source of the charge-sharing thin film transistor T3 of each sub-pixel 10 is connected to another adjacent data line 20 with opposite polarity through the conductive structure 13, and discharges through another adjacent data line 20, and a common electrode penetrating through the structure does not need to be arranged on the array substrate 1, so that the aperture ratio of the array substrate 1 is improved, and meanwhile, discharging is performed on another adjacent data line 20, so that the voltage of the current sub-pixel 12 can be reduced, and the main pixel 11 and the sub-pixel 12 of the current sub-pixel 10 are changed in brightness and darkness, so that a multi-domain display effect is realized, and the display effect of the display panel is improved.

Example two

The refinement and optimization are performed based on the first embodiment, as shown in fig. 3, wherein each sub-pixel 10 further includes a routing area 14, and the routing area 14 is located between the main pixel electrode 111 and the sub-pixel electrode 121 of each sub-pixel 10;

the scanning line 30, the main thin film transistor T1, the sub thin film transistor T2 and the charge sharing thin film transistor T3 are correspondingly disposed in the wiring area 14, each wiring area 14 traverses the middle area of the main pixel electrode 111 and the sub pixel electrode 121 of each row of the sub pixels 10 to form the wiring area 14 of the adjacent row, and the scanning line 30 does not need to be bent along the row direction, thereby simplifying the manufacturing process of the array substrate 1.

Optionally, in order to simplify the circuit structure on the array substrate 1, the main thin film transistor T1 and the sub thin film transistor T2 are disposed close to the data line 20 connected to the current sub-pixel 10, the charge sharing thin film transistor T3 is disposed close to another data line 20 and connected to another data line 20 through the conductive structure 13, the main thin film transistor T1 and the sub thin film transistor T2 are connected to the data line 20 and the scan line 30 corresponding to the current sub-pixel 10 through the conductive film 114, meanwhile, the charge sharing thin film transistor T3 is connected to the data line 20 corresponding to the adjacent sub-pixel 10, and the distance between the thin film transistor T and the corresponding data line 20 is shortened, thereby avoiding cross-line connection and simplifying the routing structure of the routing area 14.

Meanwhile, the conductive structure 13 and the data line 20 may be connected by using a via 15 or directly according to the corresponding circuit layer position, optionally, the conductive structure 13 and the data line 20 are arranged on the same layer, the data line 20 and the scan line 30 are arranged on different layers, the conductive structure 13 is directly connected with the data line 20 on the same layer, and the via 15 is not needed, so that the aperture ratio of the array substrate 1 is improved, and meanwhile, the conductive structure 13 and the data line 20 are distributed between layers, optionally, the conductive structure 13 is connected to the corresponding data line 20 along the upper side of the scan line 30, the data line 20 and the conductive structure 13 are located on the upper layer of the scan line 30, and the conductive structure 13 is directly connected with the data line 20 along the upper side of the scan line 30, so that the length of the conductive structure 13 is reduced, and the manufacturing process of the array substrate 1 is simplified.

Or the conductive structure 13 and the scan line 30 are connected to the corresponding data line 20 in a staggered manner, so that the electrical coupling between the scan line 30 and the conductive structure 13 is reduced, and the influence of parasitic capacitance on the display effect is avoided.

EXAMPLE III

Thinning and optimizing based on the second embodiment, as shown in fig. 5, optionally, a main pixel electrode 111 and an electrode of the sub-pixel 10 of each sub-pixel 10 are oppositely provided with a notch, the notch is arranged adjacent to the data line 20 and the routing area 14, and a via hole 15 is arranged at a position corresponding to each notch;

the main thin film transistor T1 is connected to the main pixel electrode 111 through the via 15 using the conductive film 114, and the sub thin film transistor T2 and the charge sharing thin film transistor T3 are connected to the sub pixel electrode 121 through the via 15 after being connected in common using the conductive film 114.

In this embodiment, the main pixel electrode 111 and the sub-pixel electrode 121 are disposed on the same layer and are disposed on different layers from the tft, so that a via hole 15 is needed to connect the pixel electrode and the tft, and meanwhile, in order to dispose the via hole 15 and not to affect the wiring of the wiring area 14, a corner is disposed on the corresponding pixel electrode to accommodate the via hole 15, and meanwhile, since there is no first common electrode 112 penetrating through the structure in the array substrate 1 and the tft T3 is directly connected to the adjacent data line 20, the via hole 15 is not needed to be disposed between the corresponding tft T3 and the adjacent data line 20, the arrangement of the via hole 15 is reduced, and the aperture ratio of the array substrate 1 is improved.

As shown in fig. 6 and 7, corresponding to the layout manner that the data line 20, the conductive film 114, and the conductive structure 13 are located below the pixel electrode, the main pixel electrode 111 is connected to the conductive film 114 below through a via 15, the conductive film 114 is connected to the main tft T1, the sub-pixel electrode 121 is connected to the conductive film 114 below through a via 15, and the conductive films 114 are respectively connected to the sub-tft T2 and the charge sharing tft T3 to realize the connection of the via 15.

Corresponding to the eight-domain structure of the array substrate 1, and in order to simplify the structure of the conductive film 114 connecting the via hole 15 and the thin film transistor, a data line 20 connected to the current sub-pixel 10 and a display domain adjacent to the routing region 14 in the main pixel electrode 111 are provided with a notch;

a data line 20 connected to the sub-pixel 10 and a display domain adjacent to the routing area 14 in the sub-pixel electrode 121 are provided with a notch, two via holes 15 are provided at the notches of the two display domains corresponding to the data line 20 connected to the sub-pixel 10, the length of the conductive film 114 for connecting the via holes 15 and the thin film transistor is shortened, and a cross-line structure is not provided between the conductive structure 13, so that the manufacturing process of the array substrate 1 is simplified.

Example four

The present application further provides a display panel 100, as shown in fig. 8, the display panel 100 includes a color film substrate 2, a liquid crystal layer 3, and an array substrate 1, and the specific structure of the array substrate 1 refers to the above embodiments, and since the display panel 100 adopts all technical solutions of all the above embodiments, the display panel at least has all beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated here.

In this embodiment, the color filter substrate 2 includes an upper polarizer, a color filter, a common electrode CF _ COM, and an upper alignment layer, and the array substrate 1 includes a lower alignment layer, a driving layer, and a lower polarizer, where the driving layer is a thin film transistor driving layer, the driving layer is used to drive liquid crystal molecules of the liquid crystal layer 3 in cooperation with the common electrode layer, and the array substrate 1 is provided with a corresponding data line 20, a corresponding scan line 30, a corresponding pixel array, and a corresponding first common electrode.

EXAMPLE five

The present application further provides a display device, as shown in fig. 9, the display device includes a backlight module 300, a display panel driving circuit 200, and a display panel 100, and the specific structure of the display device refers to the above embodiments. The display panel driving circuit 200 is correspondingly connected to the display panel 100, and the backlight module 300 is disposed opposite to the display panel 100.

In this embodiment, the display panel driving circuit 200 includes a source driving circuit, a gate driving circuit, and a common electrode voltage circuit, and may further include a timing controller and a power management integrated circuit required for driving, where the timing controller controls the source driving circuit and the gate driving circuit to scan line by line, and at the same time, the common electrode voltage circuit obtains an analog voltage output by the power management integrated circuit, converts the analog voltage into a common electrode voltage signal with a corresponding size, and outputs the common electrode voltage signal to the common electrode CF _ COM of the color film substrate 2 through the structures such as the array substrate 1, and outputs the common electrode voltage signal to the first common electrode 112 on the array substrate 1, and the common electrode voltage signal on the common electrode CF _ COM of the color film substrate 2 and the data signal output by the source driving circuit cooperate to drive liquid crystal molecules, and cooperate with the backlight module 300 to display corresponding image information.

The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. An array substrate comprises a plurality of data lines, a plurality of scanning lines and a pixel array, wherein the data lines are used for inputting data signals with opposite polarities in a staggered mode, the scanning lines are used for inputting row opening signals row by row, the pixel array comprises sub-pixels arranged in an array mode, and each sub-pixel comprises a main pixel and a sub-pixel which are respectively connected with the same data line and the same scanning line;

the main pixel comprises a main pixel electrode and a main thin film transistor, and the main pixel electrode is correspondingly connected with the data line and the scanning line through the main thin film transistor; the sub-pixel comprises a sub-pixel electrode, a sub-thin film transistor and a charge sharing thin film transistor; the sub pixel electrode is correspondingly connected with the data line and the scanning line through the sub thin film transistor; the method is characterized in that:

the grid electrode of the charge sharing thin film transistor is connected with the corresponding scanning line, the drain electrode of the charge sharing thin film transistor is connected with the sub-pixel electrode, and the source electrode of the charge sharing thin film transistor is connected with the other adjacent data line through a conductive structure.

2. The array substrate of claim 1, wherein each of the sub-pixels further comprises a routing area, the routing area being located between the main pixel electrode and the sub-pixel electrode of each of the sub-pixels;

3. The array substrate of claim 2, wherein the main thin film transistor and the sub thin film transistor are disposed adjacent to a data line to which a current sub-pixel is connected, and the charge-sharing thin film transistor is disposed adjacent to another data line and connected to another data line through a conductive structure.

4. The array substrate of claim 3, wherein the conductive structures are disposed on the same layer as the data lines, and the data lines are disposed on different layers from the scan lines.

5. The array substrate of claim 4, wherein the conductive structures are connected to the corresponding data lines along the upper portion of the scan lines;

6. The array substrate according to claim 2, wherein a notch is oppositely arranged on the main pixel electrode and the sub-pixel electrode of each sub-pixel, the notch is arranged adjacent to the data line and the wiring area, and a via hole is arranged at a position corresponding to each notch;

the main thin film transistor is connected with the main pixel electrode through a via hole, and the secondary thin film transistor and the charge sharing thin film transistor are connected with the secondary pixel electrode through via holes.

7. The array substrate of claim 6, wherein the main pixel electrode and the sub pixel electrode respectively comprise four display domains;

8. The array substrate of claim 5, wherein the array substrate further comprises:

the first common electrode, every said main pixel electrode and said first common electrode edge part overlap and form the main storage capacitance, every said sub pixel electrode and said first common electrode edge part overlap and form the sub storage capacitance;

9. A display panel, comprising a color filter substrate, a liquid crystal layer and the array substrate according to any one of claims 1 to 8, wherein the liquid crystal layer is located between the color filter substrate and the array substrate.

10. A display device, comprising a backlight module, a display panel driving circuit and the display panel as claimed in claim 9, wherein the display panel driving circuit is connected to the display panel correspondingly, and the backlight module is disposed opposite to the display panel.