CN215769283U - Array substrate and reflective display panel - Google Patents
Array substrate and reflective display panel Download PDFInfo
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- CN215769283U CN215769283U CN202120274558.4U CN202120274558U CN215769283U CN 215769283 U CN215769283 U CN 215769283U CN 202120274558 U CN202120274558 U CN 202120274558U CN 215769283 U CN215769283 U CN 215769283U
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Abstract
The application discloses display panel of array substrate and reflective belongs to and shows technical field. The array substrate includes: the liquid crystal display device comprises a substrate, a plurality of data lines and a plurality of sub-pixels, wherein the data lines and the sub-pixels are positioned on the substrate. Each sub-pixel may include: a reflective pixel electrode and a TFT. The orthographic projection of the pixel electrode in each sub-pixel on the substrate is overlapped with the orthographic projection of the first pole, the first data line and the second data line, so that the orthographic projection area of the pixel electrodes in the array substrate on the substrate is larger, and the display effect of the reflective display panel where the array substrate is located is better.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to an array substrate and a reflective display panel.
Background
With the development of display technologies, various display panels have appeared. The reflective display panel can display an image without a backlight.
The reflective display panel may generally include: the liquid crystal display panel comprises an array substrate, a color film substrate and a liquid crystal layer, wherein the array substrate and the color film substrate are oppositely arranged, and the liquid crystal layer is positioned in the array substrate and the color film substrate. The array substrate may include: the display device comprises a substrate and a plurality of pixel electrodes positioned on the substrate, wherein the pixel electrodes are made of a metal material with light reflecting property. In this way, the plurality of pixel electrodes can reflect ambient light, so that the reflective display panel can display images without a backlight source.
However, the area of the orthographic projection of the pixel electrode on the substrate in the conventional array substrate is small, which affects the display effect of the reflective display panel.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides an array substrate and a reflective display panel. The problem that the display effect of the existing reflective display panel is poor can be solved, and the technical scheme is as follows:
in one aspect, an array substrate is provided, including:
a substrate; a plurality of data lines and a plurality of sub-pixels on the substrate, each of the sub-pixels including: the first pole of the thin film transistor is connected with one data line, and the second pole of the thin film transistor is connected with the pixel electrode;
the data line comprises a first data line and a second data line, the first data line is connected with the first pole of the thin film transistor in the sub-pixel, and the second data line is connected with the first pole of the thin film transistor in the sub-pixel adjacent to the sub-pixel;
wherein, on the substrate, a first overlapping area exists between the orthographic projection of the pixel electrode in the sub-pixel and the orthographic projection of the first electrode of the thin film transistor in the sub-pixel and the first data line connected with the first electrode, and a second overlapping area exists between the orthographic projection of the pixel electrode in the sub-pixel and the orthographic projection of the second data line.
Optionally, a portion of the pixel electrode corresponding to the first overlapping region and a portion of the first electrode and the first data line connected to each other corresponding to the first overlapping region form a first parasitic capacitance, a portion of the pixel electrode corresponding to the second overlapping region and a portion of the second data line corresponding to the second overlapping region form a second parasitic capacitance, and a capacitance value of the first parasitic capacitance is equal to a capacitance value of the second parasitic capacitance.
Optionally, the first electrode and the second electrode of the thin film transistor are arranged in the same layer as the plurality of data lines and are made of the same material;
on the substrate, the area of a first overlapping region where the orthographic projection of the pixel electrode overlaps with the orthographic projection of the first electrode and the first data line which are connected with each other is a first area;
on the substrate, the area of a second overlapping region where the orthographic projection of the pixel electrode and the orthographic projection of the second data line overlap is a second area;
the first area is equal to the second area.
Optionally, the plurality of sub-pixels are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction, and the data lines extend along the second direction on the substrate as a whole;
the plurality of sub-pixels include a first sub-pixel and a second sub-pixel which are located in the same row and adjacent to each other, and the data line has: a first portion extending into the first sub-pixel and covered by a pixel electrode in the first sub-pixel, and a second portion extending into the second sub-pixel and covered by a pixel electrode in the second sub-pixel, an orthographic projection of the first portion on the substrate being within the first overlap region in the first sub-pixel, an orthographic projection of the second portion on the substrate being within the second overlap region in the second sub-pixel.
Optionally, the data line includes: the device comprises a plurality of linear extending parts and a plurality of curved extending parts which are connected in sequence, wherein each curved extending part is provided with an opening;
the plurality of linear extending parts are all positioned between a first sub-pixel column and a second sub-pixel column, the first sub-pixel column is a column of sub-pixels comprising the first sub-pixels, and the second sub-pixel column is a column of sub-pixels comprising the second sub-pixels; the first portion includes at least one of the curvilinear extensions, the second portion includes at least one of the curvilinear extensions, and the direction of the opening of the curvilinear extension in the first portion is opposite the direction of the opening of the curvilinear extension in the second portion.
Optionally, the data line includes: the first linear extension parts and the second linear extension parts are connected in sequence, the first linear extension parts and the second linear extension parts are arranged in a staggered mode one by one, and the extending directions of any two connected first linear extension parts and the second linear extension parts are intersected;
the plurality of sub-pixels are arranged in a plurality of columns, and in two adjacent first linear extending parts in the same data line on the substrate, the orthographic projection of one first linear extending part is overlapped with the orthographic projection of the pixel electrode in a first sub-pixel column, and the orthographic projection of the other first linear extending part is overlapped with the orthographic projection of the pixel electrode in a second sub-pixel column;
on the substrate, the orthographic projection of the second straight extension part in the data line is respectively overlapped with the orthographic projection of the pixel electrode in the first sub-pixel column and the orthographic projection of the pixel electrode in the second sub-pixel column;
the first sub-pixel column is a column of sub-pixels including the first sub-pixel, and the second sub-pixel column is a column of sub-pixels including the second sub-pixel;
the extending directions of the first linear extending parts are all parallel to the second direction, and the extending directions of the second linear extending parts are all parallel to the first direction.
Optionally, in two adjacent first linear extensions in the same data line, one of the first linear extensions is connected to a first electrode of a thin film transistor in the first subpixel row, and on the substrate, an orthogonal projection of one of the first linear extensions overlaps with an orthogonal projection of two adjacent pixel electrodes in the first subpixel row, respectively, and on the substrate, an orthogonal projection of another of the first linear extensions is located in an orthogonal projection of one pixel electrode in the second subpixel row and is spaced from the orthogonal projection of the thin film transistor.
Optionally, on the substrate, the pixel electrode covers the thin film transistor connected thereto and covers the data line connected thereto, while covering a part of the data lines of the adjacent sub-pixels.
Optionally, the pixel electrodes are rectangular, the data line extends along one direction as a whole and is covered by the pixel electrodes of the sub-pixels in the same column, a part of the data line passing through one pixel electrode has a part extending to an adjacent sub-pixel, and the part extending to the adjacent sub-pixel is covered by the pixel electrode of the adjacent sub-pixel.
Optionally, on the substrate, the data line is a straight line extending along the column direction in the sub-pixel connected to the data line, and extends along the column direction in the adjacent sub-pixel as a whole, and is a local straight line, a local curve, or a local broken line; the extended parts in the two sub-pixels are connected by a connecting line; alternatively, the first and second electrodes may be,
the data line is a curve or a broken line extending along the column direction in the sub-pixel connected with the data line, and the data line is a whole extending along the column direction in the adjacent sub-pixel and is a local straight line, a broken line or a curve; the extended portions within the two sub-pixels are connected by a connection line.
Optionally, each of the pixel electrodes in the plurality of sub-pixels is distributed in an array, and in the first direction or the second direction, a distance between any two adjacent pixel electrodes is equal.
Optionally, the first pole includes a U-shaped structure, the second pole includes a bar structure, one end of the second pole is located in the U-shaped structure, and the other end of the second pole is connected to the pixel electrode.
Optionally, the array substrate further includes: a first auxiliary electrode connected to the second electrode, a second auxiliary electrode located on a side of the first auxiliary electrode away from the pixel electrode, and a first insulating layer located between the first auxiliary electrode and the second auxiliary electrode;
wherein, on the substrate, a forward projection of the first auxiliary electrode overlaps with a forward projection of the second auxiliary electrode.
Optionally, the first auxiliary electrode and the first and second poles are disposed in the same layer and made of the same material; the second auxiliary electrode and the grid electrode of the thin film transistor are arranged on the same layer and are made of the same material.
In another aspect, a reflective display panel is provided, including:
the liquid crystal display panel comprises an array substrate, a color film substrate and a liquid crystal layer, wherein the array substrate and the color film substrate are oppositely arranged, and the liquid crystal layer is positioned between the array substrate and the color film substrate.
The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:
the array substrate includes: the liquid crystal display device comprises a substrate, a plurality of data lines and a plurality of sub-pixels, wherein the data lines and the sub-pixels are positioned on the substrate. Each sub-pixel may include: a reflective pixel electrode and a TFT. The orthographic projection of the pixel electrode in each sub-pixel on the substrate is overlapped with the orthographic projection of the first pole, the first data line and the second data line, so that the orthographic projection area of the pixel electrodes in the array substrate on the substrate is larger, and the display effect of the reflective display panel where the array substrate is located is better. When the reflective display panel performs display in the column inversion mode, the polarities of voltages applied to the first data line and the second data line are opposite to each other. Under the action of the first parasitic capacitance and the second parasitic capacitance, the pulling action of the first data line and the second data line on the sub-pixel voltage loaded on the pixel electrode can be counteracted positively and negatively, and the display of the reflective display panel is not influenced. Therefore, on the premise that the display effect of the reflective display panel is not influenced by the parasitic capacitance, the orthographic projection area of the pixel electrodes on the substrate in the array substrate is increased, and the good display effect of the reflective display panel is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a top view of a conventional array substrate;
fig. 2 is a top view of an array substrate according to an embodiment of the present disclosure;
FIG. 3 is a schematic view of a film layer of the array substrate shown in FIG. 2 at A-A';
fig. 4 is a top view of another array substrate provided in the embodiments of the present application;
fig. 5 is a top view of another array substrate provided in an embodiment of the present application;
fig. 6 is a top view of another array substrate provided in an embodiment of the present application;
fig. 7 is a top view of an array substrate according to another embodiment of the present application;
FIG. 8 is a schematic view of a film structure of the array substrate shown in FIG. 7 at A-A';
FIG. 9 is an equivalent circuit diagram of a sub-pixel in a reflective display panel;
fig. 10 is a top view of another array substrate according to another embodiment of the present application;
fig. 11 is a schematic view of a film structure of a reflective display panel according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a top view of a conventional array substrate. The array substrate may include: the liquid crystal display panel comprises a substrate 01, and a plurality of data lines 02, a plurality of gate lines 03 and a plurality of sub-pixels 04 which are arranged on the substrate 01. Wherein each sub-pixel 04 may include: a pixel electrode 041 and a Thin Film Transistor (TFT) 042. The TFT 042 may include: a first pole 0421, a second pole 0422 and a gate 0423. The first electrode 0421 may be connected to one data line 02, the second electrode 0422 may be connected to the pixel electrode 041, and the gate electrode 0423 may be connected to one gate line 03. When the array substrate needs to be disposed in a reflective display panel, the pixel electrode 041 in the array substrate needs to be made of a reflective metal material.
Due to the display effect of the reflective display panel, the area of the orthographic projection of the plurality of pixel electrodes 041 in the array substrate on the substrate 01 is positively correlated. Therefore, in order to improve the display effect of the reflective display panel, it is necessary to increase the area of the orthographic projection of the plurality of pixel electrodes 041 on the substrate 01 in the array substrate. However, after increasing the area of the orthographic projection of the plurality of pixel electrodes 041 on the substrate 01, the orthographic projection of the pixel electrodes 041 may overlap with the orthographic projection of the data line 02 on the substrate 01. Thus, a parasitic capacitance is generated at the overlapping portion of the pixel electrode 041 and the data line 02, which causes a crosstalk problem in the array substrate, and may significantly affect the display effect of the reflective display panel on which the array substrate is disposed.
Referring to fig. 2, fig. 2 is a top view of an array substrate according to an embodiment of the present disclosure. The array substrate 000 may include:
a substrate 100, and a plurality of data lines 200 and a plurality of sub-pixels 300 on the substrate 100.
Each sub-pixel 300 may include: a reflective pixel electrode 301 and a TFT 302. The TFT 302 has a first pole 3021 and a second pole 3022. Note that the first pole 3021 in the TFT 302 in the embodiment of the present application refers to one of the source and the drain in the TFT 302, and the second pole 3022 in the TFT 302 refers to the other of the source and the drain in the TFT 302.
The first pole 3021 of the TFT 302 in each sub-pixel 300 may be connected to one data line 200, and the second pole 3022 of the TFT 302 in each sub-pixel 300 may be connected to the pixel electrode 301 in the sub-pixel 300.
In the present application, the plurality of data lines 200 in the array substrate 000 include a first data line 200a and a second data line 200 b. The first data line 200a is connected to the first pole 3021 of the TFT 302 in the sub-pixel 300, and the second data line is connected to the first pole 3021 of the TFT 302 in the sub-pixel 300 adjacent to the sub-pixel 300. That is, the first data line 200a and the second data line 200b are two adjacent data lines of the plurality of data lines 200.
Here, on the substrate 100, there is a first overlapping area S1 with the orthographic projection of the pixel electrode 301 in each sub-pixel 300, and the orthographic projection of the first pole 3021 of the TFT 302 in that sub-pixel 300 and the first data line 200a connected to that first pole 3021, and there is a second overlapping area S2 with the orthographic projection of the second data line 200 b.
In the embodiment of the present application, the pixel electrode 301 is insulated from the data line 200. Accordingly, in each sub-pixel 300, a portion of the pixel electrode 301 corresponding to the first overlap region S1, and the first electrode 3021 and a portion of the first data line 200a connected to each other corresponding to the first overlap region S1 can form the first parasitic capacitance Cdp1(not labeled in FIG. 2). Also, in each sub-pixel 300, a portion of the pixel electrode 301 corresponding to the second overlap region S2, and a portion of the second data line 200b corresponding to the second overlap region S2 form a second parasitic capacitance Cdp2(not labeled in FIG. 2).
To clearly see the structure of the parasitic capacitance in the sub-pixel 300, please refer to fig. 3, in which fig. 3 is a schematic diagram of the array substrate shown in fig. 2 at a-a'.
In some embodiments, the first parasitic capacitance Cdp in the sub-pixel 3001Is equal to the second parasitic capacitance Cdp2The capacitance value of (2).
In other embodiments, the first parasitic capacitance Cdp in the sub-pixel 3001Is not equal to the second parasitic capacitance Cdp2The capacitance value of (2).
In the embodiment of the application, the pixel electrode of one sub-pixel completely covers one part of the data line of the sub-pixel, and the pixel electrode of the adjacent sub-pixel covers the other part of the data line.
In the embodiment of the present application, when the orthographic projection of the pixel electrode 301 in the sub-pixel 300 overlaps with the orthographic projection of the first pole 3021 in the sub-pixel 300 and the orthographic projection of the first data line 200a and the second data line 200b on the substrate 100, the area of the orthographic projection of the plurality of pixel electrodes 301 in the array substrate 000 on the substrate 100 can be increased, so that the display effect of the reflective display panel on which the array substrate 000 is located is better. When the reflective display panel displays in the column inversion mode, the polarities of the voltages applied to the first data line 200a and the second data line 200b are opposite to each other. Thus, the first parasitic capacitance Cdp in the sub-pixel 3001And the second parasitic capacitance Cdp2At the first parasitic capacitance Cdp1And a second parasitic capacitance Cdp2Under the action of (1), the pulling action of the sub-pixel voltage loaded on the pixel electrode 301 by the first data line 200a and the second data line 200b can be used for positively and negatively offsetting a part or all of the voltage, and reducing or eliminating the influence of the data line on the display of the reflective display panel.
To sum up, the array substrate provided by the embodiment of the present application includes: the liquid crystal display device comprises a substrate, a plurality of data lines and a plurality of sub-pixels, wherein the data lines and the sub-pixels are positioned on the substrate. Each sub-pixel may include: a reflective pixel electrode and a TFT. The orthographic projection of the pixel electrode in each sub-pixel on the substrate is overlapped with the orthographic projection of the first pole, the first data line and the second data line, so that the orthographic projection area of the pixel electrodes in the array substrate on the substrate is larger, and the display effect of the reflective display panel where the array substrate is located is better.
When the reflective display panel performs display in the column inversion mode, the polarities of voltages applied to the first data line and the second data line are opposite to each other. Therefore, when the capacitance value of the first parasitic capacitor and the capacitance value of the second parasitic capacitor in each sub-pixel are nonzero or nonzero and equal, under the action of the first parasitic capacitor and the second parasitic capacitor, the pulling action of the first data line and the second data line on the sub-pixel voltage loaded on the pixel electrode can be partially or completely counteracted in a positive and negative mode, and the influence on the display of the reflective display panel is reduced. Therefore, on the premise that the display effect of the reflective display panel is not influenced by the parasitic capacitance, the orthographic projection area of the pixel electrodes on the substrate in the array substrate is increased, and the good display effect of the reflective display panel is ensured.
The first parasitic capacitance Cdp in the sub-pixel 300 of the present application1And the second parasitic capacitance Cdp2Are illustrative of the same or about the same.
In the embodiment of the present application, as shown in fig. 2 and 3, the first pole 3021 and the second pole 3022 of the TFT 302 in each sub-pixel 300 in the array substrate 000 may be disposed at the same layer as the plurality of data lines 200 in the array substrate 000. And the first and second poles 3021 and 3022 and the data line 200 are made of the same material. Thus, the first and second poles 3021 and 3022 and the data line 200 are formed through a single patterning process.
In this case, the distance between the pixel electrode 301 and the data line 200, and the distance between the pixel electrode 301 and the first pole 3021 are the same. It is assumed that, on the substrate 100, the area of the first overlap region S1 where the orthographic projection of the pixel electrode 301 overlaps the orthographic projection of the first pole 3021 and the first data line 200a connected to each other is a first area, and the orthographic projection of the pixel electrode 301 overlaps the orthographic projection of the second data line 200bThe area of the second overlapping area S2 is a second area. Then, the capacitance value of the capacitor is related to the relative area of the two opposing capacitor plates, and the distance between the two capacitor plates. Therefore, when the first and second electrodes 3021 and 3022 of the TFT 302 and the plurality of data lines 200 are disposed in the same layer, the first parasitic capacitance Cdp in the sub-pixel 300 can be ensured by ensuring that the first area is equal to the second area1Is equal to the second parasitic capacitance Cdp2The capacitance value of (2).
In the embodiment of the present application, as shown in fig. 4, fig. 4 is a top view of another array substrate provided in the embodiment of the present application. The plurality of sub-pixels 300 in the array substrate 000 may be arranged in a plurality of columns along the first direction x and also arranged in a plurality of rows along the second direction y. The first direction x is a row direction of the plurality of sub-pixels 000, the second direction y is a column direction of the plurality of sub-pixels 300, and the first direction x is perpendicular to the second direction y. Each data line 200 in the array substrate 000 extends in the second direction y on the substrate 100 as a whole.
The plurality of sub-pixels 300 includes a first sub-pixel 300a and a second sub-pixel 300b located in the same row and adjacent to each other. The first sub-pixel 300a and the second sub-pixel 300b may be any two adjacent sub-pixels located in any row. It is assumed that a row of sub-pixels including the first sub-pixel 300a is a first sub-pixel row, and a row of sub-pixels including the second sub-pixel 300b is a second sub-pixel row. Then, the data line 200 between the first subpixel column and the second subpixel column has: a first portion 200c extending into the first sub-pixel 300a and covered by the pixel electrode 301 in the first sub-pixel 300a, and a second portion 200d extending into the second sub-pixel 300b and covered by the pixel electrode 301 in the second sub-pixel 300 b. The orthographic projection of the first portion 200c on the substrate 100 is located within the first overlap region S1 in the first sub-pixel 300 a; the orthographic projection of the second portion 200d on the substrate 100 is located within the second overlap region S2 in the second sub-pixel 300 b.
Note that the first portion 200c of the data line 200 is connected to the first electrode 3021 of the TFT 302, and the second portion 200d of the data line 200 is not connected to the TFT 302. And the orthographic projection of the second portion 200d on the substrate 100 completely overlaps the second overlap region S2.
In this case, on the substrate 100, the orthographic projection of each data line 200 overlaps the orthographic projections of the pixel electrodes 301 in two columns of sub-pixels adjacent to the data line 200, respectively. Accordingly, on the substrate 100, the orthographic projections of the pixel electrodes 301 in each column of sub-pixels overlap the orthographic projections of the two data lines 200 adjacent to the column of sub-pixels.
In the present application, there are various structures of the first portion 200c and the second portion 200d in the data line 200, and the embodiments of the present application are schematically illustrated by taking the following two alternative implementations as examples.
In a first alternative implementation manner, as shown in fig. 5, fig. 5 is a top view of another array substrate provided in an embodiment of the present application. Each data line 200 in the array substrate 000 may include: a plurality of linear extensions 201 and a plurality of curved extensions 202 connected in series. Each curvilinear extension 202 has an opening. In the present application, the extending direction of each linear extending portion 201 is parallel to the second direction y, and the extending direction of each curved extending portion 202 is the direction of the arc line. The plurality of linear extensions 201 and the plurality of curved extensions 202 may be staggered one by one. It should be noted that the plurality of curved extensions 202 in the data line 200 have two kinds of curved extensions 202, and the structures of the two kinds of curved extensions 202 are the same, but the directions of the openings are different.
The plurality of linear extending portions 201 in the data line 200 may be located between the first sub-pixel column and the second sub-pixel column.
The first portion 200c of the data line 200 includes at least one curvilinear extension 202. The second portion 200c of the data line 200 includes at least one curvilinear extension 202. It should be noted that when the first portion 200c includes a plurality of curved extensions 202, the openings of the plurality of curved extensions 202 are oriented in the same direction. Likewise, when the second portion 200d includes a plurality of curvilinear extensions 202, the direction of the openings of the plurality of curvilinear extensions 202 is uniform. The direction of the opening of the curved extension 202 in the first portion 200c is opposite to the direction of the opening of the curved extension 202 in the second portion 200 c. For example, the opening of the curved extension 202 in the first portion 200c is oriented toward the second sub-pixel 300b, and the opening of the curved extension 202 in the second portion 200d is oriented toward the first sub-pixel 300 a.
In the embodiment of the present application, the first portion 200c of the data line 200 needs to be connected to the first electrode 3021 of the TFT 302. Therefore, in order to secure the first parasitic capacitance Cdp in any one of the sub-pixels 3001Is equal to the second parasitic capacitance Cdp2The number of the curved extensions 202 in the first portion 200c is less than the number of the curved extensions 202 in the second portion 200 d.
There are two cases for the arrangement of the straight extension 201 between the first sub-pixel 300a and the second sub-pixel 300 b:
in the first case, on the substrate 100, the orthogonal projection of the linear extension portion 201 is disposed at an interval from the orthogonal projection of the pixel electrode 301 in the first sub-pixel 300a, and is disposed at an interval from the orthogonal projection of the pixel electrode 301 in the second sub-pixel 300 b. In this case, in order to secure the first parasitic capacitance Cdp in any one of the sub-pixels 3001Is equal to the second parasitic capacitance Cdp2The distance between the linear extension 201 and the first sub-pixel 300a and the distance between the linear extension 201 and the second sub-pixel 300b need to be ensured to be equal.
In the second case, on the substrate 100, the orthogonal projection of the linearly-extending portion 201 overlaps the orthogonal projection of the pixel electrode 301 in the first sub-pixel 300a, and overlaps the orthogonal projection of the pixel electrode 301 in the second sub-pixel 300 b. In this case, in order to secure the first parasitic capacitance Cdp in any one of the sub-pixels 3001Is equal to the second parasitic capacitance Cdp2The area of overlap of the straight extension portion 201 and the orthographic projection of the pixel electrode 301 in the first sub-pixel 300a on the substrate 100 is equal to the area of overlap of the straight extension portion 201 and the orthographic projection of the pixel electrode 301 in the second sub-pixel 300b on the substrate 100.
In a second alternative implementation manner, as shown in fig. 6, fig. 6 is a top view of still another array substrate provided in an embodiment of the present application. Each data line 200 in the array substrate 000 includes: a plurality of first linear extensions 203 and a plurality of second linear extensions 204 connected to each other in this order. Moreover, the plurality of first linear extending portions 203 and the plurality of second linear extending portions 204 are arranged in a staggered manner one by one, and the extending directions of any two connected first linear extending portions 203 and second linear extending portions 204 are intersected.
Illustratively, the plurality of first linear extending portions 203 in the data line 200 extend in the same direction, and the plurality of second linear extending portions 204 in the data line 200 extend in the same direction. The extending direction of the first linear extending portion 203 is parallel to the second direction y, and the extending direction of the second linear extending portion 204 is parallel to the first direction x. In the same data line 200, any two adjacent second linear extension portions 204 and the first linear extension portion 203 located between the two second linear extension portions 204 can form a bent structure having an opening. In this way, in the same data line 200, a plurality of bent structures can be formed by the plurality of second linear extending portions 204 and the plurality of first linear extending portions 203, and the directions of the openings of any two adjacent bent structures are opposite.
In the embodiment of the present application, on the substrate 100, in any two adjacent first linear extension portions 203 in the same data line 200, a forward projection of one first linear extension portion 203 overlaps with a forward projection of the pixel electrode 301 in the first sub-pixel column, and a forward projection of the other first linear extension portion 203 overlaps with a forward projection of the pixel electrode 301 in the second sub-pixel column. And, on the substrate 100, the orthographic projection of each second straight extension portion 204 in the data line 200 overlaps with the orthographic projection of the pixel electrode 301 in the first sub-pixel column and the orthographic projection of the pixel electrode 301 in the second sub-pixel column, respectively.
Illustratively, of any two adjacent first linear extension portions 203 in the same data line 200, one first linear extension portion 203 may be connected to the first electrode 3021 of the TFT 302 in the first sub-pixel column, and on the substrate 100, the orthographic projections of the one first linear extension portion 203 overlap with the orthographic projections of two adjacent pixel electrodes 301 in the first sub-pixel column, respectively. On the substrate 100, the orthographic projection of another first straight extension portion 203 is positioned in the orthographic projection of one pixel electrode 301 in the second sub-pixel column and is arranged at a distance from the orthographic projection of the TFT 302. Thus, the data line 200 is connected to the sub-pixels 300 in the first sub-pixel column through the first straight extension 203 of the data line 200, and the data line 200 is not connected to the sub-pixels 300 in the second sub-pixel column.
In this case, the first portion 200c of the data line 200 includes a portion of the two first linear extensions 203 and a portion of the two second linear extensions 204; the second portion 200d of the data line 200 includes all of one first linear extension 203 and a portion of two second linear extensions 204.
Alternatively, as shown in fig. 7, fig. 7 is a top view of an array substrate according to another embodiment of the present disclosure. On the substrate 100, the orthographic projection of the TFT 302 in each sub-pixel 300 is located within the orthographic projection of the pixel electrode 301 in that sub-pixel 300. In this way, the area of the orthographic projection of the plurality of pixel electrodes 301 in the array substrate 000 on the substrate 100 can be further increased. Fig. 7 is a schematic illustration of the structure of the data lines in the array substrate as the data lines shown in fig. 6.
In an embodiment of the present application, the array substrate 000 may further include: a plurality of gate lines 400 on the substrate 100. The TFT 302 of each sub-pixel 300 in the array substrate 000 further includes: a gate electrode 3023, and the gate electrode 3023 of the TFT 302 may be connected to one gate line 400. For example, the gate line 400 may be disposed on the same layer as the gate electrode 3023, and the material of the gate line 400 is the same as that of the gate electrode 3023. Thus, the gate line 400 and the gate electrode 3023 may be formed through a single patterning process.
Alternatively, as shown in fig. 7 and 8, fig. 8 is a schematic view of a film structure of the array substrate shown in fig. 7 at a-a'. The array substrate 000 may further include: a first auxiliary electrode 500 connected to the second electrode 3022 of the TFT 302, a second auxiliary electrode 600 positioned at a side of the first auxiliary electrode 500 remote from the pixel electrode 301, and a first insulating layer 700 positioned between the first auxiliary electrode 500 and the second auxiliary electrode 600.
In the present application, an orthogonal projection of the first auxiliary electrode 500 overlaps an orthogonal projection of the second auxiliary electrode 600 on the substrate 100. Since the first auxiliary electrode 500 can be electrically connected to the pixel electrode 301 through the second electrode 3022, the potential of the first auxiliary electrode 500 is the same as that of the pixel electrode 301 when power is applied. Thus, the first auxiliary electrode 500 and the second auxiliary electrode 600 can form a storage capacitor Cst, and the storage capacitor Cst can maintain the stability of the voltage applied to the pixel electrode 500.
It should be noted that the number of the first auxiliary electrodes 500 and the second auxiliary electrodes 600 in the array substrate 000 may be multiple, and the multiple first auxiliary electrodes 500, the multiple second auxiliary electrodes 600 and the multiple pixel electrodes 301 are in one-to-one correspondence. On the substrate 100, the orthographic projection of each pixel electrode 301 overlaps with the orthographic projection of the corresponding first auxiliary electrode 500 and the orthographic projection of the corresponding second auxiliary electrode 600, and the orthographic projections of the first auxiliary electrode 500 and the second auxiliary electrode 600 are located in the orthographic projection of the corresponding pixel electrode 301.
In this application, the first auxiliary electrode 500 may be disposed at the same layer as the first and second poles 3021 and 3022 of the TFT 302 and may be made of the same material. That is, the first auxiliary electrode 500 is formed through the same patterning process as the first and second poles 3021 and 3022. The second auxiliary electrode 500 may be disposed at the same layer as the gate electrode 3023 of the TFT 302 and may be the same material. That is, the second auxiliary electrode 500 and the gate electrode 3023 are formed through the same patterning process. Therefore, the manufacturing process of the array substrate is effectively simplified.
Optionally, the array substrate 000 may further include: the common electrode line 800 is electrically connected to the second auxiliary electrode 600 in each row, and the common electrode line 800 may be disposed on the same layer as the second auxiliary electrode 500 and may be made of the same material. That is, the common electrode line 800 may be formed through the same patterning process as the second auxiliary electrode 500. The common electrode line 500 may be electrically connected to a common electrode in the liquid crystal display panel on which the array substrate 000 is disposed, and thus, in case of power-on, the second auxiliary electrode 500 has the same potential as the common electrode.
In the embodiment of the present application, the first pole 3021 of the TFT 302 in each sub-pixel 300 comprises a U-shaped structure, the first pole 3022 of the TFT 302 comprises a stripe structure, and one end of the second pole 3022 is located within the U-shaped structure in the first pole 3021, and the other end is electrically connected to the pixel electrode 301. Illustratively, the TFT 302 in each sub-pixel 300 further includes an active layer 3024, the active layer 3024 is connected to the first and second poles 3021 and 3022, respectively, and the active layer 3024 is disposed in insulation with the gate electrode 3023, for example, the first insulation layer 700 is disposed between the active layer 3024 and the gate electrode 3023. When the first electrode 3021 of the TFT 302 includes a U-shaped structure and the second electrode 3022 includes a stripe structure having one end extending into the U-shaped structure, the channel region of the active layer 3024 is a U-shaped channel region. Note that the channel region of the active layer 3024 refers to: a region of the active layer 3024 between a region where the active layer 3024 contacts the first pole 3021 and a region where the active layer 3024 contacts the second pole 3022. When the channel region of the active layer 3024 is a U-shaped channel region, the TFT 302 can bear a higher breakdown voltage and the lifetime of the array substrate 000 can be improved because the U-shaped channel region has a larger length-width ratio.
As shown in fig. 8, the array substrate further includes: and a second insulating layer 900 between the pixel electrode 301 and the second electrode 3022. The second insulating layer 900 has a via hole 900a, and the pixel electrode 301 may be electrically connected to the other end of the second electrode 3022 through the via hole 900 a.
In the embodiment of the present application, as shown in fig. 7, on the substrate 100, the orthographic projection of one gate line 400 overlaps with the orthographic projection of the pixel electrode 301 in one row of the sub-pixels 300. In this way, the area of the orthographic projection of the plurality of pixel electrodes 301 in the array substrate 000 on the substrate 100 is further increased.
In this case, the size of the area of the orthographic projection of the plurality of pixel electrodes 301 on the substrate 100 in the array substrate 000 is only related to the process accuracy in manufacturing the array substrate 000. The distance between any two adjacent pixel electrodes 301 can be theoretically infinitely reduced, so that the ratio of the area of the orthographic projection of the pixel electrodes 301 on the substrate 100 to the surface of the substrate 100 close to the electrodes 301 can be theoretically close to 100%, and further the area of the orthographic projection of the pixel electrodes 301 on the substrate 100 is larger, and the display effect of the reflective display panel is greatly improved. Illustratively, each pixel electrode 301 in the plurality of sub-pixels 300 is distributed in an array, and the distance between any two adjacent pixel electrodes 301 is equal in the first direction x or the second direction y.
It should be noted that fig. 7 is schematically illustrated by taking an example in which the orthographic projection of the gate line 400 connected to the gate electrode 3023 of the TFT 302 in the nth row of sub-pixels overlaps the orthographic projection of the pixel electrode 301 in the nth row of sub-pixels on the substrate 100. However, in this case, a parasitic capacitance is generated between the pixel electrode 301 and the gate electrode 400, and due to the parasitic capacitance, the reflective display panel on which the array substrate 000 is located flickers, which seriously affects the display effect of the reflective display panel.
For example, as shown in fig. 9, fig. 9 is an equivalent circuit diagram of a sub-pixel in a reflective display panel. In each sub-pixel 300, a first pole of the TFT 302 is connected to one data line 200, a second pole of the TFT 302 is connected to the pixel electrode, and a gate of the TFT 302 is connected to one gate line 400. The pixel electrode can be equivalent to a liquid crystal capacitor Clc with a common electrode Vcom in the reflective display panel, and the pixel electrode can form a storage capacitor Cst with the common electrode line. The TFT 302 may output a data signal from the data line 200 to which the TFT 302 is connected to a pixel electrode to which it is connected in response to a gate driving signal supplied from the gate line 400 to which it is connected, to charge the pixel electrode, thereby causing a potential difference between the pixel electrode and the common electrode Vcom. The liquid crystal molecules between the pixel electrode and the common electrode Vcom can be deflected by the potential difference, thereby controlling the sub-pixel to emit light.
As shown in fig. 9, in each sub-pixel 300, the pixel electrode can be connected to each otherThe first data line and the first pole generate a first parasitic capacitance Cdp1And the pixel electrode can also generate a second parasitic capacitance Cdp with the second data line2. When the first parasitic capacitance Cdp1Is equal to the second parasitic capacitance Cdp2The first parasitic capacitance Cdp1And a second parasitic capacitance Cdp2The display of the reflective display panel is not affected.
As shown in fig. 9, in each sub-pixel 300, when the orthographic projection of the pixel electrode in the sub-pixel overlaps with the orthographic projection of the gate electrode connected to the sub-pixel on the substrate, the pixel electrode and the gate line generate a parasitic capacitance Cgs. When the potential on the gate line 200 changes, the potential of the pixel electrode connected to the gate line 200 is pulled out from the set potential by the coupling action of the parasitic capacitance Cgs. Since the electric potential of the pixel electrode changes and the electric potential of the common electrode Vcom is generally a fixed value, the electric potential difference between the pixel electrode and the common electrode changes, which eventually causes the liquid crystal molecules to deflect abnormally, and the reflective display panel will flicker, resulting in poor display effect.
Under the action of the parasitic capacitance Cgs, in the charging process of the pixel electrode, the potential charged to the pixel electrode jumps to a certain degree in the initial charging stage and the final charging stage, and the actual potential charged to the pixel electrode deviates from the set potential. And the potential difference Δ Vp between the actual potential and the set potential can satisfy:
wherein VGH is the gate high voltage, VGL is the gate low voltage. From this equation, it can be seen that the larger the parasitic capacitance Cgs, the larger Δ Vp is caused. The Δ Vp is a key factor affecting the image quality, and the risk of image flicker and residual image due to the brightness difference between the positive and negative frames increases when the Δ Vp is too large.
To this end, as shown in fig. 10, fig. 10 is a top view of another array substrate provided in another embodiment of the present application, on the substrate 100 in the array substrate 000, an orthogonal projection of the gate line 400 connected to the gate electrode 3023 of the TFT 302 in the nth row of sub-pixels may be spaced from an orthogonal projection of the pixel electrode 301 in the nth row of sub-pixels, and may overlap an orthogonal projection of the pixel electrode 301 in the (n + 1) th row of sub-pixels. Thus, the gate line 400 connected to the gate electrode 3023 of the TFT 302 in the nth row of sub-pixels forms a parasitic capacitance with the pixel electrode 301 in the (n + 1) th row of sub-pixels, but does not form a parasitic capacitance with the pixel electrode 302 in the nth row of sub-pixels. In addition, because the n-th row of sub-pixels and the n + 1-th row of sub-pixels need to be charged sequentially during display, the gate line 400 connected to the gate electrode 3023 of the TFT 302 in the n-th row of sub-pixels and the pixel electrode in the n + 1-th row of pixels form a parasitic capacitance, which does not affect the charged n + 1-th row of pixels, thereby effectively reducing the probability of flicker when the reflective display panel on which the array substrate 000 is located displays a picture, and further improving the display effect of the reflective display panel.
Optionally, any two adjacent data lines 200 in the array substrate 000 are used for loading voltages with opposite polarities. Therefore, the reflective display panel where the array substrate 000 is located adopts a column-flipping mode to display, and the phenomenon that liquid crystal molecules in the reflective display panel are aged is effectively avoided. In other alternative implementations, the reflective display panel can also display in a dot-and-dash mode. The embodiment of the present application does not limit this.
Optionally, the materials of the pixel electrode 302 in the above embodiments include: a metal material having light reflecting properties. For example, the material of the pixel electrode 302 may include: metallic materials such as metallic aluminum, metallic silver, or alloys.
In some embodiments, the pixel electrode covers the thin film transistor connected thereto and the data line connected thereto while covering a portion of the data line of the adjacent sub-pixel on the substrate.
In some embodiments, the pixel electrodes are rectangular, the data lines extend in one direction as a whole and are covered by the pixel electrodes of the sub-pixels in the same column, a portion of the data line passing through one pixel electrode has a portion extending to an adjacent sub-pixel, and the portion extending to the adjacent sub-pixel is covered by the pixel electrode of the adjacent sub-pixel.
In some embodiments, on the substrate, the data line extends in a column direction in a sub-pixel connected to the data line, extends in a column direction in an adjacent sub-pixel, and the extending portions in the two sub-pixels are connected by a connection line; alternatively, the first and second electrodes may be,
the data line is a straight line extending along the column direction in the sub-pixel connected with the data line, and extends along the column direction for the whole in the adjacent sub-pixel, and is a curve or a broken line locally; the extended parts in the two sub-pixels are connected by a connecting line; alternatively, the first and second electrodes may be,
the data line is a curve or a broken line extending along the column direction in the sub-pixel connected with the data line, and the data line is a whole extending along the column direction in the adjacent sub-pixel and is a local straight line, a broken line or a curve; the extended portions within the two sub-pixels are connected by a connection line.
To sum up, the array substrate provided by the embodiment of the present application includes: the liquid crystal display device comprises a substrate, a plurality of data lines and a plurality of sub-pixels, wherein the data lines and the sub-pixels are positioned on the substrate. Each sub-pixel may include: a reflective pixel electrode and a TFT. The orthographic projection of the pixel electrode in each sub-pixel on the substrate is overlapped with the orthographic projection of the first pole, the first data line and the second data line, so that the orthographic projection area of the pixel electrodes in the array substrate on the substrate is larger, and the display effect of the reflective display panel where the array substrate is located is better. When the reflective display panel performs display in the column inversion mode, the polarities of voltages applied to the first data line and the second data line are opposite to each other. Therefore, when the capacitance value of the first parasitic capacitance and the capacitance value of the second parasitic capacitance in each sub-pixel are equal, under the action of the first parasitic capacitance and the second parasitic capacitance, the pulling action of the first data line and the second data line on the sub-pixel voltage loaded on the pixel electrode can be counteracted positively and negatively, and the display of the reflective display panel is not influenced. Therefore, on the premise that the display effect of the reflective display panel is not influenced by the parasitic capacitance, the orthographic projection area of the pixel electrodes on the substrate in the array substrate is increased, and the good display effect of the reflective display panel is ensured.
An embodiment of the present application further provides a reflective display panel, as shown in fig. 11, fig. 11 is a schematic diagram of a film structure of the reflective display panel provided in the embodiment of the present application. The reflective display panel may include:
the liquid crystal display panel comprises an array substrate 000, a color film substrate 001 and a liquid crystal layer 002, wherein the array substrate 000 and the color film substrate 001 are arranged oppositely, and the liquid crystal layer 002 is located between the array substrate 000 and the color film substrate 001. The array substrate 000 may be the array substrate in the above embodiments, for example, the array substrate 000 may be the array substrate shown in fig. 2 or fig. 4.
In the present application, when the common electrode is located on the color filter substrate 001, the reflective display panel is a Twisted Nematic (TN) display panel.
The embodiment of the application also provides a display device, and the display device can comprise the reflective display panel. Optionally, the display device may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer or a navigator.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
In this application, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.
The above description is intended to be exemplary only, and not to limit the present application, and any modifications, equivalents, improvements, etc. made within the spirit and scope of the present application are intended to be included therein.
Claims (15)
1. An array substrate, comprising: a substrate; a plurality of data lines and a plurality of sub-pixels on the substrate, each of the sub-pixels including: the first pole of the thin film transistor is connected with one data line, and the second pole of the thin film transistor is connected with the pixel electrode; it is characterized in that the preparation method is characterized in that,
the data line comprises a first data line and a second data line, the first data line is connected with the first pole of the thin film transistor in the sub-pixel, and the second data line is connected with the first pole of the thin film transistor in the sub-pixel adjacent to the sub-pixel;
wherein, on the substrate, a first overlapping area exists between the orthographic projection of the pixel electrode in the sub-pixel and the orthographic projection of the first electrode of the thin film transistor in the sub-pixel and the first data line connected with the first electrode, and a second overlapping area exists between the orthographic projection of the pixel electrode in the sub-pixel and the orthographic projection of the second data line.
2. The array substrate of claim 1, wherein a portion of the pixel electrode corresponding to the first overlap region and a portion of the first electrode and the first data line connected to each other corresponding to the first overlap region form a first parasitic capacitance, and a portion of the pixel electrode corresponding to the second overlap region and a portion of the second data line corresponding to the second overlap region form a second parasitic capacitance, the first parasitic capacitance having a capacitance value equal to a capacitance value of the second parasitic capacitance.
3. The array substrate of claim 1 or 2, wherein the first and second electrodes of the thin film transistor are disposed on the same layer as the data lines and are made of the same material;
on the substrate, the area of a first overlapping region where the orthographic projection of the pixel electrode overlaps with the orthographic projection of the first electrode and the first data line which are connected with each other is a first area;
on the substrate, the area of a second overlapping region where the orthographic projection of the pixel electrode and the orthographic projection of the second data line overlap is a second area;
the first area is equal to the second area.
4. The array substrate of claim 1, wherein the plurality of sub-pixels are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction, the data lines extending generally along the second direction on the substrate;
the plurality of sub-pixels include a first sub-pixel and a second sub-pixel which are located in the same row and adjacent to each other, and the data line has: a first portion extending into the first sub-pixel and covered by a pixel electrode in the first sub-pixel, and a second portion extending into the second sub-pixel and covered by a pixel electrode in the second sub-pixel, an orthographic projection of the first portion on the substrate being within the first overlap region in the first sub-pixel, an orthographic projection of the second portion on the substrate being within the second overlap region in the second sub-pixel.
5. The array substrate of claim 4, wherein the data line comprises: the device comprises a plurality of linear extending parts and a plurality of curved extending parts which are connected in sequence, wherein each curved extending part is provided with an opening;
the plurality of linear extending parts are all positioned between a first sub-pixel column and a second sub-pixel column, the first sub-pixel column is a column of sub-pixels comprising the first sub-pixels, and the second sub-pixel column is a column of sub-pixels comprising the second sub-pixels;
the first portion includes at least one of the curvilinear extensions, the second portion includes at least one of the curvilinear extensions, and the direction of the opening of the curvilinear extension in the first portion is opposite the direction of the opening of the curvilinear extension in the second portion.
6. The array substrate of claim 4, wherein the data line comprises: the first linear extension parts and the second linear extension parts are connected in sequence, the first linear extension parts and the second linear extension parts are arranged in a staggered mode one by one, and the extending directions of any two connected first linear extension parts and the second linear extension parts are intersected;
the plurality of sub-pixels are arranged in a plurality of columns, and in two adjacent first linear extending parts in the same data line on the substrate, the orthographic projection of one first linear extending part is overlapped with the orthographic projection of the pixel electrode in a first sub-pixel column, and the orthographic projection of the other first linear extending part is overlapped with the orthographic projection of the pixel electrode in a second sub-pixel column;
on the substrate, the orthographic projection of the second straight extension part in the data line is respectively overlapped with the orthographic projection of the pixel electrode in the first sub-pixel column and the orthographic projection of the pixel electrode in the second sub-pixel column;
the first sub-pixel column is a column of sub-pixels including the first sub-pixel, and the second sub-pixel column is a column of sub-pixels including the second sub-pixel;
the extending directions of the first linear extending parts are all parallel to the second direction, and the extending directions of the second linear extending parts are all parallel to the first direction.
7. The array substrate of claim 6, wherein two adjacent first linear extensions in the same data line are connected to a first electrode of a thin film transistor in the first sub-pixel column, and an orthogonal projection of one first linear extension on the substrate overlaps with an orthogonal projection of two adjacent pixel electrodes in the first sub-pixel column, respectively, and an orthogonal projection of the other first linear extension on the substrate is located within an orthogonal projection of a pixel electrode in the second sub-pixel column and spaced from the orthogonal projection of the thin film transistor.
8. The array substrate of claim 1, wherein the pixel electrode covers the thin film transistor connected thereto and covers the data line connected thereto while covering a portion of the data line of the adjacent sub-pixel on the substrate.
9. The array substrate of claim 8, wherein the pixel electrodes are rectangular, the data lines extend in one direction as a whole and are covered by the pixel electrodes of the sub-pixels in the same column, a portion of the data line passing through one pixel electrode has a portion extending to an adjacent sub-pixel, and the portion extending to the adjacent sub-pixel is covered by the pixel electrode of the adjacent sub-pixel.
10. The array substrate of claim 9, wherein the data line is a straight line extending along the column direction in the sub-pixel connected to the data line and extends along the column direction in the adjacent sub-pixel as a whole, and is a local straight line, a curve or a broken line on the substrate; the extended parts in the two sub-pixels are connected by a connecting line; alternatively, the first and second electrodes may be,
the data line is a curve or a broken line extending along the column direction in the sub-pixel connected with the data line, and the data line is a whole extending along the column direction in the adjacent sub-pixel and is a local straight line, a broken line or a curve; the extended portions within the two sub-pixels are connected by a connection line.
11. The array substrate of claim 9, wherein each of the pixel electrodes in the plurality of sub-pixels is distributed in an array, and a distance between any two adjacent pixel electrodes in the first direction or the second direction is equal.
12. The array substrate of any one of claims 4 to 11, wherein the first pole comprises a U-shaped structure, the second pole comprises a stripe structure, one end of the second pole is located in the U-shaped structure, and the other end of the second pole is connected to the pixel electrode.
13. The array substrate of claim 12, further comprising: a first auxiliary electrode connected to the second electrode, a second auxiliary electrode located on a side of the first auxiliary electrode away from the pixel electrode, and a first insulating layer located between the first auxiliary electrode and the second auxiliary electrode;
wherein, on the substrate, a forward projection of the first auxiliary electrode overlaps with a forward projection of the second auxiliary electrode.
14. The array substrate of claim 13, wherein the first auxiliary electrode is disposed in the same layer as the first and second electrodes and is made of the same material; the second auxiliary electrode and the grid electrode of the thin film transistor are arranged on the same layer and are made of the same material.
15. A reflective display panel, comprising: the liquid crystal display panel comprises an array substrate, a color film substrate and a liquid crystal layer, wherein the array substrate and the color film substrate are oppositely arranged, and the liquid crystal layer is positioned between the array substrate and the color film substrate, and the array substrate is the array substrate in any one of claims 1 to 14.
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