CN114740662B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN114740662B CN114740662B CN202210486172.9A CN202210486172A CN114740662B CN 114740662 B CN114740662 B CN 114740662B CN 202210486172 A CN202210486172 A CN 202210486172A CN 114740662 B CN114740662 B CN 114740662B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134327—Segmented, e.g. alpha numeric display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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Abstract
The application belongs to the technical field of array substrates, and particularly relates to an array substrate, a display panel and a display device, wherein the array substrate comprises a plurality of data lines, a plurality of scanning lines and a pixel array, the pixel array comprises sub-pixels which are arranged in an array manner, a source electrode of a charge sharing thin film transistor of each sub-pixel is connected with a main pixel electrode of a sub-pixel of the other row in the same column through a conductive structure, the sub-pixels of the row and the sub-pixel of the other row in the same column are driven row by row, the charge sharing thin film transistor discharges through the main pixel electrode of the other row, a common electrode of an original penetrating structure is changed into a plurality of segmented conductive structures, the aperture ratio of the array substrate is improved, and simultaneously, the main pixel electrode of the other row is precharged, the charging rate of the main pixel is improved, and the display effect of the display panel is improved.
Description
Technical Field
The application belongs to the technical field of array substrates, and particularly relates to an array substrate, a display panel and a display device.
Background
With the continuous development of display technology, the quality requirements of people on display screens are continuously improved, wherein the requirements on large viewing angles are particularly obvious, so that various modes are adopted by various companies to improve the large viewing angles, and multi-domain pixel structures are generated.
In a multi-domain pixel structure, the pixel electrode is divided into a plurality of display domains in different directions, and the space of the array substrate is limited.
Meanwhile, in order to improve visual color difference or visual color cast, the sub-pixels are generally divided into main pixels and sub-pixels, the main pixels and the sub-pixels are sequentially arranged along the row direction, each main pixel comprises a main pixel electrode and a main thin film transistor, each sub-pixel comprises a sub-pixel electrode, a sub-thin film transistor and a charge sharing thin film transistor, the main thin film transistor charges the main pixel electrode, the sub-thin film transistor charges the sub-pixel electrode, and the charge sharing thin film transistor discharges the sub-pixel electrode, so that the main pixels and the sub-pixels generate different potentials to increase the viewing angle, wherein the charge sharing thin film transistor is connected with a common electrode on an array substrate, and the common electrode is discharged through the common electrode to be connected with each charge sharing thin film transistor of each row in a penetrating way, and the aperture ratio of the array substrate is reduced.
Disclosure of Invention
The application aims to provide an array substrate, which is characterized in that a charge sharing thin film transistor is connected to a main pixel electrode of a sub-pixel of the same row and another row, so that the aperture ratio of the array substrate is improved, and the charging rate is improved.
The first aspect of the embodiment of the application provides an array substrate, which comprises a plurality of data lines, a plurality of scanning lines and a pixel array, wherein the data lines are used for inputting data signals with corresponding polarities, the scanning lines are used for inputting row-by-row starting signals, the pixel array comprises sub-pixels which are arranged in an array manner, and each sub-pixel comprises a main pixel and a sub-pixel which are respectively connected with the same data line and the same scanning line;
the main pixel comprises a main pixel electrode and a main thin film transistor, and the main pixel electrode is correspondingly connected with the data line and the scanning line through the main thin film transistor;
the sub-pixel comprises a sub-pixel electrode, a sub-thin film transistor and a charge sharing thin film transistor;
the sub-pixel electrode is correspondingly connected with the data line and the scanning line through the sub-thin film transistor;
the grid electrode of the charge sharing thin film transistor is connected with the corresponding scanning line, the drain electrode of the charge sharing thin film transistor is connected with the secondary pixel electrode, and the source electrode of the charge sharing thin film transistor is connected with the main pixel electrode of the sub-pixel of the other row of the same column through a conductive structure, wherein the sub-pixel of the row and the sub-pixel of the other row of the same column are driven row by row in sequence.
Optionally, the conductive structure is arranged in different layers with the main pixel electrode, the main pixel electrode and the sub pixel electrode are arranged in the same layer, and the conductive structure extends along the right lower part of the vertical trunk of the sub pixel electrode in the current row in the same column and is connected with the main pixel electrode in the next row in the same column through a via hole.
Optionally, the main pixel electrode and the sub pixel electrode respectively include four display domains;
the main pixel electrode comprises a first display domain and a second display domain which are adjacent to two same rows of sub-pixel electrodes on the same row, and a third display domain and a fourth display domain which are far away from two same rows of sub-pixel electrodes on the same row;
the conductive structure extends to the position right below the edge center point of the first display domain and the second display domain in the main pixel electrode of the next row of the same column along the lower part of the vertical trunk of the sub pixel electrode of the current row of the same column, and is connected with the main pixel electrode through a via hole.
Optionally, the main pixel electrode and the sub pixel electrode respectively include four display domains;
the conductive structure extends to the position right below the center positions of four display domains of the main pixel electrode in the next row of the same column along the lower part of the vertical trunk of the sub pixel electrode in the current row of the same column, and is connected with the main pixel electrode through a via hole.
Optionally, the conductive structure and the main pixel electrode are arranged in different layers, the main pixel electrode and the sub-pixel electrode are arranged in the same layer, and the array substrate further includes:
a first common electrode, wherein each main pixel electrode and the edge part of the first common electrode are overlapped to form a main storage capacitor, and each sub pixel electrode and the edge part of the first common electrode are overlapped to form a sub storage capacitor;
the conductive structure and the first common electrode are arranged in different layers;
the conductive structure extends along the right upper side or the right lower side of the first common electrode and is connected to the edge position of the corresponding display domain of the main pixel electrode of the next row of the same column through a via hole.
Optionally, the conductive structure further extends along under a horizontal trunk of the main pixel electrode of the next row in the same column and is connected to a central position of a corresponding display domain of the main pixel electrode through a via hole.
Optionally, the conductive structure is arranged in a different layer from the main pixel electrode, the main pixel electrode is arranged in the same layer as the sub pixel electrode, and the conductive structure is arranged in a different layer from the data line;
the conductive structure extends along the right upper side or the right lower side of the data line commonly connected with the sub-pixels in the same column and is connected to the edge position of the corresponding display domain of the main pixel electrode in the next row in the same column.
Optionally, the conductive structure further extends along under a horizontal trunk of the main pixel electrode of the next row in the same column and is connected to a central position of a corresponding display domain of the main pixel electrode through a via hole.
A second aspect of the embodiment of the present application provides a display panel, including a color film substrate, a liquid crystal layer, and an array substrate as described above, where the liquid crystal layer is disposed between the color film substrate and the array substrate.
A third aspect of the embodiment of the present application provides a display device, including a backlight module, a display panel driving circuit and a display panel as described above, where the display panel driving circuit is correspondingly connected to the display panel, and the backlight module is disposed opposite to the display panel.
Compared with the prior art, the embodiment of the application has the beneficial effects that: in the array substrate, the source electrode of the charge sharing thin film transistor of each sub-pixel is connected with the main pixel electrode of the sub-pixel of the other row in the same column through a conductive structure, the sub-pixel of the row and the sub-pixel of the other row in the same column are driven row by row, the charge sharing thin film transistor discharges through the main pixel electrode of the other row, the common electrode of the original penetrating structure is changed into a plurality of segmented conductive structures, the aperture ratio of the array substrate is improved, and meanwhile, the main pixel electrode of the other row is precharged, the charging rate of the main pixel is improved, and the display effect of the display panel is improved.
Drawings
FIG. 1 is a schematic circuit diagram of an array substrate according to an embodiment of the present application;
fig. 2 is a schematic diagram of a charging waveform of an array substrate according to an embodiment of the application;
fig. 3 is a schematic structural diagram of an array substrate according to a second embodiment and a third embodiment of the present application;
fig. 4 is a schematic cross-sectional structure of an array substrate according to a second embodiment and a third embodiment of the present application;
fig. 5 is a schematic structural diagram of an array substrate according to a fourth embodiment of the present application;
fig. 6 is a schematic cross-sectional structure of an array substrate according to a fourth embodiment of the present application;
fig. 7 is a schematic diagram of a first structure of an array substrate according to a fifth embodiment of the present application;
fig. 8 is a schematic cross-sectional structure of an array substrate according to a fifth embodiment of the present application;
fig. 9 is a schematic diagram of a second structure of an array substrate according to a fifth embodiment of the present application;
fig. 10 is a schematic diagram of a first structure of an array substrate according to a sixth embodiment of the present application;
FIG. 11 is a schematic cross-sectional view of an array substrate according to a sixth embodiment of the present application;
fig. 12 is a schematic diagram of a second structure of an array substrate according to a sixth embodiment of the present application;
fig. 13 is a schematic structural diagram of a display panel according to a seventh embodiment of the present application;
fig. 14 is a schematic structural diagram of a display device according to an eighth embodiment of the application.
Wherein, each reference sign in the figure is:
100-display panel, 200-display panel driving circuit, 300-backlight module, 1-array substrate, 2-color film substrate, 3-liquid crystal layer, 10-sub-pixel, 20-data line, 30-scanning line, 11-main pixel, 12-sub-pixel, 13-conductive structure, 14-wiring area, 15-via hole, 111-main pixel electrode, 112-first common electrode, 121-sub-pixel electrode, T1-main thin film transistor, T2-sub-thin film transistor, T3-charge sharing thin film transistor, C1-main liquid crystal capacitor, C2-sub-liquid crystal capacitor, common electrode of CF_COM-color film substrate.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Example 1
A first aspect of an embodiment of the present application proposes an array substrate 1.
The array substrate 1 comprises a plurality of data lines 20, a plurality of scanning lines 30 and a pixel array, wherein the plurality of data lines 20 are distributed at intervals along the horizontal direction, the plurality of scanning lines 30 are distributed in sequence along the vertical direction, the data lines 20 and the scanning lines 30 are arranged in a crossing mode, the data lines 20 are used for inputting data signals with corresponding polarities, the scanning lines 30 are used for inputting row-by-row starting signals, the pixel array comprises sub-pixels 10 distributed in an array mode, and the sub-pixels 10 are correspondingly connected with the data lines 20 and the scanning lines 30 and are charged or discharged in a controlled mode.
As shown in fig. 1, each sub-pixel 10 includes a main pixel 11 and a sub-pixel 12 respectively connected to the same data line 20 and the same scan line 30;
the main pixel 11 includes a main pixel electrode 111 and a main thin film transistor T1, and the main pixel electrode 111 is correspondingly connected to the data line 20 and the scan line 30 through the main thin film transistor T1;
the sub-pixel 12 includes a sub-pixel electrode 121, a sub-thin film transistor T2, and a charge-sharing thin film transistor T3;
the sub-pixel electrode 121 is correspondingly connected with the data line 20 and the scanning line 30 through the sub-thin film transistor T2;
the gate of the charge-sharing thin film transistor T3 is connected to the corresponding scan line 30, the drain of the charge-sharing thin film transistor T3 is connected to the sub-pixel electrode 121, and the source of the charge-sharing thin film transistor T3 is connected to the main pixel electrode 111 of the sub-pixel 10 of another row in the same column through the conductive structure 13, wherein the sub-pixels 10 of the present row and the sub-pixels 10 of another row in the same column are sequentially driven row by row.
In this embodiment, the gate electrode of the main thin film transistor T1 is connected to the scan line 30 corresponding to the sub-pixel 10, the source electrode of the main thin film transistor T1 is connected to the data line 20 corresponding to the sub-pixel 10, the drain electrode of the main thin film transistor T1 is connected to the main pixel electrode 111, and the main pixel electrode 111 and the common electrode cf_com of the color film substrate 2 form a main liquid crystal capacitor C1.
The gate of the sub-thin film transistor T2 is connected to the scan line 30 corresponding to the sub-pixel 10, the source of the sub-thin film transistor T2 is connected to the data line 20 corresponding to the sub-pixel 10, the drain of the sub-thin film transistor T2 is connected to the sub-pixel electrode 121, and the sub-pixel electrode 121 and the common electrode cf_com of the color film substrate 2 form a sub-liquid crystal capacitor C2.
The gate of the charge-sharing thin film transistor T3 is connected to the scan line 30 corresponding to the sub-pixel 10, the drain of the charge-sharing thin film transistor T3 is connected to the sub-pixel electrode 121 of the sub-pixel 10, and the source of the charge-sharing thin film transistor T3 is connected to the main pixel electrode 111 of the sub-pixel 10 of another row and column through the conductive structure 13.
The sub-pixels 10 in the row and the sub-pixels 10 in another row in the same column are sequentially driven row by row, that is, the sub-pixels 10 in the row input a row start signal before the sub-pixels 10 in the row start signal after the sub-pixels 10 in the other row input a row start signal, so that the corresponding thin film transistors are sequentially turned on row by row and the corresponding data signals are input, the main thin film transistor T1 charges the main pixel electrode 111, the sub-thin film transistor T2 charges the sub-pixel electrode 121, the charge sharing thin film transistor T3 discharges the sub-pixel electrode 121, and different potentials are generated by the main pixel 11 and the sub-pixel 12 to increase the viewing angle.
The charge sharing thin film transistor T3 performs a discharging operation through the main pixel electrode 111 of the sub-pixel 10 to be driven in another row, and referring to fig. 2, the discharging structure becomes a plurality of segmented conductive structures 13, compared with the common electrode of the original penetrating structure, so that the aperture ratio of the array substrate 1 is improved.
Meanwhile, the charge sharing thin film transistor T3 discharges to the main pixel electrode 111 of the sub-pixel 10 to be driven in another row, and precharges the main pixel electrode 111 in another row, so that the charging capability of the main pixel electrode 111 in another row is enhanced, and the charging rate is improved, thereby improving the display effect of the display panel 100.
As shown in fig. 2, when the n-th row scanning line 30 inputs a row on signal, the main pixel electrode 111 and the sub-pixel electrode 121 of the sub-pixel 10 are charged, and the polarity of the input data signal and the polarity of the data signal input to the n+1th row sub-pixel 10 are opposite, so the charge sharing thin film transistor T3 of the n-th row discharges toward the main pixel electrode 111 of the n+1th row sub-pixel 10 of opposite polarity.
When the n+1th row scan line 30 inputs a row on signal, the polarity of the data signal to be charged is the same as that of the data signal of the n-th row, so that the n-th row charge sharing thin film transistor T3 is discharged to precharge the n+1th row main pixel electrode 111, and the charging capability of the n+1th row main pixel electrode 111 is enhanced, so that the charging rate is improved, thereby improving the display effect of the display panel 100.
When the sub-pixels 10 in the n+1 th row are charged, the thin film transistors in the n-th row are turned off, and the charging of the n-th row is not affected.
The charge sharing thin film transistor T3 of the sub-pixel 10 of the present row may be connected to the main pixel electrode 111 of the sub-pixel 10 of the previous row or connected to the main pixel electrode 111 of the sub-pixel 10 of the next row according to the scanning direction, and the specific connection position is designed correspondingly according to the requirement, which is not limited herein.
The connection manner of the conductive structure 13 and the main pixel electrode 111 of another row may be selected correspondingly according to the precharge effect and the routing requirement, for example, the edge position or the center position of the main pixel electrode 111 connected to another row, and the specific manner is not limited.
Meanwhile, the conductive structure 13 may be made of a material of a corresponding type, and in order to ensure the display effect and the discharge effect, the conductive structure 13 is an indium tin oxide semiconductor transparent conductive film (Indium Tin Oxides, ITO).
Optionally, each sub-pixel 10 further includes a routing area 14, and the routing area 14 is located between the main pixel electrode 111 and the sub-pixel electrode 121 of each sub-pixel 10;
the scanning lines 30, the main thin film transistor T1, the sub-thin film transistor T2 and the charge sharing thin film transistor T3 are correspondingly arranged in the routing areas 14, each routing area 14 traverses the middle areas of the main pixel electrode 111 and the sub-pixel electrode 121 of each row of sub-pixels 10 to form adjacent rows of routing areas 14, the scanning lines 30 do not need to be bent along the row direction, and the manufacturing process of the array substrate 1 is simplified.
Compared with the prior art, the embodiment of the application has the beneficial effects that: in the array substrate 1, the source electrode of the charge sharing thin film transistor T3 of each sub-pixel 10 is connected with the main pixel electrode 111 of the sub-pixel 10 of another row in the same column through the conductive structure 13, the sub-pixel 10 of the row and the sub-pixel 10 of another row in the same column are driven row by row, the charge sharing thin film transistor T3 discharges through the main pixel electrode 111 of the other row, the common electrode of the original penetrating structure becomes a plurality of segmented conductive structures 13, the aperture ratio of the array substrate 1 is improved, and meanwhile, the main pixel electrode 111 of the other row is precharged, the charging rate of the main pixel 11 is improved, and the display effect of the display panel 100 is improved.
Example two
Based on the first embodiment, as shown in fig. 3 and 4, the conductive structure 13 is arranged in different layers from the main pixel electrode 111, the main pixel electrode 111 is arranged in the same layer as the sub pixel electrode 121, the conductive structure 13 extends along the right lower part of the vertical trunk of the sub pixel electrode 121 in the current row in the same column, and is connected with the main pixel electrode 111 in the next row in the same column through the via hole 15.
In this embodiment, the main pixel electrode 111 and the sub pixel electrode 121 have stripe-shaped vertical trunks, the vertical trunks divide the main pixel electrode 111 and the sub pixel electrode 121 into display domains with equal sizes on two sides respectively, the main pixel electrode 111 and the sub pixel electrode 121 further include stripe-shaped horizontal trunks, the centers of the vertical trunks and the horizontal trunks vertically intersect, the pixel electrode is equally divided into four display domains, the conductive structure 13 extends along the different layer below the vertical trunks of the sub pixel electrode 121 on the same row and is connected with the main pixel electrode 111 on the next row, the conductive structure 13 runs along the middle position of the display domains of the pixel electrode, and the storage capacitor formed by the conductive structure 13 and the pixel electrode keeps in a stable state without affecting the display effect.
The conductive structures 13 may be disposed corresponding to the via positions of the pixel electrodes, and may be disposed at an edge side of the main pixel electrode 111, or at an inner center point.
Example III
Based on the second embodiment, refinement and optimization are performed, in order to simplify the manufacturing process and structure of the array substrate 1, the conductive structures 13 and the via holes of the pixel electrodes are disposed on the edge side of the main pixel electrode 111, specifically, the main pixel electrode 111 and the sub pixel electrode 121 respectively include four display domains;
the main pixel electrode 111 includes two identical first and second display domains of the sub-pixel electrode 121 adjacent to one row on the same column, and two identical third and fourth display domains of the sub-pixel electrode 121 distant from one row on the same column;
with continued reference to fig. 3 and fig. 4, the conductive structure 13 extends along the lower portion of the vertical trunk of the sub-pixel electrode 121 in the current row in the same column to the position right below the edge center points of the first display domain and the second display domain in the main pixel electrode 111 in the next row in the same column, and is connected to the main pixel electrode 111 through the via hole 15, and the position of the via hole 15 can be directly arranged in the gap between the adjacent rows in the same column, so that the display domains corresponding to the main pixel electrode 111 and the sub-pixel electrode 121 are not affected, the overall display effect of the display panel 100 is ensured, meanwhile, the length of each conductive structure 13 is shortened, and only the wiring from the lower portion of the sub-pixel electrode 121 is needed, and the manufacturing process and structure of the array substrate 1 are simplified.
Example IV
Based on the refinement and optimization performed on the basis of the second embodiment, in order to ensure the charging effect of each display domain of the main pixel electrode 111, the same charging rate is maintained, and in another embodiment, as shown in fig. 5 and 6, the conductive structure 13 extends to just below the center positions of four display domains of the main pixel electrode 111 of the next row in the same column along the lower side of the vertical trunk of the sub pixel electrode 121 of the current row in the same column, and is connected to the main pixel electrode 111 through the via hole 15.
In this embodiment, the position of the via hole 15 is set at the center of four display domains of the main pixel electrode 111, when the shared thin film transistor T3 discharges to the main pixel electrode 111 through the conductive structure 13, the position of the via hole 15 corresponds to a charging end, each display domain has a path with the same size relative to the charging end, the time for the charge to reach the corresponding position of each display domain is equal, the charging efficiency is the same, and the display effect is ensured.
Example five
Based on the refinement and optimization performed on the basis of the first embodiment, as shown in fig. 7 and 8, the conductive structure 13 is disposed in different layers from the main pixel electrode 111, the main pixel electrode 111 is disposed in the same layer as the sub-pixel electrode 121, and the array substrate 1 further includes:
a first common electrode 112, each of the main pixel electrodes 111 overlapping an edge portion of the first common electrode 112 to form a main storage capacitor, and each of the sub pixel electrodes 121 overlapping an edge portion of the first common electrode 112 to form a sub storage capacitor;
the conductive structure 13 is arranged in different layers with the first common electrode 112;
the conductive structure 13 extends along the right above or right below the first common electrode 112 and is connected to the edge position of the corresponding display domain of the main pixel electrode 111 of the next row of the same column through the via hole 15.
In this embodiment, each main pixel electrode 111 overlaps with the edge portion of the first common electrode 112 to form a main storage capacitor, each sub pixel electrode 121 overlaps with the edge portion of the first common electrode 112 to form a sub storage capacitor, so as to ensure that the sub pixel 10 displays the picture normally in the off state of the main thin film transistor T1 and the sub thin film transistor T2, each first common electrode 112 is connected with a common electrode voltage signal with the same size, so as to ensure the stability of the common electrode voltage signal, and the voltage signals of the first common electrode 112 on the array substrate 1 and the common electrode cf_com on the color film substrate 2 are the same, thereby shielding the irregular electric field at the pixel edge and avoiding the occurrence of dark marks due to the disorder of liquid crystal molecule guiding.
Meanwhile, since the first common electrode 112 is distributed at the edges of each main pixel 11 and each sub-pixel 12 of the array substrate 1, the conductive structure 13 follows the first common electrode 112 and is connected from the sub-pixel electrode 121 of a sub-pixel on the same row to the main pixel electrode 111 of a sub-pixel on the same row, so that the wiring is convenient, the manufacturing process of the array substrate 1 can be simplified, and meanwhile, when the conductive structure is connected to the edge position of a display domain, the display domains corresponding to the main pixel electrode 111 and the sub-pixel electrode 121 are not affected, and the overall display effect of the display panel 100 is ensured.
Further, in order to ensure the charging effect of each display domain of the main pixel electrode 111, the same charging rate is maintained, as shown in fig. 9, the conductive structure 13 further extends along the lower portion of the horizontal trunk of the main pixel electrode 111 in the next row in the same column and is connected to the center position of the corresponding display domain of the main pixel electrode 111 through the via hole 15, when the sharing thin film transistor T3 discharges to the main pixel electrode through the conductive structure 13, the position of the via hole 15 is equivalent to the charging end, each display domain has a path with the same size relative to the charging end, the time for the charge reaching the corresponding position of each display domain is equal, the charging efficiency is the same, and the display effect is ensured.
Example six
Based on the first embodiment, refinement and optimization are performed, as shown in fig. 10 and 11, the conductive structure 13 is arranged in different layers from the main pixel electrode 111, the main pixel electrode 111 is arranged in the same layer as the sub pixel electrode 121, and the conductive structure 13 is arranged in different layers from the data line 20;
the conductive structure 13 extends along the right above or right below the data line 20 commonly connected to the column sub-pixels 10, and is connected to the edge position of the corresponding display domain of the main pixel electrode 111 of the next row of the column.
In this embodiment, the main pixels 11 and the sub-pixels 12 in the same column are connected with the same data line 20, so that the conductive structure 13 follows the routing path of the data line 20, which can simplify the manufacturing process of the array substrate 1, facilitate routing, and meanwhile, when connected to the edge position of the display domain, the display domains corresponding to the main pixel electrode 111 and the sub-pixel electrode 121 are not affected, so as to ensure the overall display effect of the display panel 100.
Further, in order to ensure the charging effect of each display domain of the main pixel electrode 111, the same charging rate is maintained, as shown in fig. 12, the conductive structure 13 further extends along the lower portion of the horizontal trunk of the main pixel electrode 111 in the next row in the same column and is connected to the center position of the corresponding display domain of the main pixel electrode 111 through the via hole 15, when the sharing thin film transistor T3 discharges to the main pixel electrode 111 through the conductive structure 13, the position of the via hole 15 is equivalent to the charging end, each display domain has a path with the same size relative to the charging end, the time for the charge reaching the corresponding position of each display domain is equal, the charging efficiency is the same, and the display effect is ensured.
Example seven
The present application also proposes a display panel 100, as shown in fig. 13, where the display panel 100 includes a color film substrate 2, a liquid crystal layer 3, and an array substrate 1, and the specific structure of the array substrate 1 refers to the foregoing embodiments, and since the present display panel 100 adopts all the technical solutions of all the foregoing embodiments, at least has all the beneficial effects brought by the technical solutions of the foregoing embodiments, which are not described herein in detail.
In this embodiment, the color film substrate 2 includes an upper polarizer, a color filter, a common electrode cf_com and an upper alignment layer, the array substrate 1 includes a lower alignment layer, a driving layer and a lower polarizer, wherein the driving layer is a thin film transistor driving layer, the driving layer is used to drive liquid crystal molecules of the liquid crystal layer 3 in cooperation with the common electrode layer, and the array substrate 1 is provided with corresponding data lines 20, scan lines 30, a pixel array and a first common electrode.
Example eight
The present application also provides a display device, as shown in fig. 14, which includes a backlight module 300, a display panel driving circuit 200 and a display panel 100, and the specific structure of the display device refers to the above embodiments. The display panel driving circuit 200 is correspondingly connected with the display panel 100, and the backlight module 300 is disposed opposite to the display panel 100.
In this embodiment, the display panel driving circuit 200 includes a source driving circuit, a gate driving circuit, and a common electrode voltage circuit, and may further include a timing controller and a power management integrated circuit required for driving, where the timing controller controls the source driving circuit and the gate driving circuit to scan line by line, and the common electrode voltage circuit obtains an analog voltage output by the power management integrated circuit, converts the analog voltage into a common electrode voltage signal with a corresponding size, and outputs the common electrode voltage signal to the common electrode cf_com of the color film substrate 2 through the array substrate 1 and the like, and outputs the common electrode voltage signal to the first common electrode 112 on the array substrate 1, and the common electrode voltage signal on the common electrode cf_com of the color film substrate 2 cooperates with a data signal output by the source driving circuit to drive liquid crystal molecules, and cooperates with the backlight module 300 to display corresponding image information.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. An array substrate comprises a plurality of data lines, a plurality of scanning lines and a pixel array, wherein the data lines are used for inputting data signals with corresponding polarities, the scanning lines are used for inputting row-by-row starting signals, the pixel array comprises sub-pixels which are arranged in an array manner, and each sub-pixel comprises a main pixel and a sub-pixel which are respectively connected with the same data line and the same scanning line;
the main pixel comprises a main pixel electrode and a main thin film transistor, and the main pixel electrode is correspondingly connected with the data line and the scanning line through the main thin film transistor; the sub-pixel comprises a sub-pixel electrode, a sub-thin film transistor and a charge sharing thin film transistor; the sub-pixel electrode is correspondingly connected with the data line and the scanning line through the sub-thin film transistor; the method is characterized in that:
the grid electrode of the charge sharing thin film transistor is connected with the corresponding scanning line, the drain electrode of the charge sharing thin film transistor is connected with the secondary pixel electrode, and the source electrode of the charge sharing thin film transistor is connected with the main pixel electrode of the sub-pixel of the other row of the same column through a conductive structure, wherein the sub-pixel of the row and the sub-pixel of the other row of the same column are driven row by row in sequence.
2. The array substrate of claim 1, wherein the conductive structure is disposed in different layers from the main pixel electrode, the main pixel electrode is disposed in the same layer as the sub pixel electrode, and the conductive structure extends along a direction right under a vertical trunk of the sub pixel electrode in the current row in the same column and is connected to the main pixel electrode in the next row in the same column through a via hole.
3. The array substrate of claim 2, wherein the main pixel electrode and the sub pixel electrode each include four display domains;
the main pixel electrode comprises a first display domain and a second display domain which are adjacent to two same rows of sub-pixel electrodes on the same row, and a third display domain and a fourth display domain which are far away from two same rows of sub-pixel electrodes on the same row;
the conductive structure extends to the position right below the edge center point of the first display domain and the second display domain in the main pixel electrode of the next row of the same column along the lower part of the vertical trunk of the sub pixel electrode of the current row of the same column, and is connected with the main pixel electrode through a via hole.
4. The array substrate of claim 2, wherein the main pixel electrode and the sub pixel electrode each include four display domains;
the conductive structure extends to the position right below the center positions of four display domains of the main pixel electrode in the next row of the same column along the lower part of the vertical trunk of the sub pixel electrode in the current row of the same column, and is connected with the main pixel electrode through a via hole.
5. The array substrate of claim 1, wherein the conductive structure is disposed in a different layer from the main pixel electrode, the main pixel electrode is disposed in the same layer as the sub-pixel electrode, the array substrate further comprising:
a first common electrode, wherein each main pixel electrode and the edge part of the first common electrode are overlapped to form a main storage capacitor, and each sub pixel electrode and the edge part of the first common electrode are overlapped to form a sub storage capacitor;
the conductive structure and the first common electrode are arranged in different layers;
the conductive structure extends along the right upper side or the right lower side of the first common electrode and is connected to the edge position of the corresponding display domain of the main pixel electrode of the next row of the same column through a via hole.
6. The array substrate of claim 5, wherein the conductive structure further extends along a lower portion of a horizontal stem of the main pixel electrode of the next row of the same column and is connected to a center position of a corresponding display domain of the main pixel electrode through a via hole.
7. The array substrate of claim 1, wherein the conductive structure is disposed in a different layer from the main pixel electrode, the main pixel electrode is disposed in the same layer as the sub-pixel electrode, and the conductive structure is disposed in a different layer from the data line;
the conductive structure extends along the right upper side or the right lower side of the data line commonly connected with the sub-pixels in the same column and is connected to the edge position of the corresponding display domain of the main pixel electrode in the next row in the same column.
8. The array substrate of claim 7, wherein the conductive structure further extends along a lower portion of a horizontal stem of the main pixel electrode of the next row of the same column and is connected to a center position of a corresponding display domain of the main pixel electrode through a via hole.
9. A display panel, comprising a color film substrate, a liquid crystal layer, and an array substrate according to any one of claims 1 to 8, wherein the liquid crystal layer is located between the color film substrate and the array substrate.
10. A display device, comprising a backlight module, a display panel driving circuit and the display panel according to claim 9, wherein the display panel driving circuit is correspondingly connected with the display panel, and the backlight module is opposite to the display panel.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105045009A (en) * | 2015-08-24 | 2015-11-11 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and array substrate thereof |
| CN108169969A (en) * | 2017-12-26 | 2018-06-15 | 深圳市华星光电技术有限公司 | A kind of array substrate and liquid crystal display panel |
| CN113077717A (en) * | 2021-03-23 | 2021-07-06 | Tcl华星光电技术有限公司 | Display panel and display device |
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| US8896773B2 (en) * | 2012-09-19 | 2014-11-25 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Array substrate and liquid crystal display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105045009A (en) * | 2015-08-24 | 2015-11-11 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and array substrate thereof |
| CN108169969A (en) * | 2017-12-26 | 2018-06-15 | 深圳市华星光电技术有限公司 | A kind of array substrate and liquid crystal display panel |
| CN113077717A (en) * | 2021-03-23 | 2021-07-06 | Tcl华星光电技术有限公司 | Display panel and display device |
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