CN115763533A - Groove filling medium leakage-isolating homoepitaxial GaN HEMT device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a homoepitaxy GaN HEMT device with groove filling medium for isolating electric leakage and a manufacturing method thereof, which mainly solve the problem of electric leakage of a homoepitaxy interface of the conventional device. The GaN-based solar cell comprises a GaN substrate, a GaN buffer layer, a back barrier layer, a channel layer, an AlN insert layer, a barrier layer and an insulated gate medium from bottom to top, wherein ohmic contact regions are respectively arranged on two sides of the AlN insert layer and the barrier layer, source and drain electrodes are arranged on the ohmic contact regions, and a gate electrode is arranged on the insulated gate medium; the GaN buffer layer and the GaN substrate are provided with grooves, the grooves and the back surface of the GaN substrate are filled with high-thermal-conductivity materials and are covered with the high-thermal-conductivity materials to serve as electric leakage isolation layers, through holes from the bottom to the electric leakage isolation layers are arranged below ohmic contact regions of the source electrodes, and metal is deposited in the through holes and on the lower portions of the electric leakage isolation layers to form back electrodes. The invention has no homogeneous epitaxial interface electric leakage, high output current and power density and high heat dissipation efficiency, and can be used for microwave power amplifiers and radio frequency integrated circuit chips.

Description

Homoepitaxial GaN HEMT device with groove filling dielectric isolation leakage and its fabrication method

technical field

The invention belongs to the technical field of semiconductor devices, in particular to a homoepitaxial GaN high electron mobility transistor HEMT, which can be used for making microwave power amplifiers and radio frequency integrated circuit chips.

Background technique

The third-generation wide-bandgap semiconductor material GaN has important applications in high-frequency, high-power, high-efficiency solid-state microwave and millimeter-wave devices and power amplifiers, and has become a research hotspot and strategic competition point in the field of microelectronic devices in recent years. GaN materials have strong spontaneous polarization and piezoelectric polarization effects, and the two-dimensional electron gas with high surface density and high mobility in its heterojunction materials is the key to realizing high-efficiency switching of devices and high-frequency and high-power applications. As a mainstream device structure, GaN HEMT has gained market application in the fields of broadband communication and information perception after nearly 30 years of structural innovation and process improvement.

In order to further improve the working frequency, output power and work efficiency of GaN HEMT devices, the innovation of device structure design and the application of new materials and the development of device technology have become the main ways to improve the performance of devices, in which the material epitaxy has changed from heteroepitaxy to self-supporting gallium nitride Homoepitaxial growth on substrates. When GaN HEMT devices are heteroepitaxial on Si, SiC or sapphire substrates, there are high-density dislocation defects in the material, which will cause vertical leakage and reliability degradation of the device, while the parasitic leakage channels at the homoepitaxial interface become the limit breakdown main factor of voltage. The conventional GaN HEMT device structure is shown in Figure 1. The bottom-up structure is: substrate, nucleation layer, GaN buffer layer, channel layer, insertion layer, barrier layer, and the barrier layer is provided with a gate An electrode, a source electrode and a drain electrode are respectively arranged on the ohmic contacts of the source and drain regions. This device structure has the following disadvantages:

One is that in the heteroepitaxial GaN buffer layer, the high-density dislocations caused by lattice mismatch will enter the active region of the device along the epitaxial direction of the material, scattering the carrier transport, and forming a vertical leakage channel at the same time. The breakdown voltage of the device is reduced, and the reliability of the device is degraded.

The second is that the heteroepitaxial GaN buffer layer needs to adopt a nucleation layer structure. The growth process, material quality and thickness of the structure directly determine the crystal quality and transport characteristics of the GaN epitaxial material on it. The process control is difficult and the repeatability and consistency are poor. .

Third, when the GaN buffer layer is homoepitaxial, there is a high concentration of n-type Si impurities at the homoepitaxial interface between the self-supporting GaN substrate and the GaN material, which is difficult to completely remove and will introduce parasitic leakage channels, which will seriously Reduce the breakdown voltage and output power density of homoepitaxial GaN HEMT devices.

Fourth, in the homoepitaxial GaN buffer layer, in order to solve the problem of parasitic leakage at the homoepitaxial interface, in-situ growth is used to introduce Fe or C impurities to compensate, which will cause impurity diffusion and memory effects, and C impurities act as deep level acceptors Not suitable for use in microwave power devices.

Fifth, the thermal conductivity of the self-supporting GaN single crystal substrate is low, which will limit the normal operation of homoepitaxial GaN HEMT devices at higher temperatures, and cannot meet high-power and high-temperature applications.

Contents of the invention

The purpose of the present invention is to address the shortcomings of the above-mentioned prior art, and propose a homoepitaxial GaN HEMT device and a manufacturing method thereof with groove filling dielectric isolation leakage, so as to block the parasitic leakage channel of the homoepitaxial interface and realize extremely low-defect gallium nitride Material epitaxial growth improves device heat dissipation efficiency, output power density and reliability.

Technical scheme of the present invention is realized like this:

1. A homoepitaxial GaN HEMT device with groove filling dielectric isolation leakage, comprising a GaN substrate, a GaN buffer layer, a back barrier layer, a channel layer, an AlN insertion layer, a barrier layer and an insulating gate from bottom to top Ohmic contacts are provided on the left and right sides of the medium, the AlN insertion layer and the barrier layer, the source and drain electrodes are respectively provided on the ohmic contacts, and the gate electrode is provided on the insulating gate dielectric, which is characterized in that:

A groove is etched between the GaN substrate and the GaN buffer layer, the groove and the back of the GaN substrate are filled and covered with a high thermal conductivity material as a leakage isolation layer, so as to block the parasitic leakage channel of the homoepitaxial interface;

A through hole to the leakage isolation layer is provided under the ohmic contact area of the source electrode, and a back electrode is provided in the through hole and the lower part of the leakage isolation layer to reduce the parasitic capacitance of the device and achieve better high-frequency characteristics.

Further, the GaN substrate adopts a self-supporting gallium nitride substrate;

Further, the thickness of the GaN buffer layer is 300nm-6000nm;

Further, the back barrier layer adopts any one of graded composition AlGaN, AlGaN/GaN superlattice, and AlGaN/AlN superlattice, with a thickness of 50nm-100nm;

Further, the channel layer adopts In _x Ga _1-x N, wherein the composition 0≤x≤1, and its thickness is 10nm-30nm;

Further, the AlN insertion layer has a thickness of 1nm-2nm;

Further, the barrier layer is any one of AlN, AlGaN, InAlN, ScAlN, AlPN, BAlN, BPN, YAlN, and its thickness is 3nm-30nm;

Further, the thickness of the groove deep into the GaN buffer layer is 100-200nm;

Further, the leakage isolation layer is any one of diamond, c-BN, and AlN, and its thickness is 10 μm-20 μm;

Further, the insulating gate dielectric layer is any one of Al ₂ O ₃ , HfO ₂ , and HfAlO dielectric layers, and its thickness is 3nm-20nm.

2. A method for making a homoepitaxial GaN HEMT device with dielectric isolation leakage for filling grooves, comprising the steps of:

1) On the GaN substrate, a GaN buffer layer with a thickness of 300nm-6000nm is grown by metal-organic chemical vapor deposition technology or molecular beam epitaxy;

2) growing a back barrier layer with a thickness of 50nm-100nm on the GaN buffer layer by metal-organic chemical vapor deposition technology or molecular beam epitaxy;

3) growing a channel layer with a thickness of 10nm-30nm on the back barrier layer by metal organic chemical vapor deposition technology or molecular beam epitaxy;

4) growing an AlN insertion layer with a thickness of 1nm-2nm on the channel layer by metal-organic chemical vapor deposition technology or molecular beam epitaxy;

5) growing a barrier layer with a thickness of 3nm-30nm on the AlN insertion layer by metal organic chemical vapor deposition technology or molecular beam epitaxy;

6) Using a chemical mechanical polishing method to reduce the thickness of the GaN substrate from the backside to 50 μm-150 μm;

7) Use a photolithography process to select the area to be etched on the back of the GaN substrate, use a dry etching process to etch the GaN substrate and the GaN buffer layer, and etch a groove with a depth of 100nm-200nm deep into the GaN buffer layer ;

8) Deposit a leakage isolation layer with a thickness of 10 μm-20 μm in the etched groove and the back of the GaN substrate, and perform chemical mechanical polishing on the surface of the leakage isolation layer after deposition to smooth the surface of the material;

9) Using a photolithography process to select device source and drain ohmic contact area patterns at both ends of the barrier layer, and dry-etching them to the top of the channel layer to form grooves in the ohmic contact area;

10) Using metal-organic chemical vapor deposition technology or molecular beam epitaxy, grow a Si-doped n-type GaN layer with a thickness of 4nm-32nm in the groove of the ohmic contact region, wherein the Si doping concentration is (1-5)× 10 ²⁰ cm ^-3 , forming an ohmic contact area;

11) Using an electron beam evaporation process, deposit ohmic contact metal Ti/Al/Ni/Au in the ohmic contact area of the source electrode and the drain electrode, and anneal in a nitrogen atmosphere at 830°C to form the source electrode and the drain electrode;

12) Depositing an insulating gate dielectric layer with a thickness of 3nm-20nm on the barrier layer by using an atomic layer deposition process;

13) Selecting a gate electrode pattern on the surface of the insulating gate dielectric layer by photolithography, and depositing a Ni/Au metal combination on the pattern by electron beam evaporation process to form a gate electrode;

14) Carry out backhole etching under the leakage isolation layer by using the back channel process to form a through hole from the leakage isolation layer to the ohmic contact area under the source electrode;

15) Use magnetic sputtering process to fill the hole wall with TiW as an alloy barrier layer, then fill the through hole with Au, and continue to electroplate Au with a thickness of 8 μm-10 μm on the leakage isolation layer through the electroplating process, and at the bottom of the leakage isolation layer A back electrode is formed to complete device fabrication.

Compared with the prior art, the present invention has the following advantages:

1. Since the present invention uses a self-supporting GaN substrate for GaN HEMT material homoepitaxy, it can realize zero-stress epitaxy of GaN heterojunction materials, effectively reduce the dislocation density in heteroepitaxial GaN materials, improve material crystal quality, and reduce The vertical leakage channel improves the breakdown voltage and output power of the device.

2. The present invention effectively blocks the parasitic leakage channel formed by the homoepitaxial interface between the GaN buffer layer and the GaN substrate due to the use of the leakage isolation layer of the groove filling medium, and can improve the breakdown voltage of the GaN HEMT device.

3. The present invention uses the leakage isolation layer of the groove filling medium to block the parasitic leakage channel formed at the homoepitaxial interface, and does not introduce in-situ Fe or C doping to compensate the parasitic Si impurities at the homoepitaxial interface, so that the material grows The process is simple, and there is no memory effect and microwave radio frequency loss.

4. In the present invention, since the source electrode is led to the back of the substrate through the through hole, the parasitic capacitance of the device is reduced, better high-frequency characteristics can be achieved, and it can be bonded to other substrates as a metal heat sink material at the same time. Realize the transfer of GaN HEMT devices.

5. The present invention can efficiently dissipate the heat generated in the active area of the device by filling the groove with a high thermal conductivity leakage isolation layer material and combining the back electrode metal on the back of the leakage isolation layer to achieve better high temperature characteristics of the device. Improves device reliability and upper operating temperature limit.

Description of drawings

Figure 1 is a structural diagram of a traditional GaN HEMT device;

Fig. 2 is a structural diagram of a homoepitaxial GaN HEMT device with groove filling dielectric isolation leakage of the present invention;

Fig. 3 is a schematic diagram of the process flow of the invention for manufacturing a homoepitaxial GaN HEMT device with dielectric isolation leakage filled in grooves.

Detailed ways

Referring to Fig. 2, the homoepitaxial GaN HEMT device structure of the groove filling dielectric isolation leakage of the present invention comprises a GaN substrate 1, a GaN buffer layer 2, a back barrier layer 3, a channel layer 4, an AlN insertion layer 5, a potential The barrier layer 6, the groove 7, the leakage isolation layer 8, the insulating gate dielectric 9, the back electrode 10, the AlN insertion layer 5 and the barrier layer 6 are respectively provided with ohmic contact regions on the left and right sides, and the ohmic contact regions are respectively provided with source, The drain electrode is provided with a gate electrode on the insulating gate dielectric. in:

The GaN substrate 1 is a self-supporting gallium nitride substrate;

The GaN buffer layer 2 is located above the GaN substrate 1, and its thickness is 300nm-6000nm;

A groove 7 is provided between the GaN substrate 1 and the GaN buffer layer 2, and its depth into the GaN buffer layer 2 is 100nm-200nm;

The groove 7 and the back side of the GaN substrate 1 are filled and covered with the leakage isolation layer 8, so as to block the parasitic leakage channel of the homoepitaxial interface;

The leakage isolation layer 8 is any one of diamond, c-BN, and AlN, and its thickness is 10 μm-20 μm;

The back barrier layer 3 is located above the GaN buffer layer 2, which adopts any one of graded composition AlGaN, AlGaN/GaN superlattice, and AlGaN/AlN superlattice, with a thickness of 50nm-100nm;

The channel layer 4 is located above the back barrier layer 3, which uses In _x Ga _1-x N, composition 0≤x≤1, and a thickness of 10nm-30nm;

The AlN insertion layer 5 is located above the channel layer 4, and its thickness is 1nm-2nm;

The barrier layer 6 is located above the AlN insertion layer 5, using any one of AlN, AlGaN, InAlN, ScAlN, AlPN, BAlN, BPN, YAlN, and its thickness is 3nm-30nm;

The insulating gate dielectric layer 9 is located above the barrier layer 6, and it adopts any one of Al ₂ O ₃ , HfO ₂ , and HfAlO dielectric layers, with a thickness of 3nm-20nm;

The source electrode is etched from the back of the leakage isolation layer to the ohmic contact area through the back channel process, and the back electrode 10 is formed by filling the through hole with metal and electroplating metal on the leakage isolation layer 8 .

Referring to FIG. 3 , the present invention provides the method for manufacturing a homoepitaxial GaN HEMT device with dielectric isolation leakage filled with grooves, and provides the following three embodiments.

Embodiment 1, making a self-supporting GaN substrate, a diamond leakage isolation layer, a graded composition AlGaN back barrier layer with a thickness of 100nm, a GaN channel with a thickness of 30nm, and an Al _0.25 Ga _0.75 N barrier layer with a thickness of 30nm Homoepitaxial GaN HEMT devices.

Step 1, depositing a GaN buffer layer, as shown in Figure 3(a).

A GaN buffer layer with a thickness of 6000nm is deposited on a GaN substrate by using metal organic chemical vapor deposition technology. 150sccm, hydrogen flow rate is 3000sccm.

Step 2, depositing a graded composition AlGaN back barrier layer, as shown in Figure 3(b).

A graded composition AlGaN back barrier layer with a thickness of 100nm is deposited on the GaN buffer layer by metal-organic chemical vapor deposition technology. The source flow rate is 150 sccm, the aluminum source flow rate is 20 sccm, and the hydrogen gas flow rate is 3000 sccm.

Step 3, depositing a GaN channel layer, as shown in Fig. 3(c).

Use metal organic chemical vapor deposition technology to deposit a 30nm thick GaN channel layer on the graded composition AlGaN back barrier layer. The deposition process conditions are: at a temperature of 1250 ° C, a pressure of 50 Torr, and a gallium source flow rate of 150sccm, the flow rate of ammonia gas is 2000sccm, and the flow rate of hydrogen gas is 3000sccm.

Step 4, depositing an AlN insertion layer, as shown in Figure 3(d).

A metal-organic chemical vapor deposition technique was used to deposit an AlN insertion layer with a thickness of 1nm on the GaN channel layer. is 2000 sccm, and the hydrogen flow rate is 3000 sccm.

Step five, depositing an AlGaN barrier layer, as shown in Fig. 3(e).

A metal-organic chemical vapor deposition technique is used to deposit an Al _0.25 Ga _0.75 N barrier layer with a thickness of 30 nm on the AlN insertion layer. The deposition process conditions are: temperature 1250 ° C, pressure 50 Torr, ammonia gas flow rate 2000 sccm , Ga source flow is 60sccm, aluminum source flow is 20sccm, hydrogen flow is 3000sccm.

Step six, thinning the GaN substrate, as shown in Figure 3(f).

The GaN substrate was thinned to 50 μm using chemical mechanical polishing. First rough grinding for high-speed thinning, and then fine grinding to improve the flatness of the GaN substrate backside.

Step seven, etching the GaN substrate and the GaN buffer layer to form grooves, as shown in Figure 3(g).

A photolithographic process is used to select an etching area on the back of the GaN substrate, a dry etching process is used to etch the GaN substrate and the GaN buffer layer, and a groove with a depth of 100nm deep into the GaN buffer layer is etched.

Step 8, depositing a diamond leakage isolation layer, as shown in Figure 3(h).

Using microwave plasma chemical vapor deposition technology to deposit a diamond leakage isolation layer with a thickness of 10 μm in the groove and on the back of the GaN substrate, after deposition, chemical mechanical polishing is performed on the surface of the diamond leakage isolation layer. The deposition process The conditions are: microwave power 1400W, air pressure 21kPa, plasma power density 700W/cm ³ , temperature 850°C, CH ₄ volume fraction 1.0%, H ₂ flow rate 200ml/min.

Step 9, dry etching to form grooves in the source and drain ohmic contact regions, as shown in FIG. 3(i).

Use photolithography to select the ohmic contact pattern of the source electrode and drain electrode on both sides of the Al _0.25 Ga _0.75 N barrier layer, and use RIE dry etching technology to process the two ends of the barrier layer to the top of the channel layer to form the source and drain The etching process conditions for the groove of the ohmic contact area are: the flow rate of Cl ₂ is 15 sccm, the pressure of the reaction chamber is 12 mTorr, and the electrode power is 180 W.

Step ten, making ohmic contact area, as shown in Fig. 3(j).

A Si-doped n-type GaN layer with a thickness of 31nm was deposited in the groove of the ohmic contact region using metal organic chemical vapor deposition technology, in which the Si doping concentration was 1×10 ²⁰ cm ^-3 to form the left and right ohmic contact regions. The deposition process conditions are: temperature 1250°C, pressure 50 Torr, ammonia gas flow 2000 sccm, gallium source flow 150 sccm, hydrogen gas flow 3000 sccm, silane flow 500 sccm.

Step eleven, making source and drain electrodes, as shown in Figure 3(k).

Using the electron beam evaporation process, the Ti/Al/Ni/Au metal combination with a thickness of 0.02μm/0.05μm/0.04μm/0.04μm is deposited on the ohmic contact area of the source electrode and the drain electrode respectively, and the temperature is 830℃. Rapid thermal annealing in nitrogen atmosphere for 30s to form source electrode and drain electrode. The process conditions for depositing metal are: vacuum degree is less than 1.2×10 ^-3 Pa, power is 400W, and evaporation rate is

In step 12, deposit an Al ₂ O ₃ insulating gate dielectric layer, as shown in FIG. 3(l).

An Al ₂ O ₃ insulating gate dielectric layer with a thickness of 10 nm is grown on the Al _0.25 Ga _0.75 N barrier layer by atomic layer deposition.

Step thirteen, making a gate electrode, as shown in FIG. 3(m).

Use photolithography to make a mask on the Al ₂ O ₃ insulating gate dielectric layer, use electron beam evaporation technology to deposit metal on the selected area of the Al ₂ O ₃ insulating gate dielectric layer, and make the gate, in which the deposited metal It is a Ni/Au metal combination, the metal thickness is 0.02μm/0.3μm, the process conditions for its deposition are: the vacuum degree is less than 1.4×10 ^-3 Pa, the power range is 400-800W, and the evaporation rate is

In step fourteen, etching is performed using a backtracking process to form via holes, as shown in FIG. 3(n).

A back channel process is adopted to form a via hole from the leakage isolation layer to the ohmic contact region under the source electrode by using an inductively coupled plasma etching technique.

Step fifteen, filling the through hole with metal and electroplating metal on the leakage isolation layer, as shown in FIG. 3( o ).

Fill the hole wall with TiW as an alloy barrier layer by using the magnetic sputtering process, then fill the through hole with Au, and continue to electroplate Au with a thickness of 8 μm on the leakage isolation layer through the electroplating process, and form a back electrode at the bottom of the leakage isolation layer. Complete device fabrication.

Embodiment 2, using a self-supporting gallium nitride substrate, c-BN leakage isolation layer, AlGaN/GaN superlattice back barrier layer thickness is 80nm, In _0.1 Ga _0.9 N channel layer thickness is 20nm, Sc _0.18 Al GaN HEMT device with _0.82 N barrier layer thickness of 10nm.

Step 1, depositing a GaN buffer layer on the GaN substrate, as shown in Figure 3(a).

Using metal-organic chemical vapor deposition technology, under the process conditions of temperature 1150°C, pressure 60Torr, ammonia flow rate 2000sccm, gallium source flow rate 90sccm, hydrogen flow rate 3000sccm, the deposition thickness is 3000nm on the GaN substrate GaN buffer layer.

Step 2, depositing an AlGaN/GaN superlattice back barrier layer on the GaN buffer layer, as shown in Figure 3(b).

Using metal-organic chemical vapor phase epitaxy technology, under the process conditions of temperature 1150°C, pressure 60Torr, ammonia flow rate 2000sccm, gallium source flow rate 90sccm, aluminum source flow rate 25sccm, hydrogen flow rate 3000sccm, on a GaN substrate An Al _0.2 Ga _0.8 N/GaN superlattice back barrier layer with a growth period of 20 and a thickness of 80 nm.

Step 3, depositing an In _0.1 Ga _0.9 N channel layer on the AlGaN/GaN superlattice back barrier layer, as shown in Figure 3(c).

Using metal-organic chemical vapor deposition technology, under the process conditions of temperature 700°C, pressure 300Torr, ammonia flow rate 2000sccm, indium source flow rate 120sccm, gallium source flow rate 60sccm, nitrogen flow rate 3000sccm, AlGaN/GaN An In _0.1 Ga _0.9 N channel layer with a thickness of 20 nm is deposited on the superlattice back barrier layer.

Step 4, depositing an AlN insertion layer on the In _0.1 Ga _0.9 N channel layer, as shown in Figure 3(d).

Using metal organic chemical vapor deposition technology, under the process conditions of temperature 700 ℃, pressure 300 Torr, aluminum source flow rate 25 sccm, ammonia gas flow rate 2000 sccm, nitrogen gas flow rate 3000 sccm, on the In _0.1 Ga _0.9 N channel layer An AlN insertion layer is deposited to a thickness of 1.5 nm.

Step 5, depositing a Sc _0.18 Al _0.82 N barrier layer on the AlN insertion layer, as shown in Figure 3(e).

Using metal organic chemical vapor deposition technology, under the process conditions of temperature 1000 ℃, pressure 300 Torr, aluminum source flow rate 25 sccm, scandium source flow rate 10 sccm, ammonia gas flow rate 2000 sccm, nitrogen gas flow rate 3000 sccm, the AlN insertion layer A Sc _0.18 Al _0.82 N barrier layer with a thickness of 10 nm is deposited thereon.

Step 6, thinning the GaN substrate, as shown in Figure 3(f).

Using the chemical mechanical polishing method, the rough grinding is used to reduce the thickness at high speed, and then the fine grinding is used to improve the flatness of the back surface of the GaN substrate, and the thickness is reduced to 100 μm.

Step 7, etching the GaN substrate and the GaN buffer layer to form grooves, as shown in Figure 3(g).

A photolithographic process is used to select an etching area on the back of the GaN substrate, a dry etching process is used to etch the GaN substrate and the GaN buffer layer, and a groove with a depth of 150 nm deep into the GaN buffer layer is etched.

Step 8, depositing a leakage isolation layer on the back of the GaN substrate, as shown in FIG. 3(h).

Using metal-organic chemical vapor phase technology, under the conditions of temperature 1300°C, pressure 400Torr, boron source flow rate 20μmol/min, ammonia flow rate 3000sccm, hydrogen flow rate 2000sccm, deposit in the groove and on the back of the GaN substrate Cubic boron nitride (c-BN) with a thickness of 15 μm is deposited, and then chemical mechanical polishing is performed on the surface of the c-BN leakage isolation layer.

Step 9, dry etching to form grooves in the source and drain ohmic contact regions, as shown in FIG. 3(i).

Use photolithography to select the ohmic contact pattern of source electrode and drain electrode on the surface of Sc _0.18 Al _0.82 N barrier layer, use RIE dry etching technology, when the Cl ₂ flow rate is 20 sccm, the reaction chamber pressure is 15 mTorr, and the electrode power is Under the process condition of 200W, both ends of the barrier layer are processed to the top of the channel layer to form grooves in the source and drain ohmic contact regions.

Step 10, making source-drain ohmic contact regions, as shown in Figure 3(j).

Using metal-organic chemical vapor deposition technology, under the process conditions of temperature 1150°C, pressure 60Torr, ammonia gas flow rate 2000sccm, gallium source flow rate 90sccm, hydrogen flow rate 3000sccm, silane flow rate 800sccm, concave to the ohmic contact area A Si-doped n-type GaN layer with a thickness of 11.5nm is deposited in the trench region, where the concentration of Si ions is 3×10 ²⁰ cm ^-3 , forming an ohmic contact region.

Step 11, making the source electrode and the drain electrode, as shown in Fig. 3(k).

的工艺条件下，分别在源电极和漏电极欧姆接触区上淀积厚度为0.02μm/0.05μm/0.04μm/0.04μm的Ti/Al/Ni/Au金属组合，并在温度为830℃的氮气气氛下快速热退火30s，形成源电极和漏电极。Using electron beam evaporation process, the vacuum degree is less than 1.2×10 ^-3 Pa, the power is 400W, and the evaporation rate is

Under the process conditions, the Ti/Al/Ni/Au metal combination with a thickness of 0.02μm/0.05μm/0.04μm/0.04μm is deposited on the ohmic contact area of the source electrode and the drain electrode respectively, and the nitrogen gas at a temperature of 830°C Rapid thermal annealing under atmosphere for 30s to form source and drain electrodes.

In step 12, an insulating gate dielectric layer of HfO ₂ with a thickness of 20 nm is deposited on the Sc _0.18 Al _0.82 N barrier layer by using an atomic layer deposition process, as shown in FIG. 3(l).

Step 13, fabricating a gate electrode on the insulating gate dielectric, as shown in FIG. 3(m).

的工艺条件下，在HfO₂绝缘栅介质层上淀积金属，制作栅极，其中所淀积的金属为Ni/Au金属组合，金属厚度为0.04μm/0.5μm。The gate pattern is selected on the HfO ₂ insulating gate dielectric layer by photolithography, and the electron beam evaporation technology is used. The vacuum degree is less than 1.2×10 ^-3 Pa, the power is 600W, and the evaporation rate is

Under the process conditions, metal is deposited on the HfO ₂ insulating gate dielectric layer to make the gate, wherein the deposited metal is a Ni/Au metal combination, and the metal thickness is 0.04 μm/0.5 μm.

In step 14, etching is performed using a backtracking process to form via holes, as shown in FIG. 3(n).

A back channel process is used to etch a via hole under the leakage isolation layer, and an inductively coupled plasma etching technique is used to form a via hole from the leakage isolation layer to the ohmic contact region below the source electrode.

Step 15, filling the through hole with metal and electroplating metal on the leakage isolation layer, as shown in FIG. 3( o ).

Fill the hole wall with TiW as an alloy barrier layer by using the magnetic sputtering process, then fill the through hole with Au, and continue to electroplate Au with a thickness of 9 μm on the leakage isolation layer through the electroplating process, and form a back electrode at the bottom of the leakage isolation layer. Complete device fabrication.

Embodiment 3, a GaN HEMT device using a self-supporting gallium nitride substrate, an AlN leakage isolation layer, an AlGaN/AlN back barrier layer with a thickness of 50nm, an InN channel layer with a thickness of 10nm, and an AlN barrier layer with a thickness of 3nm was fabricated.

In step A, a self-supporting GaN substrate is selected, the set temperature is 750°C, the flow rate of nitrogen gas is 0.6 sccm, the equilibrium vapor pressure of the gallium beam is 3.5×10 ^-7 Torr, and the power of the nitrogen plasma radio frequency source is 350W. In the molecular beam epitaxy method, a GaN buffer layer with a thickness of 300nm is deposited on the GaN substrate, as shown in Figure 3(a).

Step B, set the temperature to 750°C, nitrogen flow rate to 0.6 sccm, gallium beam equilibrium vapor pressure to 3.5×10 ^-7 Torr, aluminum beam equilibrium vapor pressure to 1.2× ^{10 -7 Torr} , nitrogen plasma RF source power The process condition is 350W, and the AlGaN/AlN superlattice back barrier layer with a thickness of 50nm is deposited on the GaN buffer layer by molecular beam epitaxy, as shown in Figure 3(b).

Step C, set the process conditions at a temperature of 550°C, a nitrogen gas flow rate of 0.6 sccm, an indium beam equilibrium vapor pressure of 2.0×10 ^{- 7} Torr, and a nitrogen plasma radio frequency source power of 350 W, using molecular beam epitaxy. Deposit an InN channel layer with a thickness of 10nm on the back barrier layer of the /AlN superlattice, as shown in Figure 3(c).

In step D, set the process conditions at a temperature of 550°C, a nitrogen flow rate of 0.6 sccm, an aluminum beam equilibrium vapor pressure of 1.2×10 ^{- 7} Torr, and a nitrogen plasma radio frequency source power of 350 W, using molecular beam epitaxy. An AlN insertion layer with a thickness of 2nm is deposited on the channel layer, as shown in Figure 3(d).

Step E, set the process conditions at a temperature of 720°C, a nitrogen gas flow rate of 0.6 sccm, an aluminum beam equilibrium vapor pressure of 1.2×10 ^{- 7} Torr, and a nitrogen plasma radio frequency source power of 350 W, using molecular beam epitaxy. An AlN barrier layer with a thickness of 3nm is deposited on the insertion layer, as shown in Figure 3(e).

Step F, using chemical mechanical polishing method, first rough grinding and high-speed thinning, and then fine grinding to improve the flatness of the back surface of the GaN substrate, and reduce its thickness to 150 μm, as shown in Figure 3(f).

Step G, using a photolithography process to select an etching area on the back of the GaN substrate, using a dry etching process to etch the GaN substrate and the GaN buffer layer from the back, and etching a groove deep into the GaN buffer layer with a thickness of 200nm, Figure 3(g).

In step H, the set temperature is 400°C, the vacuum degree is less than 10 ^-4 Pa, the pressure is 40Torr, the DC sputtering power is 5kW, the aluminum source flow rate is 110 sccm, the argon gas flow rate is 45 sccm, and the ammonia gas flow rate is 1000 sccm process conditions, using physical vapor deposition In the deposition technology, an AlN leakage isolation layer with a thickness of 20 μm is deposited in the groove and on the back of the GaN substrate. After deposition, the surface of the AlN leakage isolation layer is chemically mechanically polished, as shown in Figure 3(h).

Step I, adopt photolithography process, select the ohmic contact area of source electrode and drain electrode on the surface of AlN barrier layer, set Cl _The flow rate is 10sccm, the reaction chamber pressure is 10mTorr, the process condition of electrode power is 180W, use RIE dry Etching technology is used to process both ends of the barrier layer to the top of the channel layer to form grooves in the source and drain ohmic contact regions, as shown in Figure 3(i).

In step J, set the temperature to 750°C, nitrogen flow rate to 0.6 sccm, gallium beam equilibrium vapor pressure to 3.5×10 ^-7 Torr, silicon beam equilibrium vapor pressure to 2.8× ^{10 -8 Torr} , nitrogen plasma RF source power The process condition is 350W, using molecular beam epitaxy technology, depositing a Si-doped n-type GaN layer with a thickness of 5nm in the groove area of the ohmic contact area, and the concentration of Si ions is 5×10 ²⁰ cm ^-3 to form an ohmic contact area. Figure 3(j).

的工艺条件，采用电子束蒸发工艺，分别在源电极和漏电极欧姆接触区上淀积厚度为0.02μm/0.2μm/0.05μm/0.05μm的Ti/Al/Ni/Au金属组合，并在温度为830℃的氮气气氛下快速热退火30s，形成源电极和漏电极，如图3(k)。Step K, set the vacuum degree to be less than 1.2×10 ^-3 Pa, the power is 500W, and the evaporation rate is

According to the process conditions, the electron beam evaporation process is used to deposit the Ti/Al/Ni/Au metal combination with a thickness of 0.02μm/0.2μm/0.05μm/0.05μm on the ohmic contact area of the source electrode and the drain electrode respectively. Rapid thermal annealing under nitrogen atmosphere at 830°C for 30s to form source and drain electrodes, as shown in Figure 3(k).

In step L, an HfAlO insulating gate dielectric layer with a thickness of 3 nm is deposited on the AlN barrier layer by atomic layer deposition, as shown in FIG. 3(l).

的工艺条件，使用电子束蒸发技术，在HfAlO绝缘栅介质层上淀积厚度为0.03μm/0.4μm的Ni/Au金属组合，制作栅极，如图3(m)。In step M, the gate pattern is selected on the HfAlO insulating gate dielectric layer by photolithography, the vacuum degree is set to be less than 1.2×10 ^-3 Pa, the power is 500W, and the evaporation rate is

According to the process conditions, electron beam evaporation technology is used to deposit Ni/Au metal combination with a thickness of 0.03μm/0.4μm on the HfAlO insulating gate dielectric layer to make the gate, as shown in Figure 3(m).

In step N, the through hole is etched under the leakage isolation layer by using the back channel process, and the through hole from the leakage isolation layer to the ohmic contact region under the source electrode is formed by using inductively coupled plasma etching technology, as shown in FIG. 3(n).

In step O, the magnetic sputtering process is used to fill the hole wall with TiW as an alloy barrier layer, and then fill the through hole with Au, and continue to electroplate Au with a thickness of 10 μm on the leakage isolation layer through the electroplating process, forming a The back electrode completes the device fabrication, as shown in Figure 3(o).

The above descriptions are only three specific examples of the present invention, and do not constitute any limitation to the present invention. Obviously, for those skilled in the art, after understanding the content and principle of the present invention, it is possible without departing from the principle of the present invention. , In the case of the structure, various modifications and changes are made in the form and details. For example, the barrier layer can use any one of InAlN, AlPN, BAlN, BPN or YAlN in addition to AlN, AlGaN, ScAlN, but These amendments and changes based on the idea of the present invention are still within the scope of the claims of the present invention.

Claims (10)

1. A homoepitaxial GaN HEMT device with groove filling dielectric isolation leakage, comprising GaN substrate (1), GaN buffer layer (2), back barrier layer (3), channel layer (4) from bottom to top ), the AlN insertion layer (5), the barrier layer (6) and the insulating gate dielectric (9), the AlN insertion layer (5) and the barrier layer (6) are respectively provided with ohmic contact areas on the left and right sides, and on the ohmic contact area Source and drain electrodes are provided respectively, and a gate electrode is provided on the insulating gate dielectric (9), which is characterized in that: A groove (7) is etched between the GaN substrate (1) and the GaN buffer layer (2), the groove and the back of the GaN substrate (1) are filled and covered with a high thermal conductivity material as a leakage isolation layer (8), to block the parasitic leakage channel of the homoepitaxial interface; The bottom of the source electrode ohmic contact area is provided with a through hole to the leakage isolation layer (8), and a back electrode (10) is provided in the through hole and the bottom of the leakage isolation layer to reduce the parasitic capacitance of the device and achieve better high-frequency characteristics. 2. The transistor of claim 1, wherein: The GaN substrate (1) adopts a self-supporting gallium nitride substrate; The GaN buffer layer (2) has a thickness of 300nm-6000nm; The AlN insertion layer (5) has a thickness of 1nm-2nm. 3. The transistor of claim 1, wherein: The back barrier layer (3) adopts any one of graded composition AlGaN, AlGaN/GaN superlattice, and AlGaN/AlN superlattice, with a thickness of 50nm-100nm; The channel layer (4) adopts In _x Ga _1-x N, wherein the composition 0≤x≤1, and its thickness is 10nm-30nm; The barrier layer (6) is any one of AlN, AlGaN, InAlN, ScAlN, AlPN, BAlN, BPN YAlN, and its thickness is 3nm-30nm. 4. The transistor of claim 1, wherein: The thickness of the groove (7) deep into the GaN buffer layer (2) is 100-200nm; The leakage isolation layer (8) is any one of diamond, c-BN, and AlN, and its thickness is 10 μm-20 μm; The insulating gate dielectric layer (9) is any one of Al ₂ O ₃ , HfO ₂ , and HfAlO dielectric layers, and its thickness is 3nm-20nm. 5. A method for manufacturing a homoepitaxial GaN HEMT device with a groove filling dielectric isolation leakage, characterized in that it comprises the following steps: 1) On the GaN substrate (1), a GaN buffer layer (2) with a thickness of 300nm-6000nm is grown by metal-organic chemical vapor deposition technology or molecular beam epitaxy; 2) growing a back barrier layer (3) with a thickness of 50nm-100nm on the GaN buffer layer (2) by metal-organic chemical vapor deposition technology or molecular beam epitaxy; 3) growing a channel layer (4) with a thickness of 10nm-30nm on the back barrier layer (3) by metal-organic chemical vapor deposition technology or molecular beam epitaxy; 4) growing an AlN insertion layer (5) with a thickness of 1nm-2nm on the channel layer (4) by metal-organic chemical vapor deposition technology or molecular beam epitaxy; 5) growing a barrier layer (6) with a thickness of 3nm-30nm on the AlN insertion layer (5) by metal-organic chemical vapor deposition technology or molecular beam epitaxy; 6) using a chemical mechanical polishing method to reduce the thickness of the GaN substrate (1) from the back surface to 50 μm-150 μm; 7) Select the area to be etched on the back of the GaN substrate (1) using a photolithography process, etch the GaN substrate (1) and buffer layer (2) using a dry etching process, and etch a deep GaN buffer layer (2) a groove (7) with a depth of 100nm-200nm; 8) Deposit a leakage isolation layer (8) with a thickness of 10 μm-20 μm in the etched groove (7) and on the back of the GaN substrate (1), and perform a surface treatment on the surface of the leakage isolation layer (8) after deposition. Chemical mechanical polishing treatment to smooth the surface of the material; 9) Using a photolithography process to select device source and drain ohmic contact area patterns at both ends of the barrier layer, and dry-etching them to the top of the channel layer to form grooves in the ohmic contact area; 10) Using metal-organic chemical vapor deposition technology or molecular beam epitaxy, grow a Si-doped n-type GaN layer with a thickness of 4nm-32nm in the groove of the ohmic contact region, wherein the Si doping concentration is (1-5)× 10 ²⁰ cm ^-3 , forming an ohmic contact area; 11) Using an electron beam evaporation process, deposit ohmic contact metal Ti/Al/Ni/Au on the ohmic contact area of the source electrode and the drain electrode, and anneal in a nitrogen atmosphere at 830°C to form the source electrode and the drain electrode; 12) Depositing an insulating gate dielectric layer (9) with a thickness of 3nm-20nm on the barrier layer by using an atomic layer deposition process; 13) Selecting a gate electrode pattern on the surface of the insulating gate dielectric layer (9) by using a photolithography process, and then depositing a Ni/Au metal combination on the pattern by using an electron beam evaporation process to form a gate electrode; 14) Carrying out back hole etching under the leakage isolation layer (8) by using a back channel process to form a through hole from the leakage isolation layer (8) to the ohmic contact area below the source electrode; 15) Fill the hole wall with TiW as an alloy barrier layer by using a magnetic sputtering process, then fill the through hole with Au, and continue to electroplate Au with a thickness of 8 μm-10 μm on the leakage isolation layer (8) through the electroplating process. A back electrode (10) is formed at the bottom of the isolation layer (8) to complete device fabrication. 6. manufacture method as claimed in claim 5, is characterized in that, described step 1)-step 5) in metal-organic compound chemical vapor deposition technique, its processing condition is as follows: The temperature is 700°C-1250°C; The pressure is 50Torr-300Torr; Ammonia flow rate is 2000sccm; The hydrogen flow rate is 3000sccm; The nitrogen flow rate is 3000sccm; Gallium source flow is 60sccm-150sccm; Aluminum source flow rate is 2sccm-30sccm; Indium source flow is 30sccm-120sccm; Scandium source flow is 10sccm-20sccm; Yttrium source flow rate is 4sccm-20sccm; The boron source flow rate is 10μmol/min-30μmol/min; Phosphorus source flow rate is 20μmol/min-50μmol/min; Silane flow rate is 500sccm-1000sccm. 7. manufacturing method as claimed in claim 5, is characterized in that, described step 1)-step 5) in molecular beam epitaxy method, its processing condition is as follows: The temperature is 550°C-750°C; The nitrogen flow rate is 0.6sccm-2.8sccm; Scandium beam equilibrium vapor pressure is 1.2×10 ^-8 Torr-1.8×10 ^-8 Torr; The equilibrium vapor pressure of the yttrium beam is 1.0×10 ^-8 Torr-1.5×10 ^-8 Torr; The equilibrium vapor pressure of the gallium beam is 3.5×10 ^-7 Torr-8.5×10 ^-7 Torr; The equilibrium vapor pressure of aluminum beam is 0.6×10 ^-7 Torr-2.8×10 ^-7 Torr; The equilibrium vapor pressure of indium beam is 2.0×10 ^-7 Torr-6.0×10 ^-7 Torr; Silicon beam equilibrium vapor pressure is 2.8×10 ^-8 Torr; The equilibrium vapor pressure of the boron beam is 1.2×10 ^-8 Torr-3.0×10 ^-8 Torr; Phosphorus beam equilibrium vapor pressure is 0.8×10 ^-8 Torr-2.0×10 ^-8 Torr; The nitrogen plasma RF source power is 350W. 8 . The production method according to claim 6 , wherein the scandium source is tricyclopentadienyl scandium Cp ₃ Sc or dimethylcyclopentadienyl scandium chloride (MCp) ₂ ScCl. 9. The manufacturing method according to claim 6, characterized in that: the boron source is selected from triethyl boron. 10. The production method according to claim 6, characterized in that: the phosphorus source is selected from tertiary phosphine R-3P.

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