CN115763533A - Groove filling medium leakage-isolating homoepitaxial GaN HEMT device and manufacturing method thereof - Google Patents
Groove filling medium leakage-isolating homoepitaxial GaN HEMT device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a homoepitaxy GaN HEMT device with groove filling medium for isolating electric leakage and a manufacturing method thereof, which mainly solve the problem of electric leakage of a homoepitaxy interface of the conventional device. The GaN-based solar cell comprises a GaN substrate, a GaN buffer layer, a back barrier layer, a channel layer, an AlN insert layer, a barrier layer and an insulated gate medium from bottom to top, wherein ohmic contact regions are respectively arranged on two sides of the AlN insert layer and the barrier layer, source and drain electrodes are arranged on the ohmic contact regions, and a gate electrode is arranged on the insulated gate medium; the GaN buffer layer and the GaN substrate are provided with grooves, the grooves and the back surface of the GaN substrate are filled with high-thermal-conductivity materials and are covered with the high-thermal-conductivity materials to serve as electric leakage isolation layers, through holes from the bottom to the electric leakage isolation layers are arranged below ohmic contact regions of the source electrodes, and metal is deposited in the through holes and on the lower portions of the electric leakage isolation layers to form back electrodes. The invention has no homogeneous epitaxial interface electric leakage, high output current and power density and high heat dissipation efficiency, and can be used for microwave power amplifiers and radio frequency integrated circuit chips.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a homoepitaxy GaN high electron mobility transistor HEMT which can be used for manufacturing a microwave power amplifier and a radio frequency integrated circuit chip.
Background
The third generation wide bandgap semiconductor material GaN has important application in high frequency, high power, high efficiency solid state microwave millimeter wave devices and power amplifiers, and becomes a research hotspot and strategic competitive point in the field of microelectronic devices in recent years. The GaN material has strong spontaneous polarization and piezoelectric polarization effects, and the two-dimensional electron gas with high area density and high mobility in the heterojunction material is the key for realizing high-efficiency switching and high-frequency and high-power application of devices. As a mainstream device structure, a GaN HEMT has already obtained marketable application in the fields of broadband communication and information sensing through structural innovation and process improvement for nearly thirty years.
In order to further improve the working frequency, the output power and the working efficiency of the GaN HEMT device, the device structure design innovation, the new material application and the device process development become the main ways for improving the device performance, wherein the material epitaxy develops from heteroepitaxy to homoepitaxy on a self-supporting gallium nitride substrate. When a GaN HEMT device is subjected to heteroepitaxy on a Si, siC or sapphire substrate, high-density dislocation defects exist in materials, vertical electric leakage and reliability of the device are reduced, and a homoepitaxy interface parasitic electric leakage channel becomes a main factor for limiting breakdown voltage. The structure of a conventional GaN HEMT device is shown in fig. 1, and the structures from bottom to top are respectively: the GaN-based light-emitting diode comprises a substrate, a nucleating layer, a GaN buffer layer, a channel layer, an insertion layer and a barrier layer, wherein a gate electrode is arranged on the barrier layer, and a source electrode and a drain electrode are respectively arranged on ohmic contacts of a source region and a drain region. The device structure has the following disadvantages:
firstly, in heteroepitaxy's GaN buffer layer, the high density dislocation that leads to by the lattice mismatch can get into the device active area along material epitaxy direction, produces the scattering to the carrier transport, forms perpendicular electric leakage channel simultaneously, has reduced device breakdown voltage, makes the device reliability take place the degradation.
Secondly, the hetero-epitaxial GaN buffer layer needs to adopt a nucleation layer structure, the growth process, the material quality and the thickness of the structure directly determine the crystallization quality and the transportation characteristic of GaN epitaxial materials on the structure, the process control difficulty is high, and the repeatability and the consistency are poor.
And thirdly, when the GaN buffer layer is homoepitaxially grown, high-concentration n-type Si impurities exist at the homoepitaxial interface of the self-supporting gallium nitride substrate and the GaN material, the impurities are difficult to completely remove, a parasitic leakage channel is introduced, and the breakdown voltage and the output power density of the homoepitaxial GaN HEMT device are seriously reduced.
And fourthly, when the homoepitaxy GaN buffer layer is used, in order to solve the problem of parasitic electric leakage of a homoepitaxy interface, fe or C impurities are introduced by adopting in-situ growth for compensation, so that impurity diffusion and memory effects can be caused, and the C impurities serving as deep-level acceptors are not suitable for being used in microwave power devices.
Fifthly, the self-supporting gallium nitride single crystal substrate has low heat conductivity, can limit the normal work of homoepitaxy GaN HEMT devices at higher temperature, and can not meet the application occasions of high power and high temperature.
Disclosure of Invention
The invention aims to provide a homoepitaxy GaN HEMT device with groove filling medium for isolating leakage and a manufacturing method thereof aiming at the defects of the prior art, so as to block a parasitic leakage channel of a homoepitaxy interface, realize epitaxial growth of a gallium nitride material with extremely low defect, and improve the heat dissipation efficiency, the output power density and the reliability of the device.
The technical scheme of the invention is realized as follows:
1. the utility model provides a homoepitaxy GaN HEMT device of electric leakage is kept apart to recess filling medium, includes GaN substrate, gaN buffer layer, back barrier layer, channel layer, alN inserted layer, barrier layer and insulated gate medium from bottom to top, and the AlN inserted layer is equipped with ohmic contact respectively with the barrier layer left and right sides, is equipped with source, drain electrode on the ohmic contact respectively, is equipped with gate electrode on the insulated gate medium, its characterized in that:
a groove is etched between the GaN substrate and the GaN buffer layer, and the groove and the back surface of the GaN substrate are filled with high-thermal-conductivity materials and covered with the high-thermal-conductivity materials to serve as electric leakage isolation layers so as to block a homoepitaxial interface parasitic electric leakage channel;
a through hole reaching the electric leakage isolation layer is formed below the ohmic contact area of the source electrode, and back electrodes are arranged in the through hole and on the lower portion of the electric leakage isolation layer, so that parasitic capacitance of the device is reduced, and better high-frequency characteristics are achieved.
Further, the GaN substrate adopts a self-supporting gallium nitride substrate;
further, the thickness of the GaN buffer layer is 300nm-6000nm;
further, the back barrier layer adopts any one of gradient components of AlGaN, alGaN/GaN superlattice and AlGaN/AlN superlattice, and the thickness of the back barrier layer is 50nm-100nm;
further, the channel layer adopts In x Ga 1-x N, wherein x is more than or equal to 0 and less than or equal to 1, and the thickness of the component is 10nm-30nm;
further, the AlN insert layer has a thickness of 1nm to 2nm;
further, the barrier layer is made of any one of AlN, alGaN, inAlN, scAlN, alPN, BAlN, BPN and YAlN, and the thickness of the barrier layer is 3nm-30nm;
furthermore, the thickness of the groove extending into the GaN buffer layer is 100-200nm;
further, the electric leakage isolating layer adopts any one of diamond, c-BN and AlN, and the thickness of the electric leakage isolating layer is 10-20 μm;
furthermore, the insulated gate dielectric layer adopts Al 2 O 3 、HfO 2 Any one of the HfAlO dielectric layer and the HfAlO dielectric layer, and the thickness of the dielectric layer is 3nm-20nm.
2. A manufacturing method of a groove-filled dielectric isolation electric leakage homoepitaxy GaN HEMT device comprises the following steps:
1) On the GaN substrate base chip, utilize the metal organic matter chemical vapor deposition technology or molecular beam epitaxy method to grow the GaN buffer layer with thickness of 300nm-6000nm;
2) Growing a back barrier layer with the thickness of 50nm-100nm on the GaN buffer layer by adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy method;
3) Growing a channel layer with the thickness of 10nm-30nm on the back barrier layer by adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy method;
4) Growing an AlN insert layer with the thickness of 1nm-2nm on the channel layer by adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy method;
5) Adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy method to grow a barrier layer with the thickness of 3nm-30nm on the AlN insert layer;
6) Thinning the thickness of the GaN substrate from the back surface thereof to 50-150 μm by adopting a chemical mechanical polishing method;
7) Selecting a region to be etched on the back of the GaN substrate by adopting a photoetching process, etching the GaN substrate and the GaN buffer layer by adopting a dry etching process, and etching a groove with the depth of 100nm-200nm deep into the GaN buffer layer;
8) Depositing a leakage isolating layer with the thickness of 10-20 microns in the etched groove and the back of the GaN substrate, and carrying out chemical mechanical polishing treatment on the surface of the leakage isolating layer after deposition to flatten the surface of the material;
9) Selecting device source and drain ohmic contact region patterns at two ends of the barrier layer by adopting a photoetching process, and carrying out dry etching treatment on the device source and drain ohmic contact region patterns to the upper part of the channel layer to form ohmic contact region grooves;
10 Adopting metal organic chemical vapor deposition technique or molecular beam epitaxy method to grow Si-doped n-type GaN layer with thickness of 4nm-32nm in the groove of ohmic contact region, wherein the Si doping concentration is (1-5) × 10 20 cm -3 Forming an ohmic contact region;
11 Adopting an electron beam evaporation process to deposit ohmic contact metal Ti/Al/Ni/Au on ohmic contact areas of the source electrode and the drain electrode, and annealing at 830 ℃ in a nitrogen atmosphere to form the source electrode and the drain electrode;
12 Adopting an atomic layer deposition process to deposit an insulated gate dielectric layer with the thickness of 3nm-20nm on the barrier layer;
13 Selecting a gate electrode pattern on the surface of the insulated gate dielectric layer by adopting a photoetching process, and depositing Ni/Au metal combination on the pattern by adopting an electron beam evaporation process to form a gate electrode;
14 Performing back hole etching under the leakage isolation layer by using a back channel process to form a through hole from the leakage isolation layer to an ohmic contact region below the source electrode;
15 Adopting a magnetic sputtering process to fill TiW on the hole wall as an alloy barrier layer, then filling Au in the through hole, continuously plating Au with the thickness of 8-10 mu m on the electric leakage isolation layer through an electroplating process, and forming a back electrode at the bottom of the electric leakage isolation layer to finish the manufacture of the device.
Compared with the prior art, the invention has the following advantages:
1. according to the invention, because the GaN HEMT material homoepitaxy is carried out by adopting the self-supporting GaN substrate, zero-stress epitaxy of the GaN heterojunction material can be realized, the dislocation density in the heteroepitaxy GaN material is effectively reduced, the material crystal quality is improved, the vertical leakage channel is reduced, and the breakdown voltage and the output power of the device are improved.
2. According to the invention, the leakage isolation layer with the groove filled with the medium is adopted, so that a parasitic leakage channel formed by a homoepitaxial interface between the GaN buffer layer and the GaN substrate is effectively blocked, and the breakdown voltage of the GaN HEMT device can be improved.
3. The invention adopts the leakage isolating layer of the groove filling medium to block a parasitic leakage channel formed by the homoepitaxial interface, and does not introduce in-situ Fe or C doping to compensate the parasitic Si impurity of the homoepitaxial interface, so the material growth process is simple, and the memory effect and the microwave radio frequency loss are avoided.
4. The invention leads the source electrode to the back of the substrate through the through hole, thereby reducing the parasitic capacitance of the device, realizing better high-frequency characteristic, and simultaneously bonding the source electrode to other substrates as a metal heat sink material to realize the transfer of the GaN HEMT device.
5. According to the invention, as the groove is filled with the high-thermal-conductivity leakage isolation layer material and the back electrode metal on the back of the leakage isolation layer is combined, the heat generated by the active region of the device can be efficiently dissipated, the high-temperature characteristic of the device is better, and the reliability and the upper limit of the working temperature of the device are improved.
Drawings
FIG. 1 is a diagram of a conventional GaN HEMT device structure;
FIG. 2 is a diagram of a homoepitaxial GaN HEMT device structure with groove-filled dielectric isolation leakage according to the present invention;
FIG. 3 is a schematic view of the process flow of the present invention for manufacturing a groove-filled dielectric isolation leaky homoepitaxial GaN HEMT device.
Detailed Description
Referring to fig. 2, the homoepitaxial GaN HEMT device structure with the groove filled with the dielectric isolation leakage comprises a GaN substrate 1, a GaN buffer layer 2, a back barrier layer 3, a channel layer 4, an AlN insertion layer 5, a barrier layer 6, a groove 7, a leakage isolation layer 8, an insulated gate dielectric 9 and a back electrode 10, wherein ohmic contact regions are respectively arranged on the left side and the right side of the AlN insertion layer 5 and the barrier layer 6, source electrodes and drain electrodes are respectively arranged on the ohmic contact regions, and a gate electrode is arranged on the insulated gate dielectric. Wherein:
the GaN substrate 1 adopts a self-supporting gallium nitride substrate;
the GaN buffer layer 2 is positioned above the GaN substrate 1, and the thickness of the GaN buffer layer is 300nm-6000nm;
a groove 7 is arranged between the GaN substrate 1 and the GaN buffer layer 2, and the depth of the groove 7 penetrating into the GaN buffer layer 2 is 100nm-200nm;
the groove 7 and the back surface of the GaN substrate 1 are filled and covered with a leakage isolation layer 8 to block a homoepitaxial interface parasitic leakage channel;
the electric leakage isolating layer 8 is made of any one of diamond, c-BN and AlN, and the thickness of the electric leakage isolating layer is 10-20 mu m;
the back barrier layer 3 is positioned above the GaN buffer layer 2, adopts any one of gradient components AlGaN, alGaN/GaN superlattice and AlGaN/AlN superlattice, and has the thickness of 50nm-100nm;
the channel layer 4 is arranged above the back barrier layer 3 and adopts In x Ga 1-x N, x is more than or equal to 0 and less than or equal to 1, and the thickness is 10nm-30nm;
the AlN insert layer 5 is positioned above the channel layer 4, and the thickness of the AlN insert layer is 1nm-2nm;
the barrier layer 6 is positioned above the AlN insert layer 5, and is made of any one of AlN, alGaN, inAlN, scAlN, alPN, BAlN, BPN and YAlN, and the thickness of the barrier layer is 3nm-30nm;
the insulated gate dielectric layer 9 is positioned above the barrier layer 6 and is made of Al 2 O 3 、HfO 2 Any one of the HfAlO dielectric layer and the HfAlO dielectric layer is 3nm-20nm in thickness;
the source electrode is etched from the back of the electric leakage isolation layer to the ohmic contact region through a back channel process, and metal is filled in the through hole and plated on the electric leakage isolation layer 8 to form a back electrode 10.
Referring to fig. 3, the method for manufacturing a homoepitaxial GaN HEMT device with groove-filled dielectric isolation leakage according to the present invention provides the following three embodiments.
In the first embodiment, a self-supporting GaN substrate is used for manufacturing, the thickness of a diamond leakage isolation layer and a gradient component AlGaN back barrier layer is 100nm, the thickness of a GaN channel is 30nm, and Al is used 0.25 Ga 0.75 And the thickness of the N barrier layer is 30nm.
Step one, a GaN buffer layer is deposited, as shown in fig. 3 (a).
Depositing a GaN buffer layer with the thickness of 6000nm on a GaN substrate by using a metal organic chemical vapor deposition technology, wherein the deposition process conditions are as follows: the temperature was 1250 deg.C, the pressure was 50Torr, the flow of ammonia gas was 2000sccm, the flow of gallium source was 150sccm, and the flow of hydrogen was 3000sccm.
And step two, depositing a gradient component AlGaN back barrier layer as shown in figure 3 (b).
Depositing a gradient component AlGaN back barrier layer with the thickness of 100nm on the GaN buffer layer by using a metal organic chemical vapor deposition technology, wherein the deposition process conditions are as follows: 1250 ℃, the pressure is 50Torr, the flow of ammonia gas is 2000sccm, the flow of gallium source is 150sccm, the flow of aluminum source is 20sccm, and the flow of hydrogen is 3000sccm.
Step three, depositing a GaN channel layer, as shown in FIG. 3 (c).
Depositing a 30nm thick GaN channel layer on the gradient component AlGaN back barrier layer by using a metal organic chemical vapor deposition technology, wherein the deposition process conditions are as follows: the temperature was 1250 deg.C, the pressure was 50Torr, the gallium source flow was 150sccm, the ammonia gas flow was 2000sccm, and the hydrogen gas flow was 3000sccm.
Step four, an AlN insertion layer is deposited, as shown in fig. 3 (d).
Depositing an AlN insert layer with the thickness of 1nm on the GaN channel layer by using a metal organic chemical vapor deposition technology, wherein the deposition process conditions are as follows: the temperature was 1250 deg.C, the pressure was 50Torr, the aluminum source flow was 20sccm, the ammonia gas flow was 2000sccm, and the hydrogen gas flow was 3000sccm.
Step five, depositing an AlGaN barrier layer, as shown in FIG. 3 (e).
Depositing 30nm thick Al on the AlN insert layer using a metal-organic chemical vapor deposition technique 0.25 Ga 0.75 The process conditions of the deposition of the N barrier layer are as follows: the temperature was 1250 deg.C, the pressure was 50Torr, the flow of ammonia gas was 2000sccm, the flow of gallium source was 60sccm, the flow of aluminum source was 20sccm, and the flow of hydrogen was 3000sccm.
Step six, thinning the GaN substrate, as shown in FIG. 3 (f).
The GaN substrate was thinned to 50 μm using a chemical mechanical polishing method. Firstly, coarse grinding and high-speed thinning are carried out, and then fine grinding is carried out to improve the flatness of the back surface of the GaN substrate.
Step seven, etching the GaN substrate and the GaN buffer layer to form grooves, as shown in figure 3 (g).
And selecting an etching area on the back surface of the GaN substrate by using a photoetching process, etching the GaN substrate and the GaN buffer layer by using a dry etching process, and etching a groove with the depth of 100nm penetrating into the GaN buffer layer.
And step eight, depositing a diamond leakage isolation layer as shown in figure 3 (h).
Depositing a diamond leakage isolation layer with the thickness of 10 mu m in the groove and the back of the GaN substrate by adopting a microwave plasma chemical vapor deposition technology, and performing chemical mechanical polishing treatment on the surface of the diamond leakage isolation layer after deposition, wherein the deposition process conditions are as follows: microwave power 1400W, gas pressure 21kPa, plasma power density 700W/cm 3 At a temperature of 850 ℃ CH 4 Volume fraction1.0％，H 2 The flow rate was 200ml/min.
And step nine, performing dry etching to form a source-drain ohmic contact region groove, as shown in fig. 3 (i).
By photolithography on Al 0.25 Ga 0.75 Selecting patterns of ohmic contact regions of a source electrode and a drain electrode on two sides of the N barrier layer, processing two ends of the barrier layer to the upper part of the channel layer by using an RIE (reactive ion etching) dry etching technology to form a groove of the ohmic contact regions of the source electrode and the drain electrode, wherein the etching process conditions are as follows: cl 2 The flow was 15sccm, the chamber pressure was 12mTorr, and the electrode power was 180W.
Step ten, making an ohmic contact region, as shown in fig. 3 (j).
Depositing a 31nm thick Si-doped n-type GaN layer in the groove of the ohmic contact region by using Metal Organic Chemical Vapor Deposition (MOCVD) technology, wherein the Si doping concentration is 1 × 10 20 cm -3 Forming left and right ohmic contact regions under the following deposition conditions: the temperature was 1250 deg.C, the pressure was 50Torr, the flow of ammonia gas was 2000sccm, the flow of gallium source was 150sccm, the flow of hydrogen was 3000sccm, and the flow of silane was 500sccm.
Step eleven, a source electrode and a drain electrode are fabricated as in fig. 3 (k).
Respectively depositing Ti/Al/Ni/Au metal combinations with the thickness of 0.02 mu m/0.05 mu m/0.04 mu m on ohmic contact areas of a source electrode and a drain electrode by adopting an electron beam evaporation process, and rapidly performing thermal annealing for 30s in a nitrogen atmosphere at the temperature of 830 ℃ to form the source electrode and the drain electrode, wherein the process conditions of depositing the metals are as follows: vacuum degree less than 1.2 × 10 -3 Pa, power 400W, evaporation rate
Step twelve, depositing Al 2 O 3 And (4) insulating gate dielectric layers, as shown in figure 3 (l).
Using atomic layer deposition process on Al 0.25 Ga 0.75 Al with the thickness of 10nm is grown on the N barrier layer 2 O 3 And an insulated gate dielectric layer.
Step thirteen, a gate electrode is fabricated, as shown in fig. 3 (m).
Using lightEtching process on Al 2 O 3 Making a mask on the insulated gate dielectric layer, and evaporating Al by using electron beam 2 O 3 Depositing metal on a selected area of the dielectric layer of the insulated gate to manufacture a gate, wherein the deposited metal is a Ni/Au metal combination, the thickness of the metal is 0.02 mu m/0.3 mu m, and the deposition process conditions are as follows: vacuum degree less than 1.4X 10 -3 Pa, power range of 400-800W, evaporation rate of
Fourteen, etching by using a back track process to form a through hole, as shown in fig. 3 (n).
And forming a through hole from the leakage isolation layer to the ohmic contact region below the source electrode by adopting a back channel process and using an inductively coupled plasma etching technology.
Step fifteen, filling metal into the through hole and electroplating metal on the leakage isolation layer, as shown in fig. 3 (o).
And (3) filling TiW serving as an alloy barrier layer into the hole wall by adopting a magnetic sputtering process, filling Au into the through hole, continuously electroplating the Au with the thickness of 8 mu m on the electric leakage isolation layer by adopting an electroplating process, and forming a back electrode at the bottom of the electric leakage isolation layer to finish the manufacture of the device.
In the second embodiment, a free-standing GaN substrate is used, the thickness of the c-BN leakage isolation layer and the AlGaN/GaN superlattice back barrier layer is 80nm, in 0.1 Ga 0.9 The thickness of the N channel layer is 20nm, sc 0.18 Al 0.82 And the thickness of the N barrier layer is 10 nm.
A metal organic chemical vapor deposition technology is used for depositing a GaN buffer layer with the thickness of 3000nm on a GaN substrate under the process conditions that the temperature is 1150 ℃, the pressure is 60Torr, the flow of ammonia gas is 2000sccm, the flow of a gallium source is 90sccm and the flow of hydrogen is 3000sccm.
Using MOCVD at 1150 deg.CGrowing Al with the thickness of 80nm and the period of 20 on the GaN substrate under the process conditions that the pressure is 60Torr, the flow of ammonia gas is 2000sccm, the flow of gallium source is 90sccm, the flow of aluminum source is 25sccm and the flow of hydrogen is 3000sccm 0.2 Ga 0.8 And the N/GaN superlattice back barrier layer.
Depositing In with the thickness of 20nm on the AlGaN/GaN superlattice back barrier layer by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 700 ℃, the pressure is 300Torr, the flow of ammonia is 2000sccm, the flow of an indium source is 120sccm, the flow of a gallium source is 60sccm and the flow of nitrogen is 3000sccm 0.1 Ga 0.9 And an N channel layer.
Using a metal organic chemical vapor deposition technology, under the process conditions of 700 ℃ of temperature, 300Torr of pressure, 25sccm of aluminum source flow, 2000sccm of ammonia gas flow and 3000sccm of nitrogen gas flow, in 0.1 Ga 0.9 An AlN insert layer was deposited on the N channel layer to a thickness of 1.5 nm.
Using a metallorganic chemical vapor deposition technology, and under the process conditions that the temperature is 1000 ℃, the pressure is 300Torr, the flow of an aluminum source is 25sccm, the flow of a scandium source is 10sccm, the flow of ammonia gas is 2000sccm, and the flow of nitrogen gas is 3000sccm, depositing Sc with the thickness of 10nm on the AlN insert layer 0.18 Al 0.82 An N barrier layer.
And (3) using a chemical mechanical polishing method, firstly carrying out coarse grinding and high-speed thinning, then carrying out fine grinding to improve the flatness of the back surface of the GaN substrate, and thinning the thickness of the GaN substrate to 100 mu m.
And selecting an etching area on the back surface of the GaN substrate by using a photoetching process, etching the GaN substrate and the GaN buffer layer by using a dry etching process, and etching a groove with the depth of 150nm deep into the GaN buffer layer.
And 8, depositing a leakage isolating layer on the back surface of the GaN substrate, as shown in a figure 3 (h).
By adopting a metal organic chemical vapor phase technology, under the conditions that the temperature is 1300 ℃, the pressure is 400Torr, the flow of a boron source is 20 mu mol/min, the flow of ammonia gas is 3000sccm, and the flow of hydrogen gas is 2000sccm, cubic boron nitride (c-BN) with the thickness of 15 mu m is deposited in the groove and the back surface of the GaN substrate, and after the deposition, the surface of the c-BN leakage isolation layer is subjected to chemical mechanical polishing treatment.
And 9, performing dry etching to form a source-drain ohmic contact region groove, as shown in a figure 3 (i).
Using a photoetching process in Sc 0.18 Al 0.82 Selecting ohmic contact region pattern of source electrode and drain electrode on N barrier layer surface, and etching in Cl by RIE dry method 2 And processing two ends of the barrier layer to the upper part of the channel layer under the process conditions that the flow is 20sccm, the pressure of the reaction chamber is 15mTorr and the electrode power is 200W to form a groove of the source-drain ohmic contact region.
And step 10, manufacturing a source-drain ohmic contact region, as shown in fig. 3 (j).
Using metal organic chemical vapor deposition technology, under the process conditions that the temperature is 1150 ℃, the pressure is 60Torr, the flow of ammonia is 2000sccm, the flow of gallium source is 90sccm, the flow of hydrogen is 3000sccm and the flow of silane is 800sccm, depositing a Si-doped n-type GaN layer with the thickness of 11.5nm to the groove region of the ohmic contact region, wherein the concentration of Si ions is 3 multiplied by 10 20 cm -3 And forming an ohmic contact region.
Step 11, making source and drain electrodes, as shown in fig. 3 (k).
Adopting electron beam evaporation process, and making vacuum degree be less than 1.2X 10 -3 Pa, power 400W, evaporation rate
Respectively depositing Ti/A with the thickness of 0.02/0.05/0.04 μm on the ohmic contact regions of the source electrode and the drain electrode under the process conditions of (1)l/Ni/Au metal combinations and rapid thermal annealing at 830 ℃ for 30s in a nitrogen atmosphere to form source and drain electrodes.
Step 12, using an atomic layer deposition process, in Sc 0.18 Al 0.82 Depositing HfO with a thickness of 20nm on the N-barrier layer 2 And (4) insulating gate dielectric layers, as shown in figure 3 (l).
And step 13, manufacturing a gate electrode on the insulated gate dielectric, as shown in fig. 3 (m).
Using a photolithography process on HfO 2 Selecting a grid electrode pattern on the insulated gate dielectric layer, and using an electron beam evaporation technology to ensure that the vacuum degree is less than 1.2 multiplied by 10 -3 Pa, power 600W, evaporation rate
Under the process conditions of (1), under HfO 2 And depositing metal on the insulated gate dielectric layer to manufacture a gate, wherein the deposited metal is a Ni/Au metal combination, and the thickness of the metal is 0.04 mu m/0.5 mu m.
Step 14, etching is performed by using a back-track process to form a through hole, as shown in fig. 3 (n).
And etching the through hole under the electric leakage isolation layer by adopting a back channel process, and forming the through hole from the electric leakage isolation layer to the ohmic contact region below the source electrode by using an inductive coupling plasma etching technology.
Step 15, filling metal into the via hole and electroplating metal on the leakage isolation layer, as shown in fig. 3 (o).
And filling TiW serving as an alloy barrier layer on the hole wall by adopting a magnetic sputtering process, filling Au into the through hole, continuously electroplating Au with the thickness of 9 mu m on the electric leakage isolation layer by adopting an electroplating process, and forming a back electrode at the bottom of the electric leakage isolation layer to finish the manufacture of the device.
In the third embodiment, a GaN HEMT device was fabricated using a self-supporting GaN substrate with an AlN leakage isolation layer, an AlGaN/AlN back barrier layer 50nm thick, an InN channel layer 10nm thick, and an AlN barrier layer 3nm thick.
Step A, selecting a self-supporting GaN substrate, setting the temperature to be 750 ℃, the nitrogen flow to be 0.6sccm, and the gallium beam current balance vapor pressure to be 3.5 multiplied by 10 -7 Torr, nitrogen plasma RF source power of 350WThe process conditions, using molecular beam epitaxy, deposited a GaN buffer layer with a thickness of 300nm on the GaN substrate, as shown in fig. 3 (a).
Step B, setting the temperature to 750 ℃, the nitrogen flow to 0.6sccm, and the gallium beam current balance vapor pressure to 3.5 multiplied by 10 - 7 Torr, the equilibrium vapor pressure of aluminum beam is 1.2X 10 -7 Torr, the process condition of nitrogen plasma radio frequency source power of 350W, and a molecular beam epitaxy method is adopted to deposit an AlGaN/AlN superlattice back barrier layer with the thickness of 50nm on the GaN buffer layer, as shown in figure 3 (b).
Step C, setting the temperature to be 550 ℃, the nitrogen flow to be 0.6sccm, and the equilibrium vapor pressure of the indium beam current to be 2.0 multiplied by 10 - 7 Torr, the process condition that the power of a nitrogen plasma radio frequency source is 350W, and an InN channel layer with the thickness of 10nm is deposited on the AlGaN/AlN superlattice back barrier layer by adopting a molecular beam epitaxy method, as shown in figure 3 (c).
Step D, setting the temperature to be 550 ℃, the nitrogen flow to be 0.6sccm, and the equilibrium vapor pressure of the aluminum beam current to be 1.2 multiplied by 10 - 7 Torr, the process condition of nitrogen plasma radio frequency source power of 350W, and a molecular beam epitaxy method is adopted to deposit an AlN insert layer with the thickness of 2nm on the InN channel layer, as shown in figure 3 (d).
Step E, setting the temperature to be 720 ℃, the nitrogen flow to be 0.6sccm, and the balance vapor pressure of the aluminum beam to be 1.2 multiplied by 10 - 7 Torr, the process condition of nitrogen plasma radio frequency source power of 350W, and a molecular beam epitaxy method is adopted to deposit an AlN barrier layer with the thickness of 3nm on the AlN insertion layer, as shown in figure 3 (e).
And step F, using a chemical mechanical polishing method, firstly carrying out coarse grinding and high-speed thinning, then carrying out fine grinding to improve the flatness of the back surface of the GaN substrate, and thinning the thickness of the GaN substrate to 150 mu m, as shown in a figure 3 (F).
And G, selecting an etching area on the back surface of the GaN substrate by using a photoetching process, etching the GaN substrate and the GaN buffer layer from the back surface by using a dry etching process, and etching a groove with the thickness of 200nm deep into the GaN buffer layer, as shown in a figure 3 (G).
Step H, setting the temperature to be 400 ℃ and the vacuum degree to be less than 10 -4 Pa, the pressure is 40Torr, the direct current sputtering power is 5kW, the aluminum source flow is 110sccm, and the argon flowThe AlN leakage isolating layer with the thickness of 20 microns is deposited in the groove and the back surface of the GaN substrate by adopting the physical vapor deposition technology under the process conditions that the flow rate of ammonia gas is 1000sccm and the quantity is 45sccm, and the surface of the AlN leakage isolating layer is subjected to chemical mechanical polishing treatment after deposition, as shown in figure 3 (h).
Step I, adopting a photoetching process, selecting ohmic contact areas of a source electrode and a drain electrode on the surface of the AlN barrier layer, and setting Cl 2 And (5) processing the two ends of the barrier layer to the upper part of the channel layer by using a RIE (reactive ion etching) dry etching technology under the process conditions that the flow is 10sccm, the pressure of the reaction chamber is 10mTorr and the power of the electrode is 180W to form a groove of a source-drain ohmic contact region, as shown in figure 3 (i).
Step J, setting the temperature to 750 ℃, the nitrogen flow to 0.6sccm, and the gallium beam equilibrium vapor pressure to 3.5 multiplied by 10 - 7 Torr, equilibrium vapor pressure of silicon beam current is 2.8X 10 -8 Torr, nitrogen plasma radio frequency source power is 350W, molecular beam epitaxy technique is used, si doped n type GaN layer with thickness of 5nm is deposited on the groove area of the ohmic contact area, the concentration of Si ions is 5 multiplied by 10 20 cm -3 And ohmic contact regions are formed as shown in fig. 3 (j).
Step K, setting the vacuum degree to be less than 1.2 multiplied by 10 -3 Pa, power 500W, evaporation rate
Respectively depositing a Ti/Al/Ni/Au metal combination with a thickness of 0.02/0.2/0.05 μm on the ohmic contact regions of the source electrode and the drain electrode by an electron beam evaporation process, and rapidly thermally annealing at 830 ℃ for 30s in a nitrogen atmosphere to form the source electrode and the drain electrode, as shown in FIG. 3 (k).
And step L, depositing a HfAlO insulated gate dielectric layer with the thickness of 3nm on the AlN barrier layer by using an atomic layer deposition process, as shown in a figure 3 (L).
Step M, selecting a grid pattern on the HfAlO insulated gate dielectric layer by adopting a photoetching process, and setting the vacuum degree to be less than 1.2 multiplied by 10 -3 Pa, power of 500W, evaporation rate of
Process conditions ofAnd depositing a Ni/Au metal combination with the thickness of 0.03 mu m/0.4 mu m on the HfAlO insulated gate dielectric layer by using an electron beam evaporation technology to manufacture a gate, as shown in figure 3 (m).
And step N, etching the through hole under the electric leakage isolation layer by adopting a back channel process, and forming the through hole from the electric leakage isolation layer to the ohmic contact region below the source electrode by using an inductive coupling plasma etching technology, as shown in figure 3 (N).
And step O, adopting a magnetic sputtering process to fill TiW on the hole wall as an alloy barrier layer, then filling Au in the through hole, continuously electroplating Au with the thickness of 10 mu m on the electric leakage isolation layer through an electroplating process, and forming a back electrode at the bottom of the electric leakage isolation layer to finish the manufacture of the device, as shown in figure 3 (O).
While the foregoing description is directed to three specific examples of the present invention and is not intended to limit the invention, it will be apparent to those skilled in the art that various changes and modifications in form and detail may be made therein without departing from the spirit and scope of the invention, and that the barrier layer may be made in any form and detail other than AlN, alGaN, scAlN, inAlN, any other barrier layer such as InAlN, alPN, BAlN, BPN or YAlN, and such changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. The utility model provides a homoepitaxy GaN HEMT device of electric leakage is kept apart to recess filling medium, includes GaN substrate (1), gaN buffer layer (2), back of the body barrier layer (3), channel layer (4), alN inserted layer (5), barrier layer (6) and insulated gate medium (9) from bottom to top, alN inserted layer (5) and barrier layer (6) left and right sides are equipped with the ohm contact zone respectively, are equipped with source, drain electrode on the ohm contact zone respectively, are equipped with the gate electrode on insulated gate medium (9), its characterized in that:
a groove (7) is etched between the GaN substrate (1) and the GaN buffer layer (2), and the groove and the back surface of the GaN substrate (1) are filled with high-thermal-conductivity materials and covered with the high-thermal-conductivity materials to serve as electric leakage isolation layers (8) so as to block a homoepitaxial interface parasitic electric leakage channel;
a through hole reaching the electric leakage isolation layer (8) is arranged below the ohmic contact area of the source electrode, and back electrodes (10) are arranged in the through hole and on the lower portion of the electric leakage isolation layer, so that parasitic capacitance of the device is reduced, and better high-frequency characteristics are realized.
2. The transistor of claim 1, wherein:
the GaN substrate (1) adopts a self-supporting gallium nitride substrate;
the GaN buffer layer (2) is 300nm-6000nm thick;
the AlN insert layer (5) has a thickness of 1nm to 2nm.
3. The transistor of claim 1, wherein:
the back barrier layer (3) adopts any one of AlGaN, alGaN/GaN superlattice and AlGaN/AlN superlattice with gradually changed components, and the thickness is 50nm-100nm;
the channel layer (4) is formed of In x Ga 1-x N, wherein x is more than or equal to 0 and less than or equal to 1, and the thickness of the component is 10nm-30nm;
the barrier layer (6) is made of any one of AlN, alGaN, inAlN, scAlN, alPN, BAlN and BPN YAlN, and has a thickness of 3-30 nm.
4. The transistor of claim 1, wherein:
the thickness of the groove (7) penetrating into the GaN buffer layer (2) is 100-200nm;
the electric leakage isolating layer (8) is made of any one of diamond, c-BN and AlN, and the thickness of the electric leakage isolating layer is 10-20 micrometers;
the insulated gate dielectric layer (9) adopts Al 2 O 3 、HfO 2 And the thickness of any one of the HfAlO dielectric layer is 3nm-20nm.
5. A manufacturing method of a groove-filled dielectric isolation leakage homoepitaxy GaN HEMT device is characterized by comprising the following steps:
1) On a GaN substrate (1), a GaN buffer layer (2) with the thickness of 300nm-6000nm is grown by utilizing the metal organic chemical vapor deposition technology or the molecular beam epitaxy method;
2) Growing a back barrier layer (3) with the thickness of 50nm-100nm on the GaN buffer layer (2) by adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy method;
3) Growing a channel layer (4) with the thickness of 10nm-30nm on the back barrier layer (3) by adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy method;
4) An AlN insert layer (5) with the thickness of 1nm-2nm is grown on the channel layer (4) by adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy method;
5) Adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy method to grow a barrier layer (6) with the thickness of 3nm-30nm on the AlN insert layer (5);
6) Thinning the thickness of the GaN substrate (1) from the back surface thereof to 50-150 μm by adopting a chemical mechanical polishing method;
7) Selecting a region to be etched on the back of the GaN substrate (1) by adopting a photoetching process, etching the GaN substrate (1) and the buffer layer (2) by adopting a dry etching process, and etching a groove (7) with the depth of 100nm-200nm deep into the GaN buffer layer (2);
8) Depositing a leakage isolating layer (8) with the thickness of 10-20 mu m in the etched groove (7) and the back of the GaN substrate (1), and carrying out chemical mechanical polishing treatment on the surface of the leakage isolating layer (8) after deposition to level the surface of the material;
9) Selecting device source and drain ohmic contact region patterns at two ends of the barrier layer by adopting a photoetching process, and carrying out dry etching treatment on the device source and drain ohmic contact region patterns to the upper part of the channel layer to form ohmic contact region grooves;
10 Adopting metal organic chemical vapor deposition technique or molecular beam epitaxy method to grow Si-doped n-type GaN layer with thickness of 4nm-32nm in the groove of ohmic contact region, wherein the Si doping concentration is (1-5) × 10 20 cm -3 Forming an ohmic contact region;
11 Adopting an electron beam evaporation process to deposit ohmic contact metal Ti/Al/Ni/Au on ohmic contact areas of the source electrode and the drain electrode, and annealing at 830 ℃ in a nitrogen atmosphere to form the source electrode and the drain electrode;
12 Adopting an atomic layer deposition process to deposit an insulated gate dielectric layer (9) with the thickness of 3nm-20nm on the barrier layer;
13 Selecting a gate electrode pattern on the surface of the insulated gate dielectric layer (9) by adopting a photoetching process, and depositing a Ni/Au metal combination on the pattern by adopting an electron beam evaporation process to form a gate electrode;
14 Carrying out back hole etching under the leakage isolation layer (8) by adopting a back channel process to form a through hole from the leakage isolation layer (8) to an ohmic contact region below the source electrode;
15 TiW is filled into the hole wall by adopting a magnetic sputtering process to serve as an alloy barrier layer, au is filled into the through hole, au with the thickness of 8-10 mu m is continuously plated on the electric leakage isolation layer (8) by an electroplating process, and a back electrode (10) is formed at the bottom of the electric leakage isolation layer (8) to finish the manufacture of the device.
6. The method according to claim 5, wherein the metal organic chemical vapor deposition in steps 1) to 5) comprises the following process conditions:
the temperature is 700-1250 ℃;
the pressure is 50Torr-300Torr;
the flow rate of ammonia gas is 2000sccm;
the hydrogen flow rate was 3000sccm;
the nitrogen flow is 3000sccm;
the gallium source flow is 60sccm-150sccm;
the flow rate of the aluminum source is 2sccm-30sccm;
the indium source flow is 30sccm-120sccm;
the flow of the scandium source is 10sccm to 20sccm;
the flow rate of the yttrium source is 4sccm-20sccm;
the flow rate of the boron source is 10-30 mu mol/min;
the flow rate of the phosphorus source is 20-50 mu mol/min;
the silane flow rate is 500sccm to 1000sccm.
7. The method according to claim 5, wherein the molecular beam epitaxy method in steps 1) to 5) comprises the following process conditions:
the temperature is 550-750 ℃;
the nitrogen flow is 0.6sccm-2.8sccm;
the equilibrium vapor pressure of scandium beam is 1.2X 10 -8 Torr-1.8×10 -8 Torr；
The balance vapor pressure of yttrium beam is 1.0 x 10 -8 Torr-1.5×10 -8 Torr；
The balance vapor pressure of gallium beam is 3.5 x 10 -7 Torr-8.5×10 -7 Torr；
The equilibrium vapor pressure of the aluminum beam is 0.6 multiplied by 10 -7 Torr-2.8×10 -7 Torr；
The equilibrium vapor pressure of the indium beam is 2.0 multiplied by 10 -7 Torr-6.0×10 -7 Torr；
The equilibrium vapor pressure of the silicon beam is 2.8 multiplied by 10 -8 Torr；
The equilibrium vapor pressure of boron beam is 1.2 x 10 -8 Torr-3.0×10 -8 Torr；
The equilibrium vapor pressure of the phosphor beam is 0.8 multiplied by 10 -8 Torr-2.0×10 -8 Torr；
The nitrogen plasma radio frequency source power is 350W.
8. The method of manufacturing of claim 6, wherein: the scandium source is tricyclopentadienyl scandium Cp 3 Sc or dimethylcyclopentadienyl scandium chloride (MCP) 2 ScCl。
9. The method of manufacturing of claim 6, wherein: the boron source is selected from triethylboron.
10. The method of manufacturing of claim 6, wherein: the phosphorus source is selected from tertiary phosphine R-3P.
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| CN116581210B (en) * | 2023-07-10 | 2023-09-19 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
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