CN113314598A - Diamond-based nitrogen polar surface gallium nitride high-electron-mobility transistor and manufacturing method thereof - Google Patents
Diamond-based nitrogen polar surface gallium nitride high-electron-mobility transistor and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention discloses a diamond-based nitrogen polar surface gallium nitride high-electron-mobility transistor and a manufacturing method thereof, and mainly solves the problems of low epitaxial quality, poor heat dissipation capability under the high-pressure high-power working condition, current collapse and reliability degradation of the existing nitrogen polar surface gallium nitride device material. The diamond-based thin film transistor comprises a diamond substrate (1), a transition layer (2), a supporting layer (3), a barrier layer (4), an insertion layer (5), a channel layer (6) and an insulated gate dielectric layer (7) from bottom to top, wherein ohmic contact regions are arranged on two sides of the channel layer (6), a source electrode and a drain electrode are respectively arranged on the ohmic contact regions on the two sides, and a gate electrode is arranged on the insulated gate dielectric layer (7). The device material of the invention has high epitaxial quality, can improve the self-heating effect and the current collapse phenomenon, has high output power and working reliability, simple manufacturing process and high performance consistency, and can be used for high-frequency microwave power amplifiers and monolithic microwave millimeter wave integrated circuits.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a gallium nitride high electron mobility transistor which can be used for manufacturing a microwave power amplifier and a monolithic microwave millimeter wave integrated circuit.
Background
With the continuous development of material epitaxy technology, device structure design and preparation process thereof, the performance of gallium nitride high electron mobility transistors is continuously improved, and the gallium nitride high electron mobility transistors become the first choice for preparing high-frequency high-power solid-state microwave power amplifiers. At present, gallium nitride electronic devices are mainly manufactured based on gallium polar plane heterostructure materials, because epitaxial growth technology of gallium polar plane materials is mature, high crystallization quality and low background carrier concentration are easy to realize. However, the nitrogen polar plane gallium nitride heterostructure material has many natural advantages in improving the working frequency and output power of the device. The barrier layer in the nitrogen polar face gallium nitride heterojunction forms a natural back barrier below the channel layer, the two-dimensional electron gas confinement property can be improved, and the thickness of the barrier layer is not limited by an equal proportion reduction rule. Meanwhile, the narrow-bandgap gallium nitride channel layer is positioned on the top of the epitaxial material, so that low ohmic contact resistance is easy to realize.
However, there are two main problems in the epitaxial growth of nitrogen polar plane gallium nitride device material and the improvement of device performance. Firstly, polarity inversion is easy to occur in the epitaxial growth process of the nitrogen polar surface gallium nitride material, the polarity control difficulty is high, the background carrier concentration of the epitaxial nitrogen polar surface gallium nitride material is high, and a body leakage channel is easy to form to reduce the breakdown voltage and the output power of the device. Secondly, under the working state of the nitrogen polar surface gallium nitride device with high bias voltage and high power density, the junction temperature of the device is rapidly increased due to the heat accumulation effect of the active region of the device, and the reliability and the stability of the device are rapidly deteriorated. The traditional nitrogen polar surface gallium nitride device material is epitaxially grown on a low-thermal-conductivity substrate, the heat dissipation capacity is limited, the heat diffusion to the surrounding environment is limited, and the current collapse effect is easily generated. Therefore, in order to further improve the performance of the nitrogen polar surface gallium nitride device, a substrate with higher thermal conductivity needs to be adopted, the problem of heat accumulation of an active region of the device is solved, the heat transfer capacity near the active region is improved, the self-heating effect of the device is improved, the attenuation of the carrier transport characteristic is inhibited, and the reliability and the stability of the device are improved. Meanwhile, innovations need to be made on the gallium nitride material epitaxial technology of the nitrogen polar surface, so that the background carrier concentration is effectively reduced, and the quality of epitaxial materials is improved.
The structure of a conventional nitrogen polar plane gallium nitride high electron mobility transistor is shown in figure 1, and comprises a substrate, a nucleating layer, a buffer layer, a barrier layer, an insertion layer and a channel layer from bottom to top, wherein the substrate is mostly a low-thermal conductivity substrate such as silicon, sapphire, silicon carbide and the like, and the channel layer is provided with a gate electrode, a source electrode and a drain electrode. This device has the following disadvantages:
firstly, the material polarity control difficulty is high when the gallium nitride material with the nitrogen polar surface is extended, polarity inversion is easy to occur, and the gallium nitride material with the gallium polar surface appears;
secondly, the background carrier concentration of the grown nitrogen polar surface gallium nitride material is high, iron doping is needed to compensate the background carrier, and the difficulty in material epitaxy process control is increased;
thirdly, the heat conductivity of the substrate is low, the heat of the active region of the nitrogen polar surface gallium nitride device cannot be dissipated immediately, the current collapse phenomenon of the device is caused by the heat accumulation effect, and the reliability and the stability of the device are deteriorated;
fourthly, when the nitrogen polar surface gallium nitride device is transferred to the high-thermal conductivity diamond substrate, the device peeling and transferring process is complex, the etching process is difficult to control accurately, the peeling interface is rough and uneven, the device peeling integrity is low, and the performance of the device after peeling is degraded;
fifthly, the problems of large lattice mismatch, large crystal phase mismatch, large heat mismatch and the like exist between the substrate diamond with high heat conductivity and the nitrogen polar surface gallium nitride material, and the direct heteroepitaxial growth of the nitrogen polar surface gallium nitride material on the substrate diamond is difficult to realize high crystallization quality.
Disclosure of Invention
The invention aims to provide a diamond-based nitrogen polar surface gallium nitride high-electron-mobility transistor and a manufacturing method thereof aiming at the defects of the prior art, so that the epitaxial quality of materials is improved, the background carrier concentration of the materials and the difficulty of the device peeling and transferring process are reduced, the self-heating effect and the current collapse effect of the device are improved, and the reliability and the working stability of the device are improved.
The technical scheme of the invention is realized as follows:
1. a diamond-based nitrogen polar surface gallium nitride high electron mobility transistor comprises a diamond substrate, a barrier layer, an insertion layer and a channel layer from bottom to top, and is characterized in that:
a transition layer and a supporting layer are arranged between the diamond substrate and the barrier layer and are used for depositing the diamond substrate and supporting the active region of the device;
the upper part of the channel layer is sequentially provided with an insulated gate dielectric layer and a gate electrode, the two sides of the channel layer are ohmic contact regions, and a source electrode and a drain electrode are respectively arranged on the ohmic contact regions.
Further, it is characterized in that: the transition layer adopts SiN, and the thickness of the transition layer is 50nm-150 nm; the supporting layer is made of GaN, and the thickness of the supporting layer is 4-10 mu m; the insulated gate dielectric layer adopts Al2O3Or HfO2And the dielectric layer is 5nm-20nm thick.
Further, it is characterized in that: the thickness of the diamond substrate is 30-50 μm; the barrier layer is made of any one of AlGaN, InAlN, ScAlN and BALN, and the thickness of the barrier layer is 3nm-30 nm; the insertion layer is made of AlN, and the thickness of the insertion layer is 1nm-2 nm; the channel layer is made of GaN, and the thickness of the channel layer is 10nm-30 nm.
2. A manufacturing method of a diamond-based nitrogen polar surface gallium nitride high electron mobility transistor is characterized by comprising the following steps:
1) growing a transfer layer on the self-supporting gallium nitride epitaxial wafer by using a chemical vapor deposition process;
2) growing a nucleation layer and a buffer layer on the transfer layer in sequence by using a metal organic chemical vapor deposition process;
3) growing a channel layer on the buffer layer by using a metal organic chemical vapor deposition process;
4) growing an insertion layer on the channel layer by using a metal organic chemical vapor deposition process;
5) growing a barrier layer on the insertion layer by using a metal organic chemical vapor deposition process;
6) growing a supporting layer on the barrier layer by using a metal organic chemical vapor deposition process;
7) depositing a transition layer on the support layer by using a low-pressure chemical vapor deposition technology;
8) depositing a diamond substrate on the transition layer by using a microwave plasma chemical vapor deposition process;
9) stripping the nucleation layer and the upper part thereof from the upper surface of the transfer layer;
10) removing the nucleating layer and the buffer layer by using an etching technology;
11) selecting ohmic contact areas of a source electrode and a drain electrode on the surface of the channel layer by adopting a photoetching process, depositing ohmic contact metal Ti/Al/Ni/Au on the ohmic contact areas of the source electrode and the drain electrode by adopting an electron beam evaporation process, and annealing at 830 ℃ in a nitrogen atmosphere to form the source electrode and the drain electrode;
12) growing an insulated gate dielectric layer on the channel layer by adopting an atomic layer deposition process;
13) and selecting a gate electrode pattern on the surface of the insulated gate dielectric layer by adopting a photoetching process, and depositing a Ni/Au metal combination on the insulated gate dielectric layer by adopting an electron beam evaporation process to form a gate electrode so as to finish the manufacture of the device.
Further, it is characterized in that:
the transfer layer in the step 1) adopts a thickness of 2nm-5nm graphene, BN, MoS2Any one of the above;
the nucleating layer in the step 2) is made of GaN or AlN, and the thickness of the nucleating layer is 50nm-200 nm;
the buffer layer in the step 2) is made of GaN, and the thickness of the buffer layer is 1000nm-3000 nm.
Compared with the prior art, the invention has the following advantages:
1. because the transition layer is adopted, the diamond with high thermal conductivity can be used as the substrate, the heat dissipation capability near the active region of the device can be improved, the heat accumulation effect of the device can be improved, and the output characteristic and the reliability of the device can be improved.
2. The invention realizes the nitrogen polar surface gallium nitride high electron mobility transistor by adopting a mode of peeling and turning the grown gallium polar surface gallium nitride material, reduces the process control difficulty of directly epitaxially growing the nitrogen polar surface gallium nitride material, and can realize the nitrogen polar surface gallium nitride material with extremely low background carrier concentration and high crystallization quality.
3. According to the invention, the diamond substrate is directly grown on the epitaxial gallium nitride material, so that the preparation of the nitrogen polar surface gallium nitride device on the high-thermal-conductivity diamond substrate is realized, and the problems of lattice mismatch, crystal phase mismatch and thermal mismatch of the heteroepitaxial nitrogen polar surface gallium nitride material directly on the diamond substrate are avoided.
4. In the invention, the graphene, BN or MoS is adopted in the manufacturing process of the nitrogen polar surface gallium nitride device2The two-dimensional material is used as a transfer layer to realize device stripping, so that the epitaxial gallium nitride material stripping process can be simplified, a smooth and flat stripping interface and large-area stripping can be obtained, and the rough stripping interface caused by directly etching and stripping the epitaxial layer can be avoided.
5. The device of the invention has simple preparation and stripping process and high process repeatability and consistency, and can avoid the performance attenuation of the device after stripping.
Drawings
FIG. 1 is a block diagram of a conventional nitrogen-polarity-face GaN HEMT;
FIG. 2 is a block diagram of a diamond based nitrogen polar plane gallium nitride HEMT of the present invention;
FIG. 3 is a schematic flow chart of the fabrication of a GaN HEMT with a diamond-based N-polar surface according to the present invention.
Detailed Description
Referring to fig. 2, the diamond-based nitrogen polar plane gallium nitride high electron mobility transistor of the invention comprises, from bottom to top, a diamond substrate 1, a transition layer 2, a support layer 3, a barrier layer 4, an insertion layer 5, a channel layer 6, an insulated gate dielectric layer 7 and a gate electrode, wherein both sides of the channel layer 6 are ohmic contact regions on which a source electrode and a drain electrode are respectively arranged. Wherein:
the thickness of the diamond substrate 1 is 30-50 μm;
the transition layer 2 is made of SiN, and the thickness of the transition layer is 50nm-150 nm;
the supporting layer 3 is made of GaN, and the thickness of the supporting layer is 4-10 mu m;
the barrier layer 4 is made of any one of AlGaN, InAlN, ScAlN and BALN, and has a thickness of 3-30 nm;
the insertion layer 5 is made of AlN, and the thickness of the insertion layer is 1nm-2 nm;
the channel layer 6 is made of GaN, and the thickness of the channel layer is 10nm-30 nm;
the insulated gate dielectric layer 7 adopts Al2O3Or HfO2And the dielectric layer is 5nm-20nm thick.
Referring to fig. 3, the diamond-based nitrogen polar plane gallium nitride high electron mobility transistor and the method of fabricating the same according to the present invention provide the following three embodiments.
In the first embodiment, a diamond-based nitrogen polar plane gallium nitride high electron mobility transistor in which graphene is used as a transfer layer and AlGaN is used as a barrier layer is manufactured.
Step one, a self-supporting gan epitaxial wafer is selected as an auxiliary epitaxial substrate, as shown in fig. 3 (a).
Step two, depositing a graphene transfer layer, as shown in fig. 3 (b).
A graphene transfer layer was deposited with a thickness of 5nm on a free-standing gallium nitride substrate using chemical vapor deposition techniques.
The process conditions for depositing the graphene transfer layer are as follows: the temperature is 800 ℃, the methane flow is 25mL/min, the argon flow is 350mL/min, and the hydrogen flow is 15 mL/min.
Step three, an AlN nucleation layer is deposited, as in fig. 3 (c).
And depositing an AlN nucleating layer with the thickness of 200nm on the graphene transfer layer by using a metal organic chemical vapor deposition technology.
The process conditions for depositing the AlN nucleating layer with the thickness are as follows: the temperature is 1150 deg.C, the pressure is 40Torr, the flow of ammonia gas is 2000sccm, the flow of aluminum source is 20sccm, and the flow of hydrogen gas is 3000 sccm.
Step four, depositing a GaN buffer layer, as shown in FIG. 3 (d).
And depositing a GaN buffer layer with the thickness of 1000nm on the AlN nucleating layer by using a metal organic chemical vapor deposition technology.
The technological conditions for depositing the GaN buffer layer are as follows: the temperature was 1100 deg.C, the pressure was 40Torr, the flow of ammonia gas was 2000sccm, the flow of gallium source was 100sccm, and the flow of hydrogen was 3000 sccm.
Step five, depositing a GaN channel layer, as shown in FIG. 3 (e).
A GaN channel layer with a thickness of 30nm was deposited on the GaN buffer layer using a metal organic chemical vapor deposition technique.
The process conditions for depositing the GaN channel layer are as follows: the temperature was 1100 deg.C, the pressure was 40Torr, the flow of ammonia gas was 2000sccm, the flow of gallium source was 90sccm, and the flow of hydrogen was 3000 sccm.
Step six, an AlN insertion layer is deposited, as shown in fig. 3 (f).
An AlN insertion layer with a thickness of 1nm was deposited on the GaN channel layer using a metal organic chemical vapor deposition technique.
The process conditions for depositing the AlN insert layer are as follows: the temperature was 1100 deg.C, the pressure was 40Torr, the aluminum source flow was 10sccm, the ammonia gas flow was 2000sccm, and the hydrogen gas flow was 3000 sccm.
Step seven, depositing an AlGaN barrier layer, as shown in FIG. 3 (g).
Depositing 30nm thick Al on the AlN insert layer using a metal-organic chemical vapor deposition technique0.25Ga0.75An N barrier layer.
Deposition of Al0.25Ga0.75The process conditions adopted by the N barrier layer are as follows: the temperature was 1100 deg.C, the pressure was 40Torr, the flow of ammonia gas was 2000sccm, the flow of aluminum source was 20sccm, the flow of gallium source was 100sccm, and the flow of hydrogen gas was 3000 sccm.
Step eight, depositing a GaN supporting layer, as shown in FIG. 3 (h).
Using metal organic chemical vapor deposition technique on Al0.25Ga0.75A GaN support layer with a thickness of 4 μm was deposited on the N-barrier layer.
The technological conditions adopted for depositing the GaN supporting layer are as follows: the temperature was 1100 deg.C, the pressure was 40Torr, the flow of ammonia gas was 2000sccm, the flow of gallium source was 90sccm, and the flow of hydrogen was 3000 sccm.
And step nine, depositing a SiN transition layer with the thickness of 100nm on the GaN supporting layer by using a low-pressure chemical vapor deposition technology, as shown in a figure 3 (i).
Step ten, deposit the diamond substrate, as in fig. 3 (j).
A diamond substrate with a thickness of 30 μm was deposited on the SiN transition layer using a microwave plasma chemical vapor deposition technique.
The process conditions adopted for depositing the diamond substrate are as follows: the temperature was 850 ℃, the methane flow rate was 30mL/min, the pressure was 150Torr, the microwave power was 3.0kW, the nitrogen flow rate was 60. mu.L/min, and the hydrogen flow rate was 500 mL/min.
Step eleven, the nucleation layer and the upper part thereof are stripped from the upper surface of the transfer layer, as shown in fig. 3 (k).
Step twelve, using etching technique, removing the nucleation layer and the buffer layer, as shown in fig. 3 (l).
And thirteen, manufacturing a source electrode and a drain electrode, as shown in fig. 3 (m).
Selecting a source electrode and drain electrode ohmic contact area on the surface of the stripped channel layer by adopting a photoetching process, and depositing a Ti/Al/Ni/Au metal combination with the thickness of 0.02 mu m/0.05 mu m/0.04 mu m on the source electrode and drain electrode ohmic contact area by adopting an electron beam evaporation process; and then performing rapid thermal annealing for 30s in a nitrogen atmosphere at the temperature of 830 ℃ to form a source electrode and a drain electrode.
The electron beam evaporation adopts the following process conditions: vacuum degree less than 1.2X 10-3Pa, power 400W, evaporation rate
Fourteen, depositing Al with the thickness of 20nm on the GaN channel layer by using an atomic layer deposition process2O3And (e) an insulated gate dielectric layer, as shown in fig. 3 (n).
Step fifteen, a gate electrode is fabricated, as shown in fig. 3 (o).
By adopting a photoetching process on Al2O3Selecting a grid electrode pattern on the insulated gate dielectric layer, and performing electron beam evaporation process on Al2O3And depositing metal on the insulated gate dielectric layer to manufacture a gate, wherein the deposited metal is a Ni/Au metal combination, and the thickness of the metal is 0.02 mu m/0.3 mu m.
The electron beam evaporation adopts the following process conditions: vacuum degree less than 1.2X 10-3Pa, power 400W, evaporation rate
Example two, fabrication by MoS2As a transfer layer, a barrier layer adopts a diamond-based nitrogen polar surface gallium nitride high electron mobility transistor of InAlN.
Step 2, MoS is deposited by using chemical vapor deposition technology2Transfer layer, as in fig. 3 (b).
Using chemical vapor deposition technique at 800 deg.C under nitrogen flow of 200sccm and MoO3MoS with the thickness of 3nm is deposited on the gallium nitride epitaxial wafer under the process conditions that the dosage is 0.2g and the dosage of sulfur powder is 2g2And (3) transferring the layer.
Step 3, depositing a GaN nucleation layer by using a metal organic chemical vapor deposition (mocvd) technique, as shown in fig. 3 (c).
Using metal organic chemical vapor deposition technology, at 1100 deg.C,under the process conditions of 40Torr of pressure, 2000sccm of ammonia gas flow, 100sccm of gallium source flow and 3000sccm of hydrogen gas flow, MoS2A GaN nucleation layer with a thickness of 50nm was deposited on the transfer layer.
Step 4, depositing a GaN buffer layer by using a metal organic chemical vapor deposition (mocvd) technique, as shown in fig. 3 (d).
And depositing a GaN buffer layer with the thickness of 2000nm on the GaN nucleating layer by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1200 ℃, the pressure is 40Torr, the flow of ammonia gas is 2000sccm, the flow of a gallium source is 120sccm and the flow of hydrogen is 3000 sccm.
Step 5, depositing a GaN channel layer using a metal organic chemical vapor deposition technique, as shown in fig. 3 (e).
And depositing a GaN channel layer with the thickness of 20nm on the GaN buffer layer by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1200 ℃, the pressure is 40Torr, the flow of ammonia gas is 2000sccm, the flow of a gallium source is 100sccm and the flow of nitrogen gas is 3000 sccm.
Step 6, an AlN insertion layer is deposited using a metal organic chemical vapor deposition technique, as shown in fig. 3 (f).
And depositing an AlN insert layer with the thickness of 1.5nm on the GaN channel layer by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1200 ℃, the pressure is 40Torr, the flow of an aluminum source is 8sccm, the flow of ammonia gas is 2000sccm and the flow of hydrogen gas is 3000 sccm.
Step 7, depositing In by using metal organic chemical vapor deposition technology0.17Al0.83N barrier layer, FIG. 3 (g).
Depositing 10nm of In on the AlN insert layer by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 700 ℃, the pressure is 300Torr, the flow of an aluminum source is 10sccm, the flow of an indium source is 50sccm, the flow of ammonia gas is 2000sccm and the flow of nitrogen gas is 3000sccm0.17Al0.83An N barrier layer.
Step 8, depositing a GaN support layer using a metal organic chemical vapor deposition technique, as shown in fig. 3 (h).
Using metallo-organic chemical vapour phaseThe deposition technique is carried out under the process conditions of 1200 ℃ of temperature, 40Torr of pressure, 2000sccm of ammonia gas flow, 100sccm of gallium source flow and 3000sccm of hydrogen gas flow0.17Al0.83A GaN support layer with a thickness of 10 μm was deposited on the N-barrier layer.
Step 9, using low pressure chemical vapor deposition technique to deposit a SiN transition layer with a thickness of 50nm on the GaN support layer, as shown in FIG. 3 (i).
Step 10, deposit the diamond substrate, as shown in fig. 3 (j).
A diamond substrate with a thickness of 40 μm was deposited on the SiN transition layer by microwave plasma chemical vapor deposition at a temperature of 900 deg.C, a methane flow of 40mL/min, a pressure of 160Torr, a microwave power of 3.5kW, a nitrogen flow of 70 μ L/min, and a hydrogen flow of 550 mL/min.
Step 11, the nucleation layer and the upper portion thereof are stripped from the upper surface of the transfer layer, as shown in fig. 3 (k).
At step 12, the nucleation layer and the buffer layer are removed using an etching technique, as shown in fig. 3 (l).
Step 13, making source and drain electrodes, as shown in FIG. 3(m)
Selecting ohmic contact region of source electrode and drain electrode on the surface of the stripped channel layer by photolithography, and evaporating by electron beam under vacuum degree of less than 1.2 × 10-3Pa, power 600W, evaporation rate
Under the process conditions of (1), depositing a Ti/Al/Ni/Au metal combination with the thickness of 0.05 mu m/0.12 mu m/0.08 mu m on the ohmic contact areas of the source electrode and the drain electrode; and then performing rapid thermal annealing for 30s in a nitrogen atmosphere at the temperature of 830 ℃ to form a source electrode and a drain electrode.
Step 14, depositing HfO with a thickness of 10nm on the GaN channel layer using an atomic layer deposition process2Insulating gate dielectric layer, as shown in FIG. 3(n)
Step 15, forming a gate electrode, as shown in FIG. 3(o)
Using a photolithography process on HfO2Selecting a gate pattern on an insulated gate dielectric layerUsing electron beam evaporation technique, under vacuum degree of less than 1.2 × 10-3Pa, power 600W, evaporation rate
Under the process conditions of (1), under HfO2And depositing metal on the insulated gate dielectric layer to manufacture a gate, wherein the deposited metal is a Ni/Au metal combination, and the thickness of the metal is 0.04 mu m/0.5 mu m.
In the third embodiment, a diamond-based nitrogen polar plane gan high electron mobility transistor was fabricated using BN as the transfer layer and ScAlN as the barrier layer.
Step a, selecting a self-supporting gan epitaxial wafer as an auxiliary epitaxial substrate, as shown in fig. 3 (a).
Step B, depositing a BN transfer layer, as shown in FIG. 3 (B).
And depositing a BN transfer layer with the thickness of 2nm on the gallium nitride epitaxial wafer by using a metal organic chemical vapor deposition technology and setting the process conditions of 1050 ℃ of temperature, 600Torr of pressure, 25 mu mol/min of triethylboron flow and 1500sccm of ammonia gas flow.
Step C, an AlN nucleation layer is deposited, as in fig. 3 (C).
And depositing an AlN nucleating layer with the thickness of 100nm on the BN transfer layer by using a metal organic chemical vapor deposition technology and setting the process conditions of 1200 ℃ of temperature, 40Torr of pressure, 2000sccm of ammonia gas flow, 20sccm of aluminum source flow and 3000sccm of hydrogen gas flow.
Step D, depositing a GaN buffer layer, as shown in FIG. 3 (D).
And depositing a GaN buffer layer with the thickness of 3000nm on the AlN nucleating layer by using a metal organic chemical vapor deposition technology and setting the process conditions of 1150 ℃ of temperature, 40Torr of pressure, 2000sccm of ammonia gas flow, 90sccm of gallium source flow and 3000sccm of hydrogen gas flow.
Step E, depositing a GaN channel layer, as shown in fig. 3 (E).
And depositing a 10 nm-thick GaN channel layer on the GaN buffer layer by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1150 ℃, the pressure is 40Torr, the flow of ammonia gas is 2000sccm, the flow of a gallium source is 95sccm and the flow of hydrogen is 3000 sccm.
Step F, an AlN insert layer is deposited, as shown in FIG. 3 (F).
And depositing an AlN insert layer with the thickness of 2nm on the GaN channel layer by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1150 ℃, the pressure is 40Torr, the flow of an aluminum source is 6sccm, the flow of ammonia gas is 2000sccm and the flow of hydrogen gas is 3000 sccm.
Step G, deposit a scann barrier layer, as shown in fig. 3 (G).
Using a metal organic chemical vapor deposition technology, and under the process conditions that the temperature is 900 ℃, the pressure is 200Torr, the flow of ammonia gas is 2000sccm, the flow of an aluminum source is 10sccm, the flow of a scandium source is 20sccm, and the flow of hydrogen is 3000sccm, depositing Sc with the thickness of 3nm on the AlN insert layer0.18Al0.82An N barrier layer.
Step H, depositing a GaN support layer, as shown in FIG. 3 (H).
Using metal organic chemical vapor deposition technology, setting the technological conditions of 1150 deg.C, 40Torr of pressure, 2000sccm of ammonia gas, 95sccm of gallium source and 3000sccm of hydrogen gas, and performing the chemical vapor deposition on Sc0.18Al0.82A GaN support layer with a thickness of 7 μm was deposited on the N-barrier layer.
Step I, a SiN transition layer with a thickness of 150nm was deposited on the GaN support layer using a low pressure chemical vapor deposition technique, as shown in fig. 3 (I).
Step J, deposit the diamond substrate, as in fig. 3 (J).
A diamond substrate with a thickness of 50 μm was deposited on the SiN transition layer by using a microwave plasma chemical vapor deposition technique under process conditions of a temperature of 950 ℃, a methane flow of 50mL/min, a pressure of 180Torr, a microwave power of 4.0kW, a nitrogen flow of 80 μ L/min, and a hydrogen flow of 600 mL/min.
Step K, the nucleation layer and its upper portion are stripped from the upper surface of the transfer layer, as shown in fig. 3 (K).
Step L, using an etching technique, removes the nucleation layer and the buffer layer, as shown in fig. 3 (L).
Step M, source and drain electrodes are fabricated, as shown in fig. 3 (M).
Selecting ohmic contact region of source electrode and drain electrode on the surface of the stripped channel layer by photolithography, evaporating by electron beam, and setting vacuum degree less than 1.2 × 10-3Pa, power 500W, evaporation rate
The process conditions of (1) depositing a Ti/Al/Ni/Au metal combination with a thickness of 0.02/0.2/0.05 μm on ohmic contact areas of the source and drain electrodes; and then performing rapid thermal annealing for 30s in a nitrogen atmosphere at the temperature of 830 ℃ to form a source electrode and a drain electrode.
Step N, depositing Al with the thickness of 5nm on the GaN channel layer by using an atomic layer deposition process2O3And (e) an insulated gate dielectric layer, as shown in fig. 3 (n).
And step O, manufacturing a gate electrode, as shown in FIG. 3 (O).
By adopting a photoetching process on Al2O3Selecting a grid electrode pattern on the insulated gate dielectric layer, and performing electron beam evaporation on Al2O3And depositing metal on the insulated gate dielectric layer to manufacture a gate, wherein the deposited metal is a Ni/Au metal combination, and the thickness of the metal is 0.03 mu m/0.4 mu m. The process conditions adopted for depositing the metal are as follows: vacuum degree less than 1.2X 10-3Pa, power 500W, evaporation rate
The above description is only three specific examples of the present invention, and does not constitute any limitation to the present invention, and it is obvious to those skilled in the art that after understanding the content and principle of the present invention, it is possible to remove the graphene, BN, MoS in the present example from the transition layer without departing from the principle and structure of the present invention2In addition to WS2Barrier layers InAlGaN, BAlN and AlN may be used in addition to AlGaN, InAlN and ScAlN in the present example, but various modifications and changes in form and detail thereof are still within the scope of the claims of the present invention.
Claims (10)
1. The utility model provides a diamond base nitrogen polarity face gallium nitride high electron mobility transistor, from bottom to top, includes diamond substrate (1), barrier layer (4), inserted layer (5), channel layer (6), its characterized in that:
a transition layer (2) and a support layer (3) are arranged between the diamond substrate (1) and the barrier layer (4) and are used for depositing the diamond substrate and supporting an active region of a device;
the upper part of the channel layer (6) is sequentially provided with an insulated gate dielectric layer (7) and a gate electrode, the two sides of the channel layer are ohmic contact regions, and a source electrode and a drain electrode are respectively arranged on the ohmic contact regions.
2. The transistor of claim 1, wherein:
the transition layer (2) is made of SiN, and the thickness of the transition layer is 50nm-150 nm;
the supporting layer (3) is made of GaN, and the thickness of the supporting layer is 4-10 mu m;
the insulated gate dielectric layer (7) adopts Al2O3Or HfO2And the dielectric layer is 5nm-20nm thick.
3. The transistor of claim 1, wherein:
the diamond substrate (1) has the thickness of 30-50 μm;
the barrier layer (4) is made of any one of AlGaN, InAlN, ScAlN and BALN, and the thickness of the barrier layer is 3nm-30 nm;
the insertion layer (5) is made of AlN, and the thickness of the insertion layer is 1nm-2 nm;
the channel layer (6) is made of GaN, and the thickness of the channel layer is 10nm-30 nm.
4. A manufacturing method of a diamond-based nitrogen polar surface gallium nitride high electron mobility transistor is characterized by comprising the following steps:
1) growing a transfer layer on the self-supporting gallium nitride epitaxial wafer by using a chemical vapor deposition process;
2) growing a nucleation layer and a buffer layer on the transfer layer in sequence by using a metal organic chemical vapor deposition process;
3) growing a channel layer (6) on the buffer layer by using a metal organic chemical vapor deposition process;
4) growing an insertion layer (5) on the channel layer by a metal organic chemical vapor deposition process;
5) growing a barrier layer (4) on the insertion layer by using a metal organic chemical vapor deposition process;
6) growing a support layer (3) on the barrier layer by using a metal organic chemical vapor deposition process;
7) depositing a transition layer (2) on the support layer by using a low-pressure chemical vapor deposition technology;
8) growing a diamond substrate (1) on the transition layer by using a microwave plasma chemical vapor deposition process;
9) stripping the nucleation layer and the upper part thereof from the upper surface of the transfer layer;
10) removing the nucleating layer and the buffer layer by using an etching technology;
11) selecting ohmic contact areas of a source electrode and a drain electrode on the surface of the channel layer by adopting a photoetching process, depositing ohmic contact metal Ti/Al/Ni/Au on the ohmic contact areas of the source electrode and the drain electrode by adopting an electron beam evaporation process, and annealing at 830 ℃ in a nitrogen atmosphere to form the source electrode and the drain electrode;
12) growing an insulated gate dielectric layer (7) on the channel layer by adopting an atomic layer deposition process;
13) and selecting a gate electrode pattern on the surface of the insulated gate dielectric layer by adopting a photoetching process, and depositing a Ni/Au metal combination on the insulated gate dielectric layer by adopting an electron beam evaporation process to form a gate electrode so as to finish the manufacture of the device.
5. The method of claim 4, wherein: the transfer layer in the step 1) adopts graphene, BN and MoS with the thickness of 2nm-5nm2Any one of them.
6. The method of claim 4, wherein:
the nucleating layer in the step 2) is made of GaN or AlN, and the thickness of the nucleating layer is 50nm-200 nm;
the buffer layer in the step 2) is made of GaN, and the thickness of the buffer layer is 1000nm-3000 nm.
7. The method of claim 4, wherein:
the metal organic chemical vapor deposition in the step 2) has the following process conditions: the temperature is 1100-1200 ℃, the pressure is 40Torr, the flow of ammonia gas is 2000sccm, the flow of aluminum source is 20sccm, the flow of gallium source is 90-120 sccm, and the flow of hydrogen is 3000 sccm.
8. The method of claim 4, wherein:
the metal organic chemical vapor deposition process conditions in the steps 3) and 6) are the same, namely the temperature is 1100-1200 ℃, the pressure is 40Torr, the flow of ammonia gas is 2000sccm, the flow of gallium source is 90-100 sccm, and the flow of hydrogen is 3000 sccm;
the metal organic chemical vapor deposition in the step 4) has the following process conditions: the temperature is 1100-1200 ℃, the pressure is 40Torr, the flow of ammonia gas is 2000sccm, the flow of aluminum source is 6-10 sccm, and the flow of hydrogen is 3000 sccm.
9. The method of claim 4, wherein:
the metal organic chemical vapor deposition in the step 5) has the following process conditions: the temperature is 700 ℃ -1100 ℃, the pressure is 40Torr-300Torr, the flow of ammonia gas is 2000sccm, the flow of aluminum source is 10sccm-20sccm, the flow of gallium source is 100sccm, the flow of indium source is 50sccm, the flow of scandium source is 20sccm, the flow of hydrogen is 3000sccm, and the flow of nitrogen is 3000 sccm;
the microwave plasma chemical vapor deposition in the step 8) has the following process conditions: the temperature is 850-950 ℃, the methane flow is 30-50 mL/min, the pressure is 150-180 Torr, the microwave power is 3.0-4.0 kW, the nitrogen flow is 60-80 muL/min, and the hydrogen flow is 500-600 mL/min.
10. The method of claim 4, wherein:
the electron beam evaporation in 11) and 13) is carried out under the following process conditions: vacuum degree less than 1.2X 10-3Pa, power range of 400W-600W, evaporation rate of
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