CN115692572A

CN115692572A - LED wafer, circuit board, display and preparation method thereof

Info

Publication number: CN115692572A
Application number: CN202211163239.1A
Authority: CN
Inventors: 李炫运
Original assignee: Interface Optoelectronics Shenzhen Co Ltd; Interface Technology Chengdu Co Ltd; Yecheng Optoelectronics Wuxi Co Ltd; General Interface Solution Ltd
Current assignee: Interface Optoelectronics Shenzhen Co Ltd; Interface Technology Chengdu Co Ltd; General Interface Solution Ltd
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2023-02-03
Also published as: TWI823591B

Abstract

The embodiment of the application relates to the technical field of display, aims to solve the technical problem of improving the production yield of a display using a micro LED or a mini LED as a display pixel, and provides an LED wafer, a circuit board, a display and a preparation method of the display. The LED wafer comprises an LED wafer and is characterized in that a partial area of the LED wafer is defined as an LED crystal block, and the LED crystal block comprises a light-transmitting substrate, a plurality of LEDs arranged in multiple rows and multiple columns on the substrate at intervals, a plurality of P electrodes, a plurality of N electrodes and a plurality of N electrode wires. One row of P electrodes and one row of N electrodes are alternately and periodically arranged repeatedly. One side of each LED far away from the substrate is provided with one P electrode and one N electrode at intervals. Each N-pole wiring is in direct contact with and electrically connected with the N electrodes of all the LEDs in a corresponding row.

Description

LED wafer, circuit board, display and preparation method thereof

Technical Field

The application relates to the technical field of display, in particular to an LED wafer, a circuit board, a display and a preparation method of the display.

Background

At present, a method for manufacturing a display using a micro light emitting diode (micro LED) or a mini LED as a display pixel includes a step of transferring a plurality of micro LEDs or mini LEDs from a crystal substrate (wafer) to a bulk on a circuit board. The circuit board generally includes at least two layers of wires, one layer of wires is a row wire for electrically connecting the P electrodes of all the light emitting elements corresponding to the row wire, and the other layer of wires is a column wire for electrically connecting the N electrodes of all the light emitting elements corresponding to the column wire. In addition, the circuit board needs to be provided with dense through holes so as to connect the lower layer of the two layers of wires to the bonding pads of the upper layer of wires. However, as the display has higher resolution requirements, the size of the light emitting element is smaller, and due to the limitation of the minimum drilling size and the minimum drilling tolerance of the circuit board, the area of each through hole plus the tolerance is even larger than the pad of the light emitting element in the existing circuit board. In addition, as the display has higher and higher resolution requirements, the pitch between adjacent light emitting elements is smaller and smaller, and also due to the limitation of the minimum drilling size and the minimum drilling tolerance of the circuit board, in the conventional circuit board, adjacent through holes are almost short-circuited together. Therefore, the production yield of the conventional display using micro LEDs or mini LEDs as display pixels needs to be improved.

Disclosure of Invention

The application provides an LED wafer in a first aspect. A partial area of the LED wafer is defined as an LED crystal block, and the LED crystal block comprises:

a light-transmissive substrate;

the LEDs are arranged on the base material at intervals, and are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction crossed with the first direction;

the plurality of P electrodes and the plurality of N electrodes are alternately and periodically arranged in a row of the P electrodes and a row of the N electrodes, and one P electrode and one N electrode are arranged on one side, far away from the base material, of each LED at intervals; and

and each N-pole wiring is in direct contact with and electrically connected with the N electrodes of all the LEDs in a corresponding row.

According to the LED wafer of the first aspect of the application, the N electrodes of all the LEDs in one row are electrically connected through the N pole routing wire, so that when the LED wafer is electrically tested, the N electrodes corresponding to all the LEDs are not needed to be manufactured to be electrically tested, and only the N electrodes corresponding to one of the LEDs in each row are needed to be manufactured to be electrically tested. Therefore, the jig cost for manufacturing the thimble can be reduced by the electrical measurement of the LED wafer, and the misjudgment rate of the bad thimble is reduced. Furthermore, the substrate of the LED wafer is transparent or translucent, so that after the LED dice are bonded to the circuit board, the substrate does not need to be removed, but remains in the display for reuse as a transparent cover plate. Therefore, in the process of preparing the display, the step of separating the substrate from the LED is reduced, and the manufacturing process is simplified. And because the substrate can be used as the function of the transparent cover plate, the additional cover plate is not needed, the attaching process is saved, and the cost of the cover plate is reduced.

A second aspect of the present application provides a circuit board. The circuit board includes:

an insulating substrate;

a plurality of P-pole routing lines which are arranged on the substrate at intervals;

the plurality of P pole bonding pads are arranged on the substrate at intervals, the plurality of P pole bonding pads are arranged in a plurality of rows along a first direction, all the P pole bonding pads in each row are electrically connected through one corresponding P pole routing wire, the plurality of P pole bonding pads are arranged in a plurality of rows along a second direction crossed with the first direction, and two adjacent P pole bonding pads in each row are insulated and isolated; and

a plurality of N pole bonding pads, which are arranged on the substrate at intervals, and are arranged in a plurality of rows along the second direction, wherein at least two N pole bonding pads are arranged in each row of the N pole bonding pads, and the plurality of P pole bonding pads and the plurality of N pole bonding pads are alternately and periodically arranged in a row of the P pole bonding pads and a row of the N pole bonding pads; and

and the driving chip is positioned on the substrate and electrically connected with the plurality of P pole routing wires and the plurality of N pole bonding pads.

In the circuit board of the second aspect of the present application, the N-pole pad, the P-pole pad and the P-pole trace are on the same circuit layer, and the P-pole pads for connecting the LEDs in the same row are connected together by the P-pole trace, without providing a large number of dense through holes, thereby avoiding the decrease of the yield of the circuit board and the display caused by the drilling process. Especially, the current circuit board is to the condition that LED interval is littleer and littleer, and the yield of through-hole is worse, can't make even, and the circuit board of this application embodiment because it walks the line setting for the individual layer LED, need not the through-hole, does benefit to the promotion of yield, especially does benefit to the promotion of high resolution and utilizes the yield and the productivity of mini LED or micro LED as the display of light emitting component.

A third aspect of the present application provides a method of manufacturing a display. The preparation method of the display comprises the following steps:

providing the circuit board according to the second aspect of the present application, and cutting the LED wafer according to the first aspect of the present application to obtain the LED dice; and

the LED crystal block is jointed to the circuit board, wherein one row of P electrodes corresponds to one row of P electrode pads, the P electrode pads are electrically connected with the P electrodes in a one-to-one correspondence mode, one row of N electrodes corresponds to one row of N electrode pads, the number of the N electrode pads is smaller than or equal to that of the N electrodes, each N electrode pad is electrically connected with one corresponding N electrode, the driving chip is electrically connected with one row of P electrodes of the LEDs through one row of P electrode routing, one row of P electrode pads and one row of P electrodes of the LEDs, and the driving chip is electrically connected with one row of N electrodes of the LEDs through one row of N electrode pads, one row of N electrode routing.

According to the manufacturing method of the display in the third aspect of the application, the LED crystal blocks are integrally connected to the circuit board, a large number of LEDs can be transferred at one time, and compared with a mode that a large number of LEDs are aligned one by one and transferred to the circuit board, the aligning times are reduced, the manufacturing process is simplified, and the yield and the productivity of mass transfer are improved. In addition, in the preparation method of the display, after the LED crystal blocks are jointed with the circuit board, the base material does not need to be removed, and the base material can be used as a cover plate of the display, so that the attachment cost of the cover plate and the material cost of the cover plate are saved.

A fourth aspect of the present application provides a display. The display comprises the circuit board and the LED crystal block combined with the circuit board;

the LED crystal block comprises:

a light-transmissive substrate;

the plurality of P electrodes and the plurality of N electrodes are alternately and periodically arranged in a row of the P electrodes and a row of the N electrodes, and one P electrode and one N electrode are arranged on one side of each LED far away from the base material at intervals; and

a plurality of N-pole wires, each of the N-pole wires being in direct contact with and electrically connected to the N-electrodes of all the LEDs in a corresponding row;

the LED driving circuit comprises a plurality of LEDs, a plurality of P electrodes, a plurality of N electrodes, a driving chip, a plurality of P electrodes and a plurality of N electrodes, wherein one row of the P electrodes corresponds to one row of the P electrodes, the plurality of P electrodes are electrically connected with the plurality of P electrodes in a one-to-one correspondence manner, one row of the N electrodes corresponds to one row of the N electrodes, the number of the plurality of N electrodes is smaller than or equal to that of the plurality of N electrodes, each N electrode is electrically connected with one corresponding N electrode, the driving chip is electrically connected with one row of the P electrodes through one row of the P electrodes, one row of the P electrodes and one row of the P electrodes, and the driving chip is electrically connected with one row of the N electrodes through one row of the N electrodes, one row of the N electrodes and one row of the LEDs.

In the display of the fourth aspect of the present application, the N electrode of the LED is electrically connected through the N pole wiring on the LED die, and the P electrode of the LED is electrically connected through the P pole wiring on the circuit board, because the N pole wiring is disposed on the LED die, not on the circuit board, the wiring is a single layer wiring on the circuit board, and no through hole needs to be disposed, thereby avoiding the decrease of the yield of the circuit board and the display caused by the drilling process. Moreover, the circuit board does not need to be provided with through holes, so that the yield of the circuit board is improved, and the yield and the capacity of a display with high resolution and using a mini LED or a micro LED as a light-emitting element are improved.

Drawings

Fig. 1 is a schematic plan view of a conventional circuit board.

FIG. 2 is a schematic plan view of an LED wafer according to an embodiment of the present application

Fig. 3 is a schematic cross-sectional view along the line III-III in fig. 2.

Fig. 4 is a schematic cross-sectional view along the line IV-IV in fig. 2.

Fig. 5 is a schematic plan view of a circuit board according to an embodiment of the present application.

Fig. 6 is a schematic plan view of a display according to an embodiment of the present application.

Fig. 7 is a schematic cross-sectional view along line VII-VII of fig. 6.

Description of the main element symbols:

LED wafer 10a

LED die 10

Substrate 11

LED 12

N-type semiconductor layer 121

Luminescent layer 122

P-type semiconductor layer 123

N electrode 131

N electrode metal layer 1311

N electrode solder layer 1312

P electrode 132

P electrode metal layer 1321

P electrode solder layer 1322

N-pole wiring 141

Retaining wall 15

Circuit board 20

Substrate 21

Driver chip 22

N-

pole pads

231, 2

Body parts

231a, 232a

First protrusions

231b, 232b

Second projecting

portions

231c, 232c

P-

pole pads

232, 3

P-pole trace 241

Solder mask layer 25

A first direction D1

Second direction D2

Display 100

Line 4

Through hole 5

Detailed Description

Fig. 1 is a schematic plan view of a conventional circuit board. As shown in fig. 1, the circuit board includes a plurality of N-pole pads 2 and P-pole pads 3. The arrangement of the N pole bonding pads 2 and the P pole bonding pads 3 is that one row of the N pole bonding pads 2 and one row of the P pole bonding pads 3 are alternately and periodically arranged in a repeated way. One N-pole pad 2 and one P-pole pad 3 next thereto are grouped to electrically connect N-and P-electrodes of one LED, respectively. The circuit board further includes two layers of traces, one layer of traces is a row trace 4 for electrically connecting the P electrodes of all the LEDs corresponding to the row trace 4, and the other layer of traces is a column trace (not shown) for electrically connecting the N electrodes of all the LEDs corresponding to the column trace, wherein the two layers of traces connect the lower layer of traces to the pads of the upper layer of traces through the through holes 5. However, as the display has higher resolution requirements, the size of the LED is smaller, and due to the limitation of 50 μm in the minimum drilling size diameter of the circuit board and the single side of 50 μm in the minimum drilling tolerance, the area of each through hole plus the tolerance in the existing circuit board is even larger than the pad of the light emitting element. In addition, as the display has higher and higher resolution requirements, the pitch between adjacent light emitting elements is smaller and smaller, and also due to the limitation of the minimum drilling size and the minimum drilling tolerance of the circuit board, in the conventional circuit board, adjacent through holes are almost short-circuited together. That is, when the pitch of the LEDs is smaller than 150 μm, the drilling yield is greatly reduced. Therefore, the production yield of the conventional display using micro LEDs or mini LEDs as light emitting elements needs to be improved.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.

Fig. 2 is a schematic plan view of an LED wafer according to an embodiment of the present application. As shown in fig. 2, the LED wafer 10a includes a circular base material 11. A partial region of the LED wafer 10a is defined as an LED dice 10. The LED die 10 includes a substrate 11, a plurality of LEDs 12, a plurality of N electrodes 131, a plurality of P electrodes 132, and a plurality of N traces 141. The LEDs 12 are spaced on the substrate 11 and arranged in a plurality of columns along a first direction D1 and a plurality of rows along a second direction D2 intersecting the first direction D1. In the embodiment of the present application, the first direction D1 is perpendicular to the second direction D2. The P electrodes 132 are arranged in rows and columns at intervals, and the N electrodes 131 are arranged in rows and columns at intervals. One P electrode 132 and one N electrode 131 per LED12. The plurality of P electrodes 132 and the plurality of N electrodes 131 are alternately and periodically arranged in a row of P electrodes 132 and a row of N electrodes 131. Each N-pole trace 141 extends along the first direction D1 and directly contacts and electrically connects the N-electrodes 131 of all the LEDs 12 in a corresponding row. The plurality of N-pole traces 141 are disposed at intervals along the second direction D2.

In the embodiments of the present application, an LED Wafer refers to an overall structure on which an LED stack is grown on a Wafer (Wafer). The diameter of the wafer may be, for example, 6 inches, 8 inches, 12 inches, and even larger dimensions such as, for example, 14 inches, 15 inches, 16 inches, 20 inches or more. The LED dice may be partial regions on the LED wafer (not yet cut from other parts of the LED wafer 10 a) or may be separated blocks that have been cut from the LED wafer. In addition, the shape and size of the LED dice may be divided according to the shape and size of the display area of the display to be formed, and may be any shape. In the embodiment shown in fig. 2, the LED dice 10 are rectangular. In other embodiments, the shape of the LED dice 10 may be divided according to the shape and size of the display area of the display to be formed, for example, if the display area is circular, the LED dice 10 may be circular, or if the display area is irregular, the LED dice 10 may be irregular.

In some embodiments, the LEDs 12 are micro LEDs, which refers to LEDs 12 having a die size of less than 100 microns. In other embodiments, the LED12 is a mini LED. mini LEDs, also known as sub-millimeter LEDs, are sized between conventional LEDs and micro LEDs, typically meaning LEDs with a die size of approximately 100 to 200 microns.

Fig. 3 is a schematic cross-sectional view along the line III-III in fig. 2. Fig. 4 is a schematic cross-sectional view along the line IV-IV in fig. 2. Referring to fig. 2 to 4, two adjacent LEDs 12 are spaced apart from each other along the second direction D2. Each LED12 includes an N-type semiconductor layer 121, a light emitting layer 122, and a P-type semiconductor layer 123. The N-type semiconductor layer 121 is located on the surface of the substrate 11. The light emitting layer 122 is positioned between the N-type semiconductor layer 121 and the P-type semiconductor layer 123. The P-electrode 132 is located on the side of the P-type semiconductor layer 123 of the LED12 away from the substrate 11. The N-electrode 131 is located on a side of the N-type semiconductor layer 121 of a corresponding LED12 away from the substrate 11. The N-pole trace 141 is at least partially located between the N-type semiconductor layer 121 and the N-electrode 131, and is in direct contact with and electrically connected to the N-type semiconductor layer 121 and the N-electrode 131, respectively. The N-pole trace 141 can be formed by photolithography. The N electrode 131 includes an N electrode metal layer 1311 and an N electrode solder layer 1312. In the second direction D2, the N electrode metal layer 1311 completely covers the corresponding N electrode trace 141 and is in direct contact with the corresponding N type semiconductor layer 121. The N electrode solder layer 1312 covers the surface of the N electrode metal layer 1311 remote from the substrate 11. The P-electrode 132 includes a P-electrode metal layer 1321 and a P-electrode solder layer 1322. In the second direction D2, the P-electrode metal layer 1321 directly contacts the corresponding P-type semiconductor layer 123 and partially covers the corresponding P-type semiconductor layer 123. The P-electrode solder layer 1322 covers the surface of the P-electrode metal layer 1321 away from the substrate 11. The material of the N electrode solder layer 1312 and the P electrode solder layer 1322 is, for example, tin. When the LED dice 10 are bonded to a circuit board, laser light may be irradiated on the side of the substrate 11 facing away from the LEDs 12 to melt the N-electrode solder layers 1312 and the P-electrode solder layers 1322 and bond to the corresponding N-electrode pads and P-electrode pads, respectively, on the circuit board.

The material of the N-type semiconductor layer 121 is, for example, N-type gallium nitride, the material of the P-type semiconductor layer 123 is, for example, P-type gallium nitride, and the material of the light emitting layer 122 is, for example, a multiple quantum well layer, but not limited thereto.

The LED dice 10 also include retaining walls 15 between adjacent LEDs 12 to prevent optical interference between adjacent LEDs 12.

Specifically, the dam 15 is located on the surface of the substrate 11, and is in direct contact with the N-type semiconductor layer 121 and the N-electrode 131 of one LED12, and is in direct contact with the N-type semiconductor layer 121, the light emitting layer 122, and the P-type semiconductor layer 123 of another LED12. The material of the retaining wall 15 is opaque, such as a black matrix. The retaining wall 15 may be formed by a photolithography process.

In the first direction D1, the N-pole trace 141 covers the N-type semiconductor layers 121 of all the LEDs 12 in a corresponding row, and is in direct contact with and electrically connected to the N-electrodes 131 of all the LEDs 12 in the corresponding row. The portion of the N-pole trace 141 located between two adjacent LEDs 12 directly contacts the surface of the substrate 11. The N electrode 131 of each LED12 is located on the surface of the corresponding N electrode trace 141 away from the substrate 11.

In the embodiment of the present application, the N electrodes 131 of all the LEDs 12 in a row are electrically connected by one N-pole wiring 141, so that when the LED wafer 10a is electrically tested, it is not necessary to fabricate a thimble corresponding to the N electrode 131 of each LED12 for power supply and electrical testing, but it is only necessary to fabricate a thimble corresponding to one N electrode 131 of one LED12 in each row of LEDs 12 for power supply and electrical testing. Therefore, the electrical measurement of the LED wafer 10a can reduce the cost of the tool for manufacturing the thimble, and reduce the misjudgment rate of the bad thimble.

In the present embodiment, the substrate 11 is transparent or translucent, and the material thereof is sapphire, for example. By providing the substrate 11 to be light transmissive, the substrate 11 need not be removed after the LED dice 10 are attached to the circuit board, but remains in the display for reuse as a transparent cover plate. Therefore, in the process of manufacturing the display, the steps of separating the substrate 11 from the LED12 are reduced, and the manufacturing process is simplified. Moreover, since the substrate 11 can be used as a transparent cover (cover lens), it is not necessary to additionally dispose a cover, so as to save the bonding process and reduce the cost of the cover.

Fig. 5 is a schematic plan view of a circuit board according to an embodiment of the present application. The circuit board is used for being jointed with the LED crystal block to form a display.

As shown in fig. 5, the circuit board 20 includes an insulating substrate 21, a plurality of P-pole traces 241, a plurality of P-pole pads 232, and a plurality of N-pole pads 231. Specifically, a plurality of P-pole traces 241 are disposed at intervals along the first direction D1. The P electrode pads 232 are spaced apart on the substrate 21, and are arranged in a plurality of columns along the first direction D1 and a plurality of rows along the second direction D2. The adjacent two P-pole pads 232 in each row are insulated and isolated. All the P-pole pads 232 of each column are electrically connected by a corresponding P-pole trace 241. The plurality of N-pole pads 231 are spaced apart on the substrate 21 and arranged in a plurality of rows along the second direction D2. The plurality of P-pole pads 232 and the plurality of N-pole pads 231 are alternately and periodically arranged in a row of P-pole pads 232 and a row of N-pole pads 231.

In the embodiment shown in fig. 5, there are two N-pole pads 231 per row. Each N-pole pad 231 is either between two P-pole pads 232 of the first column or between two P-pole pads 232 of the last column. Each P-electrode pad 232 is used for being electrically connected with the P-electrode 132 of a corresponding LED12, and each N-electrode pad 231 is used for being electrically connected with the N-electrode 131 of a corresponding LED12. One P-electrode pad 232 and one N-electrode pad 231 in the dashed line form a group to electrically connect the P-electrode 132 and the N-electrode 131 of the same LED12, respectively. Therefore, on the circuit board 20, for the LEDs 12 to be received, the first and last columns have the N-pole pads 231 and the P-pole pads 232, respectively, while the middle column between the first and last columns is provided with only the P-pole pads 232 and is not provided with the N-pole pads 231. Thus, the number of pads on the circuit board 20 can be reduced, the soldering time can be reduced, and the defective rate caused by soldering can be reduced.

In other embodiments, the number of the N-pole pads 231 in each row may be more than two, for example, one N-pole pad 231 is disposed in each of the first column and the last column, and the N-pole pad 231 may also be disposed on the P-pole trace 241 between the corresponding P-pole pads 232 in the middle column (the P-pole trace 241 and the N-pole pad 231 may be insulated by disposing the solder mask 25), so as to increase the position of the electrical connection between the N-pole pad 231 on the circuit board 20 and one row of the LEDs 12, and avoid the problem of the electrical connection failure between the circuit board 20 and the row of the LEDs 12 when the first and the last N-pole pads 231 and the corresponding N-poles 131 of the LEDs 12 are all electrically connected poorly.

Among the plurality of rows of pads formed by the plurality of P-pole pads 232 and the plurality of N-pole pads 231, at least two of the plurality of pads include a body portion and first and second projecting portions extending beyond the body portion from the first and second directions D1 and D2, respectively. And the bonding pads at the non-corner positions only comprise the body part. The main body is substantially rectangular, but not limited thereto.

The provision of the projections through the lands at the corners on the circuit board 20 can be used as alignment marks for bonding of the LEDs 12 in the step of transferring the LED dice 10. Therefore, an alignment mark does not need to be additionally manufactured on the circuit board 20, so that the space on the circuit board 20 is saved, and the design of a narrow frame of the display is facilitated.

Specifically, in the embodiment shown in fig. 5, the first row of pads is the N-pole pad 231, and the last row of pads is the P-pole pad 232. The N-pole pad 231 at the head of the first row and the N-pole pad 231 at the tail of the first row respectively include a body 231a for electrically connecting with the N-electrode 131 of the LED12, and a first protrusion 231b extending from the body 231a in the first direction D1 and a second protrusion 231c extending from the body 231a in the second direction D2. The first protruding portions 231b of the N-pole pad 231 at the head of the first row and the N-pole pad 231 at the tail of the first row extend from the negative direction and the positive direction of the first direction, respectively.

The P-pole pad 232 at the head of the last row and the P-pole pad 232 at the tail of the last row respectively include a body portion 232a for electrically connecting with the P-electrode 231 of the LED12, and a first protrusion portion 232b extending from the body portion 232a along the first direction D1 and a second protrusion portion 232c extending from the body portion 232a along the second direction D2. The P-pole pad 232 at the head of the last row and the first protrusion 232b at the end of the last row extend in the negative and positive directions from the first direction, respectively.

When the LED dice 10 are joined to the circuit board 20, only two adjacent edges of the corresponding LEDs 12 on the LED dice 10 need to be aligned with the boundaries of the body portion and the first protruding portion, and the boundaries of the body portion and the second protruding portion, respectively; or, the vertex of the corner of the corresponding LED12 on the LED dice 10 is aligned with the point where the main body, the first protrusion and the second protrusion meet.

In some embodiments, the first protruding portion 231b and the first protruding portion 232b extend beyond the first direction D1 by more than 40 μm, and the second protruding portion 231c and the second protruding portion 232c extend beyond the second direction D2 by more than 40 μm (e.g., 40 μm, 50 μm, etc.). When the first protruding portion 231b and/or the second protruding portion 231c extend beyond the main body 231a too long, and the first protruding portion 232b and/or the second protruding portion 232c extend beyond the main body 232a too long, the circuit board 20 is occupied with a large space; when the length of the first protruding portion 231b and/or the second protruding portion 231c extending beyond the main body 231a is too short, and the length of the first protruding portion 232b and/or the second protruding portion 232c extending beyond the main body 232a is too short, the alignment accuracy may be affected.

Compared with the existing double-layer routing design that the N pole bonding pad and the P pole bonding pad of the LED are respectively connected through the existing walking line layer and the existing row routing layer, and a large number of dense through holes are arranged, in the embodiment of the application, the N pole bonding pad 231, the P pole bonding pad 232 and the P pole routing 241 are on the same line layer, and the P pole bonding pads 232 in the same row for connecting the LED12 are connected together through the P pole routing 241, so that a large number of dense through holes do not need to be arranged, and the reduction of the yield of the circuit board and the display caused by the drilling process is avoided. Especially, the current circuit board is to the condition that LED interval is littleer and littleer, and the yield of through-hole is worse, can't make even, and the circuit board of this application embodiment because it walks the line setting for the individual layer LED, need not the through-hole, does benefit to the promotion of yield, especially does benefit to the promotion of high resolution and utilizes the yield and the productivity of mini LED or micro LED as the display of light emitting component. In addition, since no through hole is required, the circuit board 20 of the embodiment of the present application may use a material that is not easily perforated, such as glass, as the substrate 21.

Understandably, the circuit board 20 further includes a driving chip 22 (shown in fig. 7) and a solder mask layer 25 (shown in fig. 7) on the substrate 21. The driving chip 22 is electrically connected to the P-pole traces 241 and the N-pole pads 231. The solder mask 25 covers at least a portion of each P-pole trace 241 between two adjacent P-pole pads 232. After the LED dice 10 are bonded to the circuit board 20, the N-electrode pads 231 on the circuit board 20 are electrically connected to the N-electrodes of the corresponding LEDs 12, the P-electrode pads 232 are electrically connected to the P-electrodes 132 of the corresponding LEDs 12, and the solder mask layer 25 is located between the N-electrodes 131 and the P-electrode traces 241, so that the N-electrodes 131 and the P-electrode traces 241 are insulated and isolated. The driving chip 22 is electrically connected to the P electrodes 132 of one row of LEDs 12 through one P trace 241 and one row of P pads 232, so as to apply a driving voltage to the P electrodes 132 of the corresponding row of LEDs 12. The driving chip 22 is electrically connected to the N electrodes 131 of the LEDs 12 in a row through a row of N pads 231 and an N trace 141, so that the N electrodes 131 of the LEDs 12 in the corresponding row maintain a common cathode voltage (e.g., ground). When the P electrode 132 and the N electrode 131 of the LED12 have a voltage difference, the LED12 emits light.

The embodiment of the application also provides a preparation method of the display. The preparation method comprises the following steps S1 and S2.

Step S1: and providing a circuit board, and cutting the LED wafer to obtain an LED crystal block.

Specifically, in step S1, the circuit board is, for example, the circuit board 20 shown in fig. 5 described above. The LED wafer is, for example, the LED12 wafer shown in fig. 2. In step S1, pads and lines on the circuit board 20 can be designed according to the shape and size of the display area of the display 100, and the LED dice 10 with corresponding shape and size can be cut out.

Referring to fig. 2 and 5, a row of P electrodes 132 on the LED die 10 corresponds to a row of P pads 232 on the circuit board 20, and the number of the P electrodes 132 on the LED die 12 is the same as the number of the P pads 232 on the circuit board 20, and the arrangement positions correspond to each other. The N electrodes 131 in one row on the LED dice 10 correspond to the N pads 231 in one row on the circuit board 20, and the number of the N electrodes 131 on the LED dice 12 is greater than the number of the N pads 231 on the circuit board 20, and in the position arrangement, the N electrodes 131 in the first and last columns on the LED dice 10 correspond to the N pads 231 in the first and last columns on the circuit board 20 one to one. In addition, the N electrode 131 corresponding to the middle column on the LED die 10 is not provided with the N electrode pad 231 on the circuit board 20, but corresponds to the position of the P electrode trace 241 (it should be noted that the P electrode trace 241 at the position is provided with the solder mask layer 25, the material of the solder mask layer 25 is, for example, solder mask ink, so that after the LED die 10 is transferred onto the circuit board 20, the N electrode 131 and the P electrode trace 241 are insulated and isolated).

Step S2: and bonding the LED crystal block to the circuit board.

Specifically, referring to fig. 2, 5 and 6, taking a bonding pad at the leftmost corner as an example, the LED die 10 is transferred onto the circuit board 20, such that the long side of the left side of the LED12 at the leftmost corner on the LED die 10 is aligned with the boundary between the first protruding portion 231b and the body portion 231a, and the short side of the upper side of the LED12 at the leftmost corner on the LED die 10 is aligned with the boundary between the second protruding portion 231c and the body portion 231a, and the LED die 10 is transferred onto the circuit board 20. And similarly, the bonding pad at the leftmost lower corner, the bonding pad at the rightmost lower corner and the bonding pad at the rightmost upper corner are used as alignment marks for transferring.

After the LED die 10 is transferred to the circuit board 20, the LED die 10 is irradiated with laser light on a side away from the circuit board 20 to melt the N electrode solder layer 1312 and the P electrode solder layer 1322, so that the P electrode pads 232 are electrically connected to the P electrodes 132 one by one, and each N electrode pad 231 is electrically connected to a corresponding N electrode 131. The driving chip 22 is electrically connected to the P electrodes 132 of one row of LEDs 12 through a P-pole trace 241 and a row of P-pole pads 232, and the driving chip 22 is electrically connected to the N electrodes 131 of one row of LEDs 12 through a row of N-pole pads 231 and an N-pole trace 141. Thus, the display 100 is obtained.

It should be noted that, in the embodiment of the present application, the substrate 11 of the LED die 10 is transparent or transparent, after the LED12 die is bonded to the circuit board 20, the substrate 11 does not need to be removed, and the substrate 11 can be used as a cover plate of the display 100, so that the cover plate bonding cost and the cover plate material cost are saved. In addition, according to the manufacturing method of the display, the LED crystal blocks 10 are integrally connected to the circuit board 20, so that a large number of LEDs can be transferred at one time, and compared with a mode of aligning a large number of LEDs one by one and transferring the LEDs to the circuit board, the aligning times are reduced, the manufacturing process is simplified, and the yield and the productivity of mass transfer are improved.

Fig. 7 is a schematic cross-sectional view along line VII-VII of fig. 6. As shown in fig. 6 and 7, the display 100 includes a circuit board 20 and an LED dice 10 combined with the circuit board 20. The LED die 10 includes a transparent substrate 11, a plurality of LEDs 12 spaced apart on the substrate 11, a plurality of P electrodes 132, a plurality of N electrodes 131, and a plurality of N traces 141. The plurality of LEDs 12 are arranged in a plurality of rows along a first direction D1 and in a plurality of columns along a second direction D2 intersecting the first direction D1, and each LED12 includes an N-type semiconductor layer 121, a light emitting layer 122, and a P-type semiconductor layer 123, wherein the N-type semiconductor layer 121 is located on the surface of the substrate 11, and the light emitting layer 122 is located between the N-type semiconductor layer 121 and the P-type semiconductor layer 123. Each P-electrode 132 is located on a side of the P-type semiconductor layer 123 of a corresponding LED12 away from the substrate 11. Each N-electrode 131 is located on a side of the N-type semiconductor layer 121 of a corresponding LED12 away from the substrate 11, wherein the P-electrodes 132 and the N-electrodes 131 are alternately and periodically arranged in a row of P-electrodes 132 and a row of N-electrodes 131. Each N-pole trace 141 covers the N-type semiconductor layers 121 of all the LEDs 12 in a corresponding row, and is in direct contact with and electrically connected to the N-electrodes 131 of all the LEDs 12 in the corresponding row. One row of P electrodes 132 corresponds to one row of P electrode pads 232, the P electrode pads 232 are electrically connected with the P electrodes 132 in a one-to-one correspondence manner, one row of N electrodes 131 corresponds to one row of N electrode pads 231, the number of the N electrode pads 231 is less than or equal to the number of the N electrodes 131, each N electrode pad 231 is electrically connected with one corresponding N electrode 131, the driving chip 22 is electrically connected with one row of P electrodes 132 of one row of LEDs 12 through one P electrode routing line 241 and one row of P electrode pads 232, and the driving chip 22 is electrically connected with one row of N electrodes 131 of one row of LEDs 12 through one row of N electrode pads 231 and one row of N electrode routing line 141. The first protrusion 231b, the first protrusion 232b, the second protrusion 231c, and the second protrusion 232c all extend beyond the substrate 11.

According to the display provided by the embodiment of the application, the N electrode of the LED is electrically connected with the N pole wiring on the LED crystal block, the P electrode of the LED is electrically connected with the P pole wiring on the circuit board, and the N pole wiring is arranged on the LED crystal block instead of the circuit board, so that the circuit board is a single-layer wiring without arranging through holes, and the reduction of the yield of the circuit board and the display caused by the drilling process is avoided. Moreover, the circuit board does not need to be provided with through holes, so that the yield of the circuit board is favorably improved, and the yield and the capacity of a display which utilizes a mini LED or a micro LED as a light-emitting element with high resolution are favorably improved.

Although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the present application.

Claims

1. An LED wafer, wherein a partial region of the LED wafer is defined as an LED die, and the LED die comprises:

a light-transmissive substrate;

2. The LED wafer of claim 1, wherein the LED dice further comprises a dam between adjacent LEDs to prevent optical interference between adjacent LEDs.

3. A circuit board, comprising:

an insulating substrate;

a plurality of P-pole wires which are arranged on the substrate at intervals;

the plurality of P pole bonding pads are arranged on the substrate at intervals, the plurality of P pole bonding pads are arranged in multiple rows along a first direction, all the P pole bonding pads in each row are electrically connected through one corresponding P pole routing wire, the plurality of P pole bonding pads are arranged in multiple rows along a second direction crossed with the first direction, and two adjacent P pole bonding pads in each row are insulated and isolated; and

and the driving chip is positioned on the substrate and electrically connected with the plurality of P pole wires and the plurality of N pole bonding pads.

4. The circuit board according to claim 3, further comprising a solder mask layer, wherein the solder mask layer covers at least a portion of each of the P traces between two adjacent P pads.

5. The circuit board according to claim 3 or 4, wherein the plurality of P-pole pads and the plurality of N-pole pads together form a plurality of rows of pads, at least two of the pads at the head of the first row, the pads at the tail of the first row, the pads at the head of the last row, and the pads at the tail of the last row comprise a body portion and first and second projections extending beyond the body portion from the first and second directions, respectively.

6. A method for manufacturing a display, comprising:

providing a circuit board according to any one of claims 3 to 5, and cutting the LED wafer according to claim 1 or 2 to obtain the LED crystal block; and

7. The method according to claim 6, wherein in the step of bonding the LED dice to the circuit board, in a case where among the plurality of rows of pads collectively constituted by the plurality of P-pole pads and the plurality of N-pole pads, at least two of the pads at a head of a first row, the pads at a tail of the first row, the pads at a head of a last row, and the pads at a tail of the last row include a body portion and first and second projections extending beyond the body portion from the first and second directions, respectively, the projections are used as alignment marks in the step of bonding the LED dice to the circuit board.

8. A display comprising a circuit board according to any one of claims 3 to 5 and an LED die bonded to the circuit board;

the LED crystal block comprises:

a light-transmissive substrate;

9. The display according to claim 8, wherein in a case that the circuit board further includes a solder mask layer covering at least a portion of each P-pole trace between two adjacent P-pole pads, the solder mask layer is located between the N-electrode and the P-pole trace, so as to insulate and isolate the N-electrode from the P-pole trace.

10. The display device according to claim 8 or 9, wherein in a case where among the plurality of rows of pads collectively constituted by the plurality of P-pole pads and the plurality of N-pole pads, at least two of the pads at a head of a first row, the pads at a tail of the first row, the pads at a head of a last row, and the pads at a tail of the last row include a body portion and first and second projections extending beyond the body portion from the first and second directions, respectively, the first and second projections extend beyond the base material.