KR102215937B1 - Semiconductor light emitting device - Google Patents

Abstract

The present disclosure provides a semiconductor light emitting element comprising: a substrate which relates to a rigid substrate having a plurality of second holes penetrating an upper portion and a lower portion and a groove formed at a lower portion, and including a plurality of first holes formed inside grooves in a plane surface; at least one semiconductor light emitting element chip provided on the substrate and including a plurality of electrodes; a pad formed to be spaced apart from the plurality of electrodes on a plane surface by a predetermined distance and electrically connected to the outside; a through-connection formed in the plurality of first holes and the plurality of second holes; a driving element provided in the groove and electrically connected to the pad and the semiconductor light emitting element chip; and a connection layer provided on the substrate to electrically connect the pad, the driving device, and the semiconductor light emitting element chip, wherein the connection layer includes: an electrical connection provided on the substrate and electrically connected between the plurality of first holes and the plurality of second holes; and an insulation layer covering the electric connection such that a first hole not connected to the electric connection is exposed and a portion of the electric connection is exposed, and the semiconductor light emitting element chip is electrically connected to the first hole exposed by the insulating layer and to the electric connection exposed by the insulating layer. The present invention can electrically connect the upper part to the lower part of the semiconductor light emitting element through the hole formed on the substrate.

Description

Semiconductor light emitting device{SEMICONDUCTOR LIGHT EMITTING DEVICE}

The present disclosure generally relates to a semiconductor light emitting device, and in particular, to a highly reliable semiconductor light emitting device.

Here, a background technology related to the present disclosure is provided, and these do not necessarily mean a known technology (This section provides background information related to the present disclosure which is not necessarily prior art). In addition, in the present specification, direction indications such as top/bottom and top/bottom are based on the drawings.

1 is a diagram illustrating an example of a conventional semiconductor light emitting device chip.

The semiconductor light emitting device chip includes a growth substrate 10 (e.g., a sapphire substrate), a buffer layer 20 on the growth substrate 10, a first semiconductor layer 30 having a first conductivity (e.g., an n-type GaN layer), and electrons. An active layer 40 generating light through recombination of holes (eg: INGaN/(In)GaN MQWs), a second semiconductor layer 50 having a second conductivity different from the first conductivity (eg, a p-type GaN layer) are sequentially A translucent conductive film 60 for current diffusion and an electrode 70 serving as a pad are formed thereon, and an electrode serving as a pad on the exposed first semiconductor layer 30 by etching ( 80: Example: Cr/Ni/Au laminated metal pad) is formed. The semiconductor light emitting device of the shape as shown in FIG. 1 is specifically referred to as a lateral chip. Here, when the growth substrate 10 side is electrically connected to the outside, it becomes a mounting surface. In the present specification, the semiconductor light emitting device chip or the exterior to which the semiconductor light emitting device is electrically connected means a printed circuit board (PCB), a submount, a thin film transistor (TFT), and the like.

2 is a view showing another example of a semiconductor light emitting device chip disclosed in US Patent Publication No. 7,262,436. For convenience of explanation, the reference numerals have been changed.

The semiconductor light emitting device chip includes a growth substrate 10, a first semiconductor layer 30 having a first conductivity on the growth substrate 10, an active layer 40 generating light through recombination of electrons and holes, and a first conductivity. A second semiconductor layer 50 having a second conductivity different from that is sequentially deposited, and a three-layered electrode film 90, 91, 92 for reflecting light toward the growth substrate 10 is formed thereon. have. The first electrode layer 90 may be an Ag reflective layer, the second electrode layer 91 may be a Ni diffusion barrier layer, and the third electrode layer 92 may be an Au bonding layer. An electrode 80 serving as a pad is formed on the first semiconductor layer 30 exposed by etching. Here, when the electrode film 92 side is electrically connected to the outside, it becomes a mounting surface. The semiconductor light emitting device chip of the shape as shown in FIG. 2 is specifically referred to as a flip chip. In the case of the flip chip shown in FIG. 2, the electrode 80 formed on the first semiconductor layer 30 is at a lower height than the electrode films 90, 91 and 92 formed on the second semiconductor layer, but may be formed at the same height. You can also do it. Here, the standard of the height may be the height from the growth substrate 10.

3 is a view showing another example of a semiconductor light emitting device chip disclosed in US Patent Publication No. 8,008,683. For convenience of explanation, the reference numerals have been changed.

The semiconductor light emitting device chip includes a first semiconductor layer 30 having a first conductivity, an active layer 40 generating light through recombination of electrons and holes, and a second semiconductor layer 50 having a second conductivity different from the first conductivity. ) Are sequentially formed, and supply current to the upper electrode 31 and the second semiconductor layer 50 formed on the side from which the growth substrate is removed, and a support substrate (for supporting the semiconductor layers 30, 40, 50) ( 51), and a lower electrode 52 formed on the support substrate 51. The upper electrode 31 is electrically connected to the outside using wire bonding. When the lower electrode 52 side is electrically connected to the outside, it functions as a mounting surface. As shown in FIG. 3, a semiconductor light emitting device chip having a structure in which one electrode 31 and 52 is disposed above and below the active layer 40 is referred to as a vertical chip.

4 is a diagram illustrating an example of a conventional semiconductor light emitting device.

The semiconductor light emitting device 100 includes a lead frame 110 and 120 functioning as a pad, a mold 130, and a vertical type light emitting device chip 150 in the cavity 140, The cavity 140 is filled with an encapsulant 170 containing a wavelength converting material 160. The lower surface of the vertical semiconductor light emitting device chip 150 is electrically directly connected to the lead frame 110, and the upper surface is electrically connected to the lead frame 120 by a wire 180. Part of the light emitted from the vertical semiconductor light emitting device chip 150 excites the wavelength converter 160 to generate light of different colors, and two different lights may be mixed to produce white light. For example, the semiconductor light emitting device chip 150 produces blue light, and the light generated by excitation by the wavelength converter 160 is yellow light, and blue light and yellow light are mixed to produce white light. FIG. 4 shows a semiconductor light emitting device using the vertical semiconductor light emitting device chip 150 shown in FIG. 3, but using the semiconductor light emitting device chip shown in FIGS. 1 and 2 Devices can also be manufactured.

5 is a diagram showing an example of an LED display disclosed in Japanese Laid-Open Patent Publication No. 1995-288341. For convenience of explanation, the reference numerals have been changed.

5 is a plan view 190 illustrating a single pixel structure in an LED display. In a pixel structure, semiconductor light emitting device chips 194, 195, and 196 are electrically connected to a conductor layer 191 formed on a PCB. The semiconductor light emitting device chip 194 emitting blue light is a lateral chip and is electrically connected to the conductor layer 191 through wire bonding, and is bonded to the conductor layer 191 with an insulating adhesive 193. The semiconductor light emitting device chips 195 and 196 emitting green and red light are vertical chips and are electrically connected to the conductor layer 191 through a conductive adhesive 197 and wire bonding. In addition, it is surrounded by a cover part 192 to distinguish it from other adjacent pixels. Although not shown in the drawing, a sealing material covers the semiconductor light emitting device chips 194, 195 and 196 to protect the semiconductor light emitting device chips 194, 195, and 196.

According to the trend of miniaturization and weight reduction, the size of semiconductor light emitting devices has gradually become smaller. However, in the case of a semiconductor light emitting device using a mini or micro semiconductor light emitting device chip having a size of 300 μm or less with a maximum side size, the size of the pad and the spacing between the pads decrease, causing problems in the SMT process such as short circuit and poor adhesion.

Accordingly, the present disclosure is to solve the problems in the SMT process in a semiconductor light emitting device using a mini or micro semiconductor light emitting device chip, and furthermore, to provide a semiconductor light emitting device suitable for a transparent display.

This will be described later in the'Specific Contents for the Implementation of the Invention'.

Here, a summary of the present disclosure is provided, and this section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).

According to one aspect of the present disclosure, in a semiconductor light emitting device, a plurality of second holes penetrating the upper and lower portions and a hard substrate having a groove formed at the lower portion thereof; as, a groove on a plane surface. A substrate including a plurality of first holes formed on the inside of the substrate; At least one semiconductor light emitting device chip provided on the substrate and including a plurality of electrodes; A pad formed at a distance from the plurality of electrodes on a plane and electrically connected to the outside; A through connection formed in the plurality of first holes and the plurality of second holes; A driving device provided in the groove and electrically connected to the pad and the semiconductor light emitting device chip; And a connection layer provided on the substrate and electrically connecting the pad, the driving device, and the semiconductor light emitting device chip, wherein the connection layer is provided on the substrate, and includes a plurality of first holes and a plurality of second holes. An electrical connection electrically connected; And, the first hole not connected to the electrical connection is exposed, and an insulating layer covering the electrical connection to expose a part of the electrical connection; Including, the semiconductor light emitting device chip is exposed by the insulating layer A semiconductor light emitting device is provided that is electrically connected to the electrical connection exposed by the formed first hole and the insulating layer, respectively.

This will be described later in the'Specific Contents for the Implementation of the Invention'.

1 is a diagram showing an example of a conventional semiconductor light emitting device chip;
2 is a view showing another example of a semiconductor light emitting device chip disclosed in US Patent Publication No. 7,262,436;
3 is a view showing another example of a semiconductor light emitting device chip proposed in US Patent Publication No. 8,008,683;
4 is a view showing an example of a conventional semiconductor light emitting device;
5 is a view showing an example of the LED display disclosed in Japanese Patent Laid-Open No. 1995-288341,
6 is a view showing an example of a semiconductor light emitting device according to the present disclosure;
7 is a view showing another example of a semiconductor light emitting device according to the present disclosure;
8 is a view showing still another example of a semiconductor light emitting device according to the present disclosure;
9 is a view showing still another example of a semiconductor light emitting device according to the present disclosure;
Fig. 10 is a diagram explaining in detail A in Fig. 9(b);
11 is a diagram illustrating examples of patterns according to the present disclosure;
12 is a diagram illustrating an example of a method of manufacturing a semiconductor light emitting device according to the present disclosure;
13 is a view showing another example of a method of manufacturing a semiconductor light emitting device according to the present disclosure;
14 is a diagram illustrating a Zener diode according to the present disclosure;
15 is a view showing another example of a semiconductor light emitting device according to the present disclosure;
16 to 18 are views showing still another example of a semiconductor light emitting device according to the present disclosure;
19 to 20 are views showing still another example of a method of manufacturing a semiconductor light emitting device according to the present disclosure;
21 is a view showing another example of a semiconductor light emitting device according to the present disclosure;
22 is a view showing another example of a semiconductor light emitting device according to the present disclosure;
23 to 25 are views showing still another example of a method of manufacturing a semiconductor light emitting device according to the present disclosure.

Hereinafter, the present disclosure will now be described in detail with reference to the accompanying drawing(s)).

6 is a diagram illustrating an example of a semiconductor light emitting device according to the present disclosure.

FIG. 6(a) is a plan view of the semiconductor light emitting device 100, and FIG. 6(b) shows a cross-section AA′ of FIG. 6(a).

The semiconductor light emitting device 100 includes at least one semiconductor light emitting device chip 110, a plurality of pads 121, an electrical connection 123, and an encapsulant 150.

At least one semiconductor light emitting device chip 110 includes a plurality of electrodes 111.

The plurality of pads 121 are formed at a predetermined distance away from the at least one semiconductor light emitting device chip 110 on a plane. The semiconductor light emitting device 100 is directly electrically connected to the outside through the pad 121.

The plurality of pads 121 are not provided under the at least one semiconductor light emitting device chip 110. That is, a predetermined distance is formed between the plurality of pads 121 and at least one semiconductor light emitting device chip 110. By forming a predetermined distance between the plurality of pads 121 and at least one semiconductor light emitting device chip 110, the size of the pads 121 can be increased, and the spacing between the pads 121 is widened to increase the SMT (Surface Mounting Technology). Mounted Technology) in the process, solved problems such as short circuit and poor adhesion. In addition, when elements occupying a certain area, such as the pad 121 and the semiconductor light emitting device chip 110, among the devices constituting the semiconductor light emitting device 100 are provided apart from each other without being concentrated and applied to a transparent display, the semiconductor light emitting device 100 Can be made inconspicuous. Furthermore, since light can be emitted through the gap between the pad 121 and the semiconductor light emitting device chip 110, 6-sided light emission is possible. In this case, the plurality of pads 121 correspond to the plurality of electrodes 111, respectively.

The electrical connection 123 is provided between the plurality of pads 121 and the plurality of electrodes 111. The electrical connection 123 electrically connects the plurality of pads 121 and the plurality of electrodes 111. In particular, the electrical connection 123 may be formed on the same plane as the pad 121.

The electrical connection 123 is formed as a single line in FIG. 6A. When the electrical connection 123 is formed with a single line, a problem in that the semiconductor light emitting device chip 110 cannot be driven may occur when the electrical connection 123 is disconnected, and a solution thereof will be described in FIG. 7.

The encapsulant 150 covers at least one semiconductor light emitting device chip 110. The light-transmitting encapsulant 150, the semiconductor light emitting device chip 110, and the pad 121 are formed at predetermined intervals, so that the present disclosure may be a semiconductor light emitting device capable of emitting six-sided light. A plurality of pads 121 and electrical connections 123 may protrude from the encapsulant 150. A case in which the plurality of pads 121 and the electrical connection 123 are formed in the encapsulant 150 will be described with reference to FIG. 7.

It is preferable that the size of the pad 121 is larger than the size of the semiconductor light emitting device chip 110 and a predetermined distance between the pad 121 and the semiconductor light emitting device chip 110 is larger than the size of the semiconductor light emitting device chip 110. For example, the size of one semiconductor light emitting device chip 110 is a mini or micro semiconductor light emitting device chip having a maximum side size of 300 μm or less, and the size of one pad 121 is a maximum side size of 100 μm or more, and one The maximum side size of the distance between the pad 121 and one semiconductor light emitting device chip 110 is 150 μm or more, and the size of the semiconductor light emitting device 100 is 300 μm or more.

7 is a diagram illustrating another example of a semiconductor light emitting device according to the present disclosure.

7(a) is a view showing a plan view of the semiconductor light emitting device 100, and FIG. 7(b) is a view showing a cross section of the semiconductor light emitting device 100 of FIG. 7(a).

The electrical connection 123 forms a plurality of paths between the plurality of pads 121 and the plurality of electrodes 111, respectively. Since the plurality of pads 121 and the plurality of electrodes 111 are electrically connected through a plurality of paths, even if one path is disconnected, the plurality of pads 121 and the plurality of electrodes 111 are electrically connected through the remaining paths. It is connected by Therefore, if there is only one line as shown in FIG. 6(a), the semiconductor light emitting device does not operate when one line is disconnected, but even if one line is disconnected, between the plurality of pads 121 and the plurality of electrodes 111 Any one of a plurality of paths of the electrical connection 123 may be electrically connected to. In addition, since the electrical connection 123 is not concentrated and spreads thin and wide, the back side of the semiconductor light emitting device 100 is more visible.

The encapsulant 150 covers the electrical connection 123 and at least a portion of the electrical connection 123 may be exposed. The encapsulant 150 may cover the plurality of pads 121 and at least a portion of the pads may be exposed.

Zener diode 130 is provided to prevent reverse voltage applied to at least one semiconductor light emitting device chip 110. The Zener diode 130 is connected in parallel with the semiconductor light emitting device chip 110, and when a reverse voltage is applied to the semiconductor light emitting device chip 110, a current flows through the Zener diode 130 so that the semiconductor light emitting device chip 110 Protect.

In addition, the zener diode 130 has a plurality of zener electrodes 131, one of the plurality of zener electrodes 131 is in contact with a corresponding one of the plurality of pads 121, and a plurality of zener electrodes 131 The other Zener electrode 131 of the electrodes 131 is electrically connected to be connected to the corresponding at least one semiconductor light emitting device chip 110 in reverse parallel. At this time, one of the plurality of zener electrodes 131 may be connected to one of the plurality of electrodes 121 of the semiconductor light emitting device chip 110 and may be connected to one of the plurality of pads 121, or It may be connected to the electrical connection 123. The Zener diode 130 will be described in detail in FIG. 14.

8 is a diagram illustrating still other examples of a semiconductor light emitting device according to the present disclosure.

8A illustrates an example in which a plurality of paths are formed between the plurality of pads 121 and the plurality of electrodes 111 in the electrical connection 123.

8(b) shows an example in which the electrical connection 123 is formed in a net shape. The pattern of the electrical connection 123 is hexagonal and is an example formed in a honeycomb shape. This is an example in which the pattern is formed in a certain size. In the net type, the back side of the semiconductor light emitting device 100 is more visible.

9 is a diagram illustrating still other examples of a semiconductor light emitting device according to the present disclosure.

9A is a diagram illustrating an example of a semiconductor light emitting device 100 including a plurality of semiconductor light emitting device chips 110 according to the present disclosure.

At least one semiconductor light emitting device chip 110 includes a first semiconductor light emitting device chip 110 and a third electrode 111-3 including a first electrode 111-1 and a second electrode 111-2 The second semiconductor light emitting device chip 110 including the fourth electrode 111-4 and the third semiconductor light emitting device chip 110 including the fifth electrode 111-5 and the sixth electrode 111-6 It may include. The first electrode 111-1 and the second electrode 111-2 of one semiconductor light emitting device chip 110 have different polarities. For example, the first electrode 111-1 of the first semiconductor light emitting device chip 110 may be a-electrode, and the second electrode 111-2 may be a + electrode. The third electrode 111-3 of the second semiconductor light emitting device chip 110 may be a-electrode, and the fourth electrode 111-4 may be a + electrode. The fifth electrode 111-5 of the third semiconductor light emitting device chip 110 may be a-electrode, and the sixth electrode 111-6 may be a + electrode.

The plurality of pads 121 includes a first pad 121-1, a second pad 121-2, a third pad 121-3 and a fourth pad 121-4. The first pad 121-1 is electrically connected to the first electrode 111-1, the third electrode 111-3, and the fifth electrode 111-5. The second pad 121-2 is electrically connected to the second electrode 111-2. The third pad 121-3 is connected to the fourth electrode 111-4. The fourth pad 121-4 is connected to the sixth electrode 111-6. The first pad 121-1, the second pad 121-2, the third pad 121-3, and the fourth pad 121-4 may have different polarities. The second pad 121-2, the third pad 121-3, and the fourth pad 121-4 have the same polarity, but the first semiconductor light emitting device chip 110, the second semiconductor light emitting device chip 110, and They are formed separately to control ON/OFF of the third semiconductor light emitting device chip 110, respectively.

The electrical connection 123 includes a first electrical connection 123-1, a second electrical connection 123-2, a third electrical connection 123-3, and a fourth electrical connection 123-4. The first electrical connection 123-1 electrically connects the first pad 121-1, the first electrode 111-1, the third electrode 111-3, and the fifth electrode 111-5 do. The second electrical connection 123-2 electrically connects the second pad 121-2 and the second electrode 111-2. The third electrical connection 123-3 electrically connects the third pad 121-3 and the fourth electrode 111-4. The fourth electrical connection 123-4 electrically connects the fourth pad 121-4 and the sixth electrode 111-6.

The plurality of semiconductor light emitting device chips 110 may be turned on/off in various combinations in order to emit white light or various colors. A plurality of semiconductor light emitting device chips 110 are gathered in the center and provided in the semiconductor light emitting device 100, one semiconductor light emitting device chip 110; 110-1, 110-2, 110-3 and one pad 121; 121-1, 121 A certain distance may be formed between -2,121-3).

Since the plurality of semiconductor light emitting device chips 110 are well-mixed to form one pixel, the plurality of semiconductor light emitting device chips 110 must be provided in the center of the semiconductor light emitting device 100. If a plurality of pads 121 are provided under the plurality of semiconductor light emitting device chips 110 and the plurality of pads 121 enter the SMT process, a problem in that a plurality of nearby pads 121 may be shorted may occur. . Accordingly, the present disclosure, characterized in that the electrical connection 123 is made between the plurality of pads 121 and the semiconductor light emitting device chip 110, includes a plurality of mini or micro semiconductor light emitting device chips 110 in the center as shown in FIG. It is more effective if you put them together.

9B is a diagram illustrating another example of a semiconductor light emitting device 100 including a plurality of semiconductor light emitting device chips 110 according to the present disclosure.

The electrical connection 123 formed of a single line described in FIG. 9A may be formed in a net shape to solve the problem of being disconnected. The electrical connection 123 is formed thinner and the total area in which the electrical connection 123 is formed is formed wider. As described in FIG. 7, in the electrical connection 123, a plurality of paths are formed between the plurality of pads 121 and the plurality of electrodes 111, so that even if a part of the thin electrical connection 123 is disconnected, there is a probability that a connected path exists. It gets higher. Therefore, the probability that electricity does not pass through the semiconductor light emitting device chip 110 is lowered.

The electrical connection 123 may be formed to have a certain pattern. The electrical connection 123 may be formed in a net shape. The size of the pattern of the electrical connection 123 contacting the plurality of pads 121 or the plurality of electrodes 111 is smaller than the size of the pattern not contacting the plurality of pads 121 or the plurality of electrodes 111 . The detailed reason will be described in FIG. 10.

The first electrical connection 123-1 to the fourth electrical connection 123-4 are formed in a net shape. The net type is formed by connecting a plurality of patterns. The pattern may be formed as a figure, and examples of the pattern will be described in FIG. 11. Forming the first electrical connection 123-1 to the fourth electrical connection 123-4 in a net shape is the electrical connection 123 of FIG. 9(a) when the semiconductor light emitting device 100 is used in a transparent display. ), the back side of the semiconductor light emitting device 100 of FIG. 9(b) may be more visible than the back side of the semiconductor light emitting device 100 of FIG. 9(a).

Fig. 10 is a diagram explaining in detail A in Fig. 9B.

A third electrical connection 123-3 is positioned between the third pad 121-3 and the fourth electrode 111-4. Among the third electrical connections 123-3, the size of the pattern a contacting the third pad 121-3 and the fourth electrode 111-4 is reduced. This is because more paths can be formed only when the size of the pattern (a) contacting the third pad 121-3 and the fourth electrode 111-4 is reduced. Since the area of the third electrical connection 123-3 that can reach the third pad 121-3 and the fourth electrode 111-4 is limited, the third pad 121- The size of the pattern (a) in contact with 3) and the third electrode 111-3 may be formed to be smaller than that of the non-contact pattern (b). Therefore, the probability that the third electrical connection 123-3 between the first pad 121-1 and the third electrode 111-3 is disconnected can be lowered, and more electrical than forming a pattern having one size A plurality of paths may be formed in the connection 121.

11 is a diagram illustrating examples of patterns according to the present disclosure.

The pattern can be formed in various shapes. It may be formed in a variety of squares as shown in FIG. 11(a)(b), a hexagonal shape as in FIG. 11(c), a circle as in FIG. 11(d), and a triangle as in FIG. 11(e). The shape of the pattern is not limited to the illustrated drawings.

12 is a diagram illustrating an example of a method of manufacturing a semiconductor light emitting device according to the present disclosure.

In the method of manufacturing a semiconductor light emitting device 100 including at least one semiconductor light emitting device chip 110, first, a substrate 140 is prepared as shown in FIG. 12(a). The substrate 140 is then temporarily fixed to the semiconductor light emitting device chip 110, and may be, for example, a silicon tape. The substrate 140 is not electrically connected to the semiconductor light emitting device chip 110.

Thereafter, at least one semiconductor light emitting device chip 110 is provided on the substrate 140 as shown in FIG. 12(b). In this case, although not shown, a zener diode 130 (refer to FIG. 7) may be provided on the substrate 140. The Zener diode 130 may be provided to correspond to at least one semiconductor light emitting device chip 110 and may include a Zener diode 130 to be separated from the at least one semiconductor light emitting device chip 110 by a predetermined distance.

Thereafter, the encapsulant 150 is provided on the substrate 140 and at least one semiconductor light emitting device chip 110 as shown in FIG. 12C. The semiconductor light emitting device chip 110 may be fixed by covering the encapsulant 150 on the substrate 140.

Thereafter, the substrate 140 is removed as shown in FIG. 12(d). Since it is a configuration for temporarily fixing the semiconductor light emitting device chip 110, it can be removed.

Thereafter, as shown in FIG. 12(e), a plurality of pads 121 and a plurality of pads 121 and at least one or more semiconductor light emitting device chips 110 separated from the semiconductor light emitting device chip 110 in the encapsulant 150 An electrical connection 123 is formed between them. After the encapsulant 150 is formed, a plurality of pads 121 and electrical connections 123 are formed under the semiconductor light emitting device chip 110 and the encapsulant 150, so a plurality of pads 121 and electrical connections 123 Silver protrudes from the encapsulant 150. Since the plurality of pads 121 and the electrical connection 123 are formed on one surface of the encapsulant 150 by a method such as vapor deposition, the plurality of pads 121 and the electrical connection 123 are provided on the same plane.

13 is a diagram illustrating another example of a method of manufacturing a semiconductor light emitting device according to the present disclosure.

In a method of manufacturing a semiconductor light emitting device 100 including at least one semiconductor light emitting device chip 110, first, a substrate 140 is prepared as shown in FIG. 13(a). The substrate 140 is then temporarily fixed to the semiconductor light emitting device chip 110, and may be, for example, a silicon tape. The substrate 140 is not electrically connected to the semiconductor light emitting device chip 110.

Thereafter, as shown in FIG. 13(b), a plurality of pads 121 and a plurality of pads 121 and at least one or more semiconductor light emitting device chips ( 110) to form an electrical connection 123 to connect. Since the plurality of pads 121 and the electrical connection 123 are formed on one surface of the substrate 140 by a method such as vapor deposition, the plurality of pads 121 and the electrical connection 123 are provided on the same plane.

Thereafter, at least one semiconductor light emitting device chip 110 is provided on the substrate 140 as shown in FIG. 13(c). The semiconductor light emitting device chip 110 may be positioned to contact the electrical connection 123. In this case, although not shown, a zener diode 130 corresponding to at least one semiconductor light emitting device chip 110 may be provided on the plurality of pads 121.

Thereafter, as shown in FIG. 13D, an encapsulant 150 is provided on the substrate 140 and at least one semiconductor light emitting device chip 110.

Thereafter, the substrate 140 is removed as shown in FIG. 13(e). After forming the plurality of pads 121 and the electrical connection 123 and covering the encapsulant 150, the plurality of pads 121 and the electrical connection 123 are provided in the encapsulant 150 and the substrate 140 In the case of removing the plurality of pads 121 and the electrical connection 123, only one surface that was in contact with the substrate 140 is exposed.

It is preferable that the plurality of pads 121 and the electrical connection 123 are provided in the encapsulant 150. This is because when the plurality of pads 121 and the electrical connection 123 protrude out of the encapsulant 150 as shown in FIG. 12(e), the adhesion between the encapsulant 150 and the plurality of pads 121 and the electrical connection 123 Because these are weak and can be separated from each other.

14 is a diagram illustrating a Zener diode according to the present disclosure.

14(a) is a diagram illustrating an example in which a Zener diode is mounted in a conventional semiconductor light emitting device.

A hole (H) is provided in the PCB substrate 240, and an electrical connection is formed along the hole (H) while forming the pad 221 provided under the PCB substrate 240, and to the top surface of the PCB substrate 240. An electrical connection is made to protrude. The pad electrode 223 is formed on the upper surface of the PCB substrate 240 so as to be connected to the pad 221, and the pad electrode 223 is also formed to protrude by the protruding electrical connection. Therefore, when the Zener electrode 131 of the Zener diode 130 is attached to the pad electrode 223, a gap is created, and the Zener diode 130 is liable to fall off. Accordingly, although not shown, the zener diode 130 is provided at a portion other than the pad electrode 223 avoiding the hole H, and the zener diode 130 is provided at a position not overlapping with the pad 221.

FIG. 14(b) is a diagram illustrating a section BB′ of FIG. 7.

One of the zener electrodes 131 of the zener diode 130 is in contact with one pad 121. This disclosure is possible because the pad 121 is formed flat without the hole H (FIG. 14(a)) and the pad electrode 223 (FIG. 14(a)).

The pad 121 and the zener diode 130 are configured to increase optical loss, and the pad 121 is formed flat so that the zener diode 130 can be positioned within the pad 121 on a plane, so that the pad 121 It is formed so that the area of and the area of the zener diode 130 overlaps, thereby reducing optical loss. In addition, when applied to a transparent display, since many portions of the pad 121 and the zener diode 130 overlap, the transparency of the semiconductor light emitting device 100 can be increased.

15 is a diagram illustrating another example of a semiconductor light emitting device according to the present disclosure.

FIG. 15A is a bottom view showing the lower surface of the semiconductor light emitting device 100, and is an example in which one semiconductor light emitting device chip 110 is provided in the semiconductor light emitting device 100. Fig. 15(b) is a view showing a cross section AA' of Fig. 15(a).

The semiconductor light emitting device 100 may include an insulating layer 160 covering the electrical connection 123 and exposing the plurality of pads 121. By covering the electrical connection 123 with the insulating layer 160, it is possible to reduce the risk of a short circuit during soldering. Although an example in which the electrical connection 123 and the pad 121 are provided inside the encapsulant 150 is shown, it can also be applied to an example in which the electrical connection 123 and the pad 121 protrude from the encapsulant 150. The insulating layer 160 may be formed after FIGS. 12(e) and 13(e) by using a method such as silk screen printing.

It is preferable that the height h of the insulating layer 160 is formed to be 10 μm or less. Since the insulating layer 160 is formed so that the plurality of pads 121 are exposed after FIG. 12(e) or 13(e), the plurality of pads 121 may be formed lower than the insulating layer 160. When electrically connected to the outside by soldering, the height h of the insulating layer 160 is preferably as thin as 10 μm or less in order for the solder material to make good contact with the plurality of pads 121. Alternatively, after the formation of the insulating layer 160, the height of the plurality of pads 121 may be increased as shown by the dotted line 122 by a method such as plating to be formed equal to or higher than the height h of the insulating layer 160.

The insulating layer 160 may be formed of at least one of a transparent material or an opaque material. When the insulating layer 160 is formed of a transparent material, the semiconductor light emitting device 100 may emit light on six surfaces. On the other hand, when the insulating layer 160 is formed of an opaque material, the semiconductor light emitting device 100 may emit light on five surfaces. When applied to a transparent display, it may be necessary to prevent the light from exiting the back side. Therefore, the insulating layer 160 may be formed of an opaque material. However, for example, if the size of the semiconductor light emitting device is 500umX500um or less, the semiconductor light emitting device is not easily recognized even if the insulating layer is opaque, but as in the present disclosure, the gap between the pad and the semiconductor light emitting device chip is increased, When the size is larger than before (for example, a semiconductor light emitting device having a size of 1500umX1500um), the semiconductor light emitting device 100 can be well recognized. In order to solve such a problem, only the portion 170 indicated by the dotted line in FIG. 15(a) of the insulating layer 160 under the semiconductor light emitting device chip 110 is formed of an opaque material, and the remaining portions are formed of a transparent material. I can. In this case, the light emitted from the semiconductor light emitting device chip 110 is prevented from exiting the bottom of the semiconductor light emitting device 100, and the remaining portions are transparent, so that even when the size of the semiconductor light emitting device is increased by the present disclosure, It can be applied to transparent displays that require no light to emit. At this time, it is preferable that the size of the portion 170 indicated by the dotted line is 300um or less.

15(c) is a bottom view showing the lower surface of the semiconductor light emitting device 100, and is an example in which a plurality of semiconductor light emitting device chips 110 are provided in the semiconductor light emitting device 100. FIG. 15(d) is a diagram showing a section BB′ of FIG. 15(c).

15(a) and 15(b) may be applied to FIGS. 15(c) and 15(d).

16 to 18 are diagrams illustrating still another example of a semiconductor light emitting device according to the present disclosure.

16 shows a plan view of the semiconductor light emitting device 200, FIG. 17 shows a cross-sectional view AA' of FIG. 16, and FIG. 18 shows a rear view of the semiconductor light emitting device 200.

The semiconductor light emitting device 200 includes a substrate 210, a semiconductor light emitting device chip 220, a pad 230, an electrical connection 240, and an encapsulant 250.

The substrate 210 includes one or more holes 213 penetrating the upper portion 211 of the substrate 210 and the lower portion 212 of the substrate 210, and is formed to be rigid. The substrate 210 is advantageous as the difference between the electrical connection 240 and the thermal strain coefficient decreases. This is because the substrate 210 and the electrical connection 240 must be designed in consideration of the tolerance for the large difference in the coefficient of thermal deformation. Therefore, the substrate 210 is preferably made of glass having a small difference between the electrical connection 240 and the coefficient of thermal deformation.

The semiconductor light emitting device chip 220 is provided on the substrate 210 and includes an electrode 221. For example, the semiconductor light emitting device chip 220 may include a first electrode 221-1 and a second electrode 221-2.

The pad 230 is provided between the upper pad 232 provided on the upper part 211 of the substrate 210, the lower pad 233 provided on the lower part 212 of the substrate 210, and the upper pad and the lower pad 233. It may include a through connection 231 provided. The pad 230 is formed at a predetermined distance L apart from the electrode 221 of the semiconductor light emitting device chip 220 on a plane. The pad 230 is connected from the upper part 211 to the lower part 212 through one or more holes 213 of the substrate 210. The pad 230 is electrically connected to the outside. Of course, the upper pad 232 can be omitted. Instead of the upper pad 232, an electrical connection 240 may be connected to the upper part of the hole 213.

The electrical connection 240 may be provided between the pad 230 and the electrode 221 of the at least one semiconductor light emitting device chip 220. The electrical connection 240 electrically connects the pad 230 and the electrode 221. The electrical connection 240 may be formed of a light-transmitting material, for example, indium tin oxide (ITO). ITO functions as a solder resist, so that solder does not adhere without using a separate solder resist.

The encapsulant 250 covers at least one semiconductor light emitting device chip 220, electrical connection 240, and upper pad 232, and the encapsulant 250 covers at least one semiconductor light emitting device chip 220, electrical connection (240) and the upper pad 232 can be protected.

The semiconductor light emitting device 200 prior to FIG. 15 had a problem in that the size of the semiconductor light emitting device 200 changes due to contraction of the encapsulant 250 because there is no hard part. As the size of the semiconductor light emitting device 200 changes, there is a problem in that a short circuit occurs as the distance between electrodes is changed, or the semiconductor light emitting device 200 is electrically connected to another place and does not operate properly. In order to solve this problem, the substrate 210 that is not affected by the shrinkage of the encapsulant 250 is provided, so that the size of the semiconductor light emitting device 200 is not changed.

In addition, in general, it takes a long time to form the hole 213 in the substrate 210 made of glass by using a laser, and it is difficult to easily form the hole 213. When the substrate 210 of the glass is a photosensitive glass, a hole 213 may be simply formed in the substrate 210 through wet etching. Through this, the process of forming the hole 213 in the substrate 210 can be simplified, and cost can be reduced in that an expensive laser device is not used.

19 to 20 are diagrams showing still another example of a method of manufacturing a semiconductor light emitting device according to the present disclosure

First, a substrate 210 as shown in FIG. 19(a) is prepared.

Thereafter, a hole 213 is formed in the substrate 210 prepared as shown in FIG. 19(b). The hole 213 is formed to penetrate the upper 211 and the lower 212 of the substrate 210. A through connection 231 may be formed in the hole 213. Although a method of forming the hole 213 is not shown, briefly described, in the case of a positive case, a portion in which the hole 213 is to be formed is exposed, and the exposed portion can be etched (etched) by an etching solution. In addition, the hole 213 may be filled with a conductive material to form the through connection 231, and imbalance on the surface of the substrate 210 and foreign matter (conductive material) on the surface of the substrate 210 may be removed.

Thereafter, as shown in FIG. 19(c), a pad 230 is formed on the substrate 210. The pad 230 may be formed on the upper portion 211 and lower portion 212 of the substrate 210, and the pad 230 of the lower portion 212 is electrically connected to the outside. A through connection 231 is formed in the hole 213 electrically connecting the pad 230 of the upper 211 and the lower 212. A through connection 231 is formed between the pad 230 of the upper 211 and the lower 212. In addition, an electrical connection 240 electrically connected to the pad 230 is formed. The electrical connection 240 is electrically connected to the semiconductor light emitting device chip 220.

Then, solder (s) is deposited on the electrical connection 230 as shown in FIG. 20(a). The solder (s) may be a SnCuNi alloy (SAC; an example).

Thereafter, as shown in FIG. 20B, the semiconductor light emitting device chip 220 is positioned so that the electrode 221 of the semiconductor light emitting device chip 220 is placed on the solder s. The solder (s) is melted in the present step or melted in the step prior to the present step to bond the electrode 221 and the electrical connection 230 of the semiconductor light emitting device chip 220.

Thereafter, the encapsulant 250 is covered on the semiconductor light emitting device chip 220 as shown in FIG. 20(c).

In the present invention, the hole 213 is formed in the substrate 210 by a positive process in which a portion receiving light is etched, but it will be described separately that a hole can be formed even by using a negative process in which a portion receiving light is etched. There is no need to do it.

21 is a diagram illustrating another example of a semiconductor light emitting device according to the present disclosure.

The semiconductor light emitting device 200 includes a plurality of semiconductor light emitting device chips 220.

The plurality of semiconductor light emitting device chips 220 include a first semiconductor light emitting device chip 220-1, a second semiconductor light emitting device chip 220-2, and a third semiconductor light emitting device chip 220-3.

The first semiconductor light emitting device chip 220-1 includes a first electrode 221-1 and a second electrode 221-2, and the second semiconductor light emitting device chip 220-2 is a third electrode 221 -3) and the fourth electrode 221-4, and the third semiconductor light emitting device chip 220-3 may include a fifth electrode 221-5 and a sixth electrode 221-6. .

The electrical connection 240 includes a first electrical connection 240-1, a second electrical connection 240-2, a third electrical connection 240-3, and a fourth electrical connection 240-4.

The first electrical connection 240-1 is provided between the first electrode 221-1, the third electrode 221-3 and the fifth electrode 221-5 and the first upper pad 232-1 , The first electrode 221-1, the third electrode 221-3, and the fifth electrode 221-5 and the first upper pad 232-1 are electrically connected. The second electrical connection 240-2 is provided between the second electrode 221-2 and the second upper pad 232-2, and the second electrode 221-2 and the second upper pad 232-2 ) Are electrically connected. The third electrical connection 240-3 is provided between the fourth electrode 221-4 and the third upper pad 232-3, and the fourth electrode 221-4 and the third upper pad 232-3 ) Are electrically connected. The fourth electrical connection 240-4 is provided between the sixth electrode 221-6 and the fourth upper pad 232-4, and the sixth electrode 221-6 and the fourth upper pad 232-4 ) Are electrically connected.

22 is a diagram illustrating another example of a semiconductor light emitting device according to the present disclosure.

FIG. 22(a) is a view showing a cross-section AA' of the semiconductor light emitting device 200 of FIG. 25(b), and FIG. 22(b) is a cross-sectional view of BB' of the semiconductor light emitting device 200 of FIG. 25(b). It is a figure shown.

The semiconductor light emitting device 200 includes a substrate 210, at least one semiconductor light emitting device chip 220 (FIG. 25), a pad 230, a through connection 231, a driving device 260, a connection layer 290, and 1 encapsulant 251, and a second encapsulant 252.

The substrate 210 includes an upper portion 211 and a lower portion 212, and a groove 215 is formed in the lower portion 212 of the substrate 210. The substrate 210 is formed to be rigid, and the substrate 210 includes a plurality of second holes 217 and a plurality of first holes 219 penetrating the substrate 210. The plurality of second holes 217 are formed outside the groove 215, and the plurality of first holes 219 are formed above the groove 215. The substrate 210 may be formed of glass, and is preferably formed of photosensitive glass. When the substrate 210 is formed of photosensitive glass, it may be easier to form the plurality of second holes 217 and the plurality of first holes 219 in the substrate 210. Therefore, there is an advantage of simplifying the cost and process. The problem with the substrate 210 formed of glass is described in FIG. 18, and there is a problem similar to that of FIG. 18.

As for the number of second holes 217 and the number of first holes 219, as shown in the drawing, six second holes 217 may be formed, and nine first holes 219 may be formed. The number of second holes 217 and the number of first holes 219 may vary depending on the driving element 260.

A through connection 231 is provided inside the first hole 219 and the second hole 217. The through connection 231 is formed of an electrically conductive material.

At least one semiconductor light emitting device chip 220 emits light, is provided on the substrate 210, and includes a plurality of electrodes 221. A plurality of at least one semiconductor light emitting device chip 220 may be provided. For example, the plurality of semiconductor light emitting device chips 220 may emit RED, GREEN, and BLUE light.

The pad 230 is provided on the lower portion 212 of the substrate 210, contacts the outside (eg, PCB, submount, etc.), and is electrically connected to the outside. On a plane, the electrodes 221 and the pads 230 of the semiconductor light emitting device chip 220 are formed at a predetermined distance apart. Light may pass between the plurality of electrodes 221 and the pad 230. In addition, among the pads 230, the pad 230 around the driving element 260 may be formed to contact the driving element 260, and the heat generated from the driving element 260 is formed of metal. By transmitting to the outside through, the heat dissipation effect of the driving element 260 can be increased. In particular, the pad 230 and the driving element 260 are insulated from each other and are not electrically.

The electrical connection 240 is formed on the upper portion 211 of the substrate 210 and is formed between the plurality of second holes 217 and the plurality of first holes 219. The electrical connection 240 may be formed of a light-transmitting material that passes light. For example, the electrical connection 240 may be ITO. Through this, the electrical connection 240 may be formed of a metal mesh, and the electrical connection 240 formed of a metal mesh may increase the transparency of the semiconductor light emitting device 200.

The electrical connection 240 electrically connects the through connection 231 of the first hole 219 and the through connection 231 of the second hole 217. The through connection 231 includes a first through connection 231-1 and a second through connection 231-2. The first through connection 231-1 is covered by the electrical connection 240, and the second through connection 231-2 is not covered by the electrical connection 240. Thereafter, it is denoted as a first through connection 231-1 covered by the electrical connection 240. The through connection 231 not covered by the electrical connection 240 is hereinafter referred to as a second through connection 231-2.

The driving device 260 is provided in the groove 215 and is electrically connected to the pad 230 and the semiconductor light emitting device chip 220. The driving device 260 may control ON/OFF and brightness of the semiconductor light emitting device chip 220.

The connection layer 290 includes an electrical connection 240, an insulating layer 270, and a metal layer 280 (FIG. 4(b)).

The electrical connection 240 is provided on the upper portion 211 of the substrate 210, and electrically connects the pad 230, the driving device 260, and the semiconductor light emitting device chip 220.

The insulating layer 270 exposes the first hole 219 not connected to the electrical connection 240 and covers the electrical connection 240 to expose a part of the electrical connection 240. The insulating layer 270 may be formed of a material that is transparent and does not conduct electricity. Accordingly, the insulating layer 270 is preferably a material capable of a pattern process, and, for example, the insulating layer 270 may be formed by depositing an epoxy-based PR or SiO ₂ .

The metal layer 280 is formed between the exposed electrical connection 241 and the electrode 221 of the semiconductor light emitting device chip 220, and between the exposed first hole 219 and the electrode 221 of the semiconductor light emitting device chip 220. Is formed. The metal layer 280 may include a first metal part 281, a second metal part 282, a third metal part 283, and a fourth metal part 284. In FIG. 22, only the first metal part 281, the second metal part 282, and the fourth metal part 284, which are some of them, are shown, which will be described in detail in FIG. 24(b).

The first encapsulant 251 is provided on the upper portion 211 of the substrate 210 and may cover the semiconductor light emitting device chip 220.

The second encapsulant 252 is provided in the groove 215 and may cover the driving element 260 located in the groove 215. In addition, the driving device 260 may directly contact the pad 230, and the second encapsulant 252 may wrap the driving device 260 so as to expose the lower portion 261 of the driving device 260.

The first encapsulant 251 and the second encapsulant 252 may be formed of the same material. For example, the first encapsulant 251 and the second encapsulant 252 may be of a polymer type such as epoxy or silicone.

Although not shown, when the metal layer 280 is not formed, the semiconductor light emitting device chip 220 has the first hole 219 exposed by the insulating layer 270 and the electrical connection exposed by the insulating layer 270 ( 241) and each may be electrically connected.

FIG. 22(b) shows a fourth metal part 284 electrically connected to the exposed electrical connection 241 and a first metal layer 281 electrically connected to the exposed through connection 232. This will be described in detail in FIG. 24.

23 to 25 are diagrams illustrating still another example of a method of manufacturing a semiconductor light emitting device according to the present disclosure.

As shown in FIG. 23(a), a substrate 210 having a groove 215 formed in a lower portion 212 (FIG. 22) of the substrate 210 is prepared. The substrate 210 is formed inside a plurality of second holes 217 and grooves 215 penetrating through the upper portion 211 (FIG. 22) and the lower portion 212 of the substrate 210 to form the substrate 210. It includes a plurality of first holes 219 passing through. A through connection 231 is formed in the plurality of first holes 219 and the plurality of second holes 217. The through connection 231 is formed of a conductive material. The groove 215 may be formed after the through connection 231 is formed.

The through connection 231 and the plurality of second holes 217 of the plurality of first holes 219 (FIG. 23(a)) formed in FIG. 23(b) and the upper part 211 of the substrate 210; FIG. 23(a) )) of the through connection 231 is electrically connected by an electrical connection 240. Some of the through connections 231 are not covered by the electrical connection 240, which is the second through connection 231.

24(a), an insulating layer 270 is formed over the electrical connection 240. The insulating layer 270 is formed except for the first hole 219 not connected by the electrical connection 240. At the same time, the insulating layer 270 is formed excluding a part of one electrical connection 240. That is, the through connection 231 provided in the first hole 219 is exposed, and the exposed second through connection 231-2 is electrically connected to the semiconductor light emitting device chip 220. Electrical connection 240 includes an exposed electrical connection 241 that is not covered by the insulating layer 270.

As shown in FIG. 24(b), a metal layer 280 is formed. The metal layer 280 is in contact with the plurality of electrodes 221 (FIG. 25) of the plurality of semiconductor light emitting device chips 220 (FIG. 25). The metal layer 280 may be formed wider than the plurality of electrodes 221 of the semiconductor light emitting device chip 220, but since the metal layer 280 absorbs light, it is preferable to have a minimum width. The metal layer 280 may be formed to have a size such that one electrode 221 may contact each of the plurality of first holes 219 (FIG. 24A). The metal layer 280 electrically formed with the exposed electrical connection 241 (FIG. 24(a)) may be formed in a size such that the plurality of semiconductor light emitting device chips 220 can contact each other.

For example, the metal layer 280 may include a first metal part 281, a second metal part 282, a third metal part 283, and a fourth metal part 284.

As shown in FIG. 25A, a plurality of semiconductor light emitting device chips 220 are respectively in contact with the metal layer 280.

For example, the plurality of semiconductor light emitting device chips 220 include a first semiconductor light emitting device chip 220-1, a second semiconductor light emitting device chip 220-2, and a third semiconductor light emitting device chip 220-3. Can include. The first semiconductor light emitting device chip 220-1 includes a first electrode 221-1 and a second electrode 221-2, and the second semiconductor light emitting device chip 220-2 is a third electrode 221 -3) and a fourth electrode 221-4, and the third semiconductor light emitting device chip 220-3 includes a fifth electrode 221-5 and a sixth electrode 221-6.

The first metal part 281 (FIG. 24) to the third metal part 283 (FIG. 24) contact the exposed through connection 232, and the fourth metal part 284 (FIG. 24) is connected to the electrical connection 241 I can contact you.

The first metal part 281 is electrically connected to the first electrode 221-1 of the first semiconductor light emitting device chip 220-1. The second metal part 282 is electrically connected to the third electrode 221-3 of the second semiconductor light emitting device chip 220-2. The third metal part 283 is electrically connected to the fifth electrode 221-5 of the third semiconductor light emitting device chip 220-3. In addition, the fourth metal part 284 is a second electrode 221-2 of the first semiconductor light emitting device chip 220-1 and a fourth electrode 221-4 of the second semiconductor light emitting device chip 220-2. ) And the sixth electrode 221-6 of the third semiconductor light emitting device chip 220-3.

As shown in FIG. 25(b), a first encapsulant 251 is provided to cover the semiconductor light emitting device chip 220, the metal layer 280, and the insulating layer 270 (FIG. 24(a)). Although not shown, a second encapsulant 252 (FIG. 22) may be provided at the lower portion 212 (FIG. 22) of the substrate 210 (FIG. 22). In addition, after the driving element 260 (FIG. 23) is provided in the groove 215 (FIG. 22) of the substrate 210 in FIG. 23(a), the second encapsulant 252 may be provided.

Hereinafter, various embodiments of the present disclosure will be described.

(1) A semiconductor light emitting device, comprising: a hard substrate having a plurality of second holes penetrating an upper portion and a lower portion thereof and a groove formed at a lower portion thereof; a substrate including a plurality of first holes formed inside the groove in a plan view; At least one semiconductor light emitting device chip provided on the substrate and including a plurality of electrodes; A pad formed at a distance from the plurality of electrodes on a plane and electrically connected to the outside; A through connection formed in a plurality of first holes and a plurality of second holes and including a first through connection and a second through connection; A driving device provided in the groove and electrically connected to the pad and the semiconductor light emitting device chip; And a connection layer provided on the substrate and electrically connecting the pad, the driving device, and the semiconductor light emitting device chip, wherein the connection layer is provided on the substrate, and includes a first through connection and a plurality of first holes. Electrical connection for electrically connecting the first through connection of the 2 holes; And, the second through connection of the first hole that is not connected to the electrical connection is exposed, and an insulating layer covering the electrical connection to expose a part of the electrical connection; The semiconductor light emitting device chip is a semiconductor light emitting device electrically connected to the second through connection exposed by the insulating layer and the electrical connection exposed by the insulating layer.

(2) a metal layer formed between the exposed electrical connection and the electrode of the semiconductor light emitting device chip, and between the second through connection and the electrode of the semiconductor light emitting device chip.

(3) The substrate is a semiconductor light emitting device formed of photosensitive glass.

(4) A plurality of at least one semiconductor light emitting device chip is provided, and the plurality of semiconductor light emitting device chips includes a first semiconductor light emitting device chip including a first electrode and a second electrode, a second semiconductor light emitting device chip including a third electrode and a fourth electrode. A semiconductor light emitting device chip, a third semiconductor light emitting device chip including a fifth electrode and a sixth electrode, and one of the second through-connections is electrically connected to the first electrode of the first semiconductor light emitting device chip, and the second The other of the through connection is electrically connected to the third electrode of the second semiconductor light emitting device chip, and the other of the second through connection is electrically connected to the fifth electrode of the third semiconductor light emitting device chip, and the electrical connection is A semiconductor light emitting device electrically connected to a second electrode of a first semiconductor light emitting device chip, a fourth electrode of a second semiconductor light emitting device chip, and a sixth electrode of a third semiconductor light emitting device chip.

(5) A first encapsulant covering at least one semiconductor light emitting device chip.

(6) a second encapsulant covering the driving device; a semiconductor light emitting device further provided.

(7) The electrical connection is a semiconductor light emitting device formed of a light-transmitting material.

(8) The substrate is a semiconductor light emitting device formed of glass.

(9) A semiconductor light emitting device having a larger number of first holes than the number of second holes.

(10) a metal layer formed between the exposed electrical connection and the electrode of the semiconductor light emitting device chip, and between the second through connection of the exposed first hole and the electrode of the semiconductor light emitting device chip, wherein the semiconductor light emitting device chip includes a first electrode And a first semiconductor light emitting device chip including a second electrode, a second semiconductor light emitting device chip including a third electrode and a fourth electrode, a third semiconductor light emitting device chip including a fifth electrode and a sixth electrode, , A first metal layer, a second metal layer and a third metal layer are formed in the plurality of second through connections, a fourth metal layer is formed in the exposed electrical connection, and the first metal layer is formed with the first electrode of the first semiconductor light emitting device chip. It is electrically connected, the second metal layer is electrically connected to the third electrode of the second semiconductor light emitting device chip, the third metal layer is electrically connected to the fifth electrode of the third semiconductor light emitting device chip, and the fourth metal layer is 1 A semiconductor light emitting device electrically connected to a second electrode of a semiconductor light emitting device chip, a fourth electrode of a second semiconductor light emitting device chip, and a sixth electrode of a third semiconductor light emitting device chip.

(11) A semiconductor light emitting device whose electrical connection is ITO.

According to one semiconductor light emitting device according to the present disclosure, upper and lower portions are electrically connected through holes formed in a substrate.

According to another semiconductor light emitting device according to the present disclosure, an electrode and a pad are connected by electrical connection.

According to another semiconductor light emitting device according to the present disclosure, shrinkage is not caused by the encapsulant by the rigidly formed substrate.

200: semiconductor light emitting device 211: upper portion 212: lower portion
220: semiconductor light emitting device chip 221: electrode 230: pad
231: through connection 232: exposed through connection
240: electrical connection 241: exposed electrical connection
250: encapsulant 260: driving element
270: insulating layer 280: metal layer
290: connection part

Claims (11)

In a semiconductor light emitting device,
A rigid substrate having a plurality of second holes passing through the upper and lower portions and a groove formed at the lower portion thereof, comprising: a substrate including a plurality of first holes formed inside the grooves on a plane;
At least one semiconductor light emitting device chip provided on the substrate and including a plurality of electrodes;
A pad formed at a distance from the plurality of electrodes on a plane and electrically connected to the outside;
A through connection formed in the plurality of first holes and the plurality of second holes and including a first through connection and a second through connection;
A driving device provided in the groove and electrically connected to the pad and the semiconductor light emitting device chip; And,
Includes; a connection layer provided on the substrate and electrically connecting the pad, the driving device, and the semiconductor light emitting device chip,
The connecting layer is:
An electrical connection provided on the substrate and electrically connecting the first through connection of the plurality of first holes and the first through connection of the plurality of second holes; And,
Including; an insulating layer covering the electrical connection so that the second through connection of the first hole not connected to the electrical connection is exposed, and a part of the electrical connection is exposed, and
The semiconductor light emitting device chip is a semiconductor light emitting device that is electrically connected to a second through connection exposed by an insulating layer and an electrical connection exposed by the insulating layer, respectively. The method according to claim 1,
A semiconductor light emitting device comprising: a metal layer formed between the exposed electrical connection and the electrode of the semiconductor light emitting device chip, and between the second through connection and the electrode of the semiconductor light emitting device chip. The method according to claim 1,
The substrate is a semiconductor light emitting device formed of photosensitive glass. The method according to claim 1,
A plurality of at least one semiconductor light emitting device chip is provided,
The plurality of semiconductor light emitting device chips include a first semiconductor light emitting device chip including a first electrode and a second electrode, a second semiconductor light emitting device chip including a third electrode and a fourth electrode, a fifth electrode and a sixth electrode. Including a third semiconductor light emitting device chip,
One of the second through connections is electrically connected to the first electrode of the first semiconductor light emitting device chip, and the other of the second through connections is electrically connected to the third electrode of the second semiconductor light emitting device chip, and the second through connection Another of the connections is electrically connected to the fifth electrode of the third semiconductor light emitting device chip,
The electrical connection is a semiconductor light emitting device electrically connected to a second electrode of the first semiconductor light emitting device chip, a fourth electrode of the second semiconductor light emitting device chip, and a sixth electrode of the third semiconductor light emitting device chip. The method according to claim 1,
A semiconductor light emitting device comprising a; a first encapsulant covering at least one semiconductor light emitting device chip. The method according to claim 1,
A semiconductor light emitting device further provided with a second encapsulant covering the driving device. The method according to claim 1,
The electrical connection is a semiconductor light emitting device formed of a light-transmitting material. The method according to claim 1,
The substrate is a semiconductor light emitting device formed of glass. The method according to claim 1,
A semiconductor light emitting device having a greater number of first holes than the number of second holes. The method according to claim 1,
A metal layer formed between the exposed electrical connection and the electrode of the semiconductor light emitting device chip, and between the second through connection of the exposed first hole and the electrode of the semiconductor light emitting device chip; and
The semiconductor light emitting device chip includes a first semiconductor light emitting device chip including a first electrode and a second electrode, a second semiconductor light emitting device chip including a third electrode and a fourth electrode, and a fifth electrode including a fifth electrode and a sixth electrode. 3 Including a semiconductor light emitting device chip,
A first metal layer, a second metal layer, and a third metal layer are formed in the plurality of second through connections, and a fourth metal layer is formed in the exposed electrical connection,
The first metal layer is electrically connected to the first electrode of the first semiconductor light emitting device chip, the second metal layer is electrically connected to the third electrode of the second semiconductor light emitting device chip, and the third metal layer is the third semiconductor light emitting device chip. Is electrically connected to the fifth electrode of, and the fourth metal layer is electrically connected to the second electrode of the first semiconductor light emitting device chip, the fourth electrode of the second semiconductor light emitting device chip, and the sixth electrode of the third semiconductor light emitting device chip. Semiconductor light emitting device. The method according to claim 1,
The electrical connection is a semiconductor light emitting device with ITO.

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